EMC2303 Multiple RPM-Based PWM Fan Controller for Three Fans PRODUCT FEATURES Datasheet General Description Features The EMC2303 is an SMBus compliant fan controller with (cid:132) Three Programmable Fan Control circuits (EMC2303) up to three independently controlled PWM fan drivers. — 4-wire fan compatible Each fan driver is controlled by a programmable — High speed PWM (26 kHz) — Low speed PWM (9.5Hz - 2240 Hz) frequency PWM driver and Fan Speed Control algorithm — Optional detection of aging fans that operates in either a closed loop fashion or as a — Fan Spin Up Control and Ramp Rate Control directly PWM-controlled device. — Alert on Fan Stall — Up to 3 Selectable Default Fan Speeds The closed loop Fan Speed Control algorithm (FSC) has the capability to detect aging fans and alert the system. (cid:132) Watchdog Timer It will likewise detect stalled or locked fans and trigger (cid:132) RPM-based fan control algorithm an interrupt. — 0.5% accuracy from 500 RPM to 16k RPM (external crystal oscillator) Additionally, the EMC2303 offers a clock output so that — 1% accuracy from 500 RPM to 16k RPM (internal clock) multiple devices may be chained and slaved to the (cid:132) SMBus 2.0 Compliant same clock source for optimal performance in large — Up to 6 selectable SMBus addresses distributed systems. — SMBus Alert compatible (cid:132) CLK Pin can provide a clock source output Applications (cid:132) Available in a 12-pin 4mm x 4mm QFN Lead-free (cid:132) Servers RoHS Compliant package (cid:132) Projectors (cid:132) Industrial and Networking Equipment (cid:132) Notebook Computers Block Diagram CLK TACH1 Tachometer Tach TACH2 Limit Measurement Registers ADDR_SEL TACH3 SMBus SMCLK Slave Protocol SMDATA PWM1 Fan Speed Control Algorithm ALERT# PWM PWM2 Fan Speed Control Algorithm Drivers PWM3 Fan Speed Control Algorithm DATASHEET SMSC EMC2303 Revision 1.3 (05-18-11)

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet Order Number: ORDERING NUMBER PACKAGE FEATURES EMC2303-1-KP-TR 12-pin QFN (Lead-free Three RPM-based fan speed control RoHS compliant) algorithms This product meets the halogen maximum concentration values per IEC61249-2-21 For RoHS compliance and environmental information, please visit www.smsc.com/rohs 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000 or 1 (800) 443-SEMI Copyright © 2011 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Revision 1.3 (05-18-11) 2 SMSC EMC2303 DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet Table of Contents Chapter1 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Chapter2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 SMBus Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Chapter3 Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 System Management Bus Interface Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1.1 SMBus Start Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1.2 SMBus Address and RD / WR Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1.3 SMBus Data Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1.4 SMBus ACK and NACK Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1.5 SMBus Stop Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1.6 SMBus Time-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1.7 SMBus and I2C Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 SMBus Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2.1 Write Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2.2 Read Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2.3 Send Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2.4 Receive Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2.5 Block Write Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2.6 Block Read Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2.7 Alert Response Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Chapter4 Product Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1 Fan Control Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2 PWM Fan Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3 RPM-based Fan Speed Control Algorithm (FSC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3.1 Programming the RPM-based Fan Speed Control Algorithm . . . . . . . . . . . . . . . . . . . . . 20 4.4 Tachometer Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.4.1 Stalled Fan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.4.2 Aging Fan or Invalid Drive Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.5 CLK Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.5.1 Pull Up Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.5.2 External Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.5.3 Internal Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.6 Spin Up Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.6.1 Power Up Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.7 Ramp Rate Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.8 Watchdog Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.8.1 Power Up Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.8.2 Continuous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Chapter5 Register Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1.1 Lock Entries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3 Fan Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3.1 Fan Status - 24h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3.2 Fan Stall Status - 25h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 SMSC EMC2303 3 Revision 1.3 (05-18-11) DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet 5.3.3 Fan Spin Status - 26h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.3.4 Fan Drive Fail Status - 27h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.4 Fan Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.5 PWM Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.5.1 PWM Polarity Config - 2Ah . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.5.2 PWM Output Config - 2Bh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.6 PWM Base Frequency Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.7 Fan Setting Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.8 PWM Divide Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.9 Fan Configuration 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.10 Fan Configuration 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.11 Gain Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.12 Fan Spin Up Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.13 Fan Max Step Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.14 Fan Minimum Drive Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.15 Valid TACH Count Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.16 Fan Drive Fail Band Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.17 TACH Target Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.18 TACH Reading Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.19 Software Lock Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.20 Product Features Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.21 Product ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.22 Manufacturer ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.23 Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Chapter6 Typical Operating Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Chapter7 Package Drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.1 EMC2303 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.2 Package Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Chapter8 Datasheet Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Revision 1.3 (05-18-11) 4 SMSC EMC2303 DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet List of Figures Figure1.1 EMC2303 Pin Diagram (12-Pin QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure3.1 SMBus Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure4.1 System Diagram of EMC2303 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure4.2 Spin Up Routine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure4.3 Ramp Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure7.1 Package Drawing - 12-Pin QFN 4mm x 4mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure7.2 Package Dimensions - 12-Pin QFN 4mm x 4mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure7.3 PCB Footprint - 12-Pin QFN 4mm x 4mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure7.4 EMC2303 Package Markings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 SMSC EMC2303 5 Revision 1.3 (05-18-11) DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet List of Tables Table1.1 Pin Description for EMC2303 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table1.2 Pin Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table2.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table2.2 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table2.3 SMBus Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table3.1 ADDR_SEL Pin Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table3.2 Protocol Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table3.3 Write Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table3.4 Read Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table3.5 Send Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table3.6 Receive Byte Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table3.7 Block Write Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table3.8 Block Read Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table3.9 Alert Response Address Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table4.1 Fan Controls Active for Operating Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table4.2 CLK Pin Pull-Up Decode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table5.1 EMC2303 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table5.2 Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table5.3 Fan Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table5.4 Fan Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table5.5 PWM Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table5.6 PWM Base Frequency Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table5.7 PWM_BASEx[1:0] Bit Decode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table5.8 Fan Driver Setting Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table5.9 PWM Divide Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table5.10Fan Configuration 1 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table5.11Range Decode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table5.12Minimum Edges for Fan Rotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table5.13Update Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table5.14Fan Configuration 2 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table5.15Derivative Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table5.16Error Range Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table5.17Gain Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table5.18Gain Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table5.19Fan Spin Up Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table5.20DRIVE_FAIL_CNT[1:0] Bit Decode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table5.21Spin Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table5.22Spin Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table5.23Fan Max Step Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table5.24Minimum Fan Drive Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table5.25Valid TACH Count Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table5.26Fan Drive Fail Band Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table5.27TACH Target Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table5.28TACH Reading Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table5.29Software Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table5.30Product Features Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table5.31ADDR_SEL Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table5.32FAN_SPD Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table5.33Product ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table5.34Manufacturer ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table5.35Revision Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table8.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Revision 1.3 (05-18-11) 6 SMSC EMC2303 DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet Chapter 1 Pin Description # 3 T 3 H M R C E W A L T P A 2 1 0 1 1 1 SMDATA 1 9 CLK EMC2303 SMCLK 2 12-QFN 8 TACH2 VDD 3 7 PWM2 4 5 6 L 1 1 E M H S W C _ A R P T D D A Figure1.1 EMC2303 Pin Diagram (12-Pin QFN) Table1.1 Pin Description for EMC2303 PIN NUMBER PIN NAME PIN FUNCTION PIN TYPE SMBus data input/output - requires 1 SMDATA DIOD (5V) external pull-up resistor SMBus clock input - requires external 2 SMCLK DI (5V) pull-up resistor 3 VDD Power Supply Power SMSC EMC2303 7 Revision 1.3 (05-18-11) DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet Table1.1 Pin Description for EMC2303 (continued) PIN NUMBER PIN NAME PIN FUNCTION PIN TYPE Address selection input - requires pull-up 4 ADDR_SEL AIO resistor Push-Pull PWM output driver for Fan 1 DO 5 PWM1 Open Drain PWM output driver for Fan 1 OD (5V) Open drain tachometer input for Fan 1- 6 TACH1 DI (5V) requires pull-up resistor Push-Pull PWM output driver for Fan 2 DO 7 PWM2 Open Drain PWM output driver for Fan 2 OD (5V) Open drain tachometer input for Fan 2 - 8 TACH2 DI (5V) requires pull-up resistor Clock input for tachometer measurement DI (5V) 9 CLK Push Pull Clock output to other fan controllers to cynchronize Fan Speed DO Control Active low interrupt - requires external 10 ALERT# OD (5V) pull-up resistor. Push-Pull PWM output driver for Fan 3 DO 11 PWM3 Open Drain PWM output driver for Fan 3 OD (5V) Open drain tachometer input for Fan 3 - 12 TACH3 DI (5V) requires pull-up resistor Bottom Pad GND Ground Power The pin types are described in detail below. All pins labeled with (5V) are 5V tolerant. APPLICATION NOTE: For the 5V tolerant pins that have a pull-up resistor, the voltage difference between VDD and the 5V tolerant pad must never be more than 3.6V. Revision 1.3 (05-18-11) 8 SMSC EMC2303 DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet Table1.2 Pin Types PIN TYPE DESCRIPTION Power This pin is used to supply power or ground to the device. AIO Analog input / output - this pin is used for analog signals Digital Input - this pin is used as a digital input. This pin is DI 5V tolerant. Push / Pull Digital Output - this pin is used as a digital DO output. It can both source and sink current. Digital Input / Open Drain Output this pin is used as a DIOD digital I/O. When it is used as an output, it is open drain and requires a pull-up resistor. This pin is 5V tolerant. Open Drain Digital Output - this pin is used as a digital OD output. It is open drain and requires a pull-up resistor. This pin is 5V tolerant. SMSC EMC2303 9 Revision 1.3 (05-18-11) DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet Chapter 2 Electrical Specifications Table2.1 Absolute Maximum Ratings Voltage on 5V tolerant pins (V ) -0.3 to 5.5 V 5VT_pin Voltage on 5V tolerant pins (|V - V |) (see Note2.1) 0 to 3.6 V 5VT_pin DD Voltage on VDD pin -0.3 to 4 V Voltage on any other pin to GND -0.3 to VDD + 0.3 V Package Thermal Resistance - Junction to Ambient (θ ) 50 °C/W JA Operating Ambient Temperature Range -40 to 125 °C Storage Temperature Range -55 to 150 °C ESD Rating, All Pins, HBM 2000 V Note: Stresses above those listed could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. Note2.1 For the 5V tolerant pins that have a pull-up resistor, the pull-up voltage must not exceed 3.6V when the EMC2303 is unpowered. 2.1 Electrical Specifications Table2.2 Electrical Specifications V = 3V to 3.6V, T = -40°C to 125°C, all Typical values at T = 27°C unless otherwise noted. DD A A CHARACTERISTIC SYMBOL MIN TYP MAX UNIT CONDITIONS DC Power Supply Voltage V 3 3.3 3.6 V DD Supply Current I 475 600 uA DD PWM Fan Driver PWM Resolution PWM 256 Steps PWM Duty Cycle DUTY 0 100 % RPM-based Fan Controller Tachometer Range TACH 480 16000 RPM Tachometer Setting Δ ±0.5 ±1 % External oscillator 32.768kHz TACH Accuracy Δ ±1 ±2 % Internal Oscillator TACH Input High Voltage V 2.0 V IH Revision 1.3 (05-18-11) 10 SMSC EMC2303 DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet Table2.2 Electrical Specifications (continued) V = 3V to 3.6V, T = -40°C to 125°C, all Typical values at T = 27°C unless otherwise noted. DD A A CHARACTERISTIC SYMBOL MIN TYP MAX UNIT CONDITIONS Input Low Voltage V 0.8 V IL Output High Voltage VDD - 8 mA current drive V V OH 0.4 Output Low Voltage V 0.4 V 8 mA current sink OL Leakage current ALERT# pin Powered and unpowered I ±5 uA LEAK 0°C < TA < 85°C pull-up voltage < 3.6V Note2.2 All voltages are relative to ground. 2.2 SMBus Electrical Specifications Table2.3 SMBus Electrical Specifications VDD= 3V to 3.6V, T = -40°C to 125°C Typical values are at T = 27°C unless otherwise noted. A A CHARACTERISTIC SYMBOL MIN TYP MAX UNITS CONDITIONS SMBus Interface Input High Voltage V 2.0 V IH Input Low Voltage V 0.8 V IL Output High Voltage VDD V V OH - 0.4 Output Low Voltage V 0.4 V 4 mA current sink OL Input High/Low Current Powered and unpowered I I ±5 uA IH / IL 0°C < TA < 85°C Input Capacitance C 5 pF IN SMBus Timing Clock Frequency f 10 400 kHz SMB Spike Suppression t 50 ns SP Bus free time Start to t 1.3 us Stop BUF Setup Time: Start t 0.6 us SU:STA Setup Time: Stop t 0.6 us SU:STP Data Hold Time t 0 us HD:DAT Data Setup Time t 0.6 us SU:DAT SMSC EMC2303 11 Revision 1.3 (05-18-11) DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet Table2.3 SMBus Electrical Specifications (continued) VDD= 3V to 3.6V, T = -40°C to 125°C Typical values are at T = 27°C unless otherwise noted. A A CHARACTERISTIC SYMBOL MIN TYP MAX UNITS CONDITIONS Clock Low Period t 1.3 us LOW Clock High Period t 0.6 us HIGH Clock/Data Fall time t 300 ns Min = 20+0.1C ns FALL LOAD Clock/Data Rise time t 300 ns Min = 20+0.1C ns RISE LOAD Capacitive Load C 400 pF per bus line LOAD Revision 1.3 (05-18-11) 12 SMSC EMC2303 DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet Chapter 3 Communications 3.1 System Management Bus Interface Protocol The EMC2303 communicates with a host controller, such as an SMSC SIO, through the SMBus. The SMBus is a two-wire serial communication protocol between a computer host and its peripheral devices. A detailed timing diagram is shown in Figure3.1. Stretching of the SMCLK signal is supported; however, the EMC2303 will not stretch the clock signal. TLOW THIGH THD:STA TSU:STO SMCLK TRISE TFALL THD:STA THD:DAT TSU:DAT TSU:STA SMDATA TBUF P S S - Start Condition S P - Stop Condition P Figure3.1 SMBus Timing Diagram 3.1.1 SMBus Start Bit The SMBus Start bit is defined as a transition of the SMBus Data line from a logic ‘1’ state to a logic ‘0’ state while the SMBus Clock line is in a logic ‘1’ state. 3.1.2 SMBus Address and RD / WR Bit The SMBus Address Byte consists of the 7-bit client address followed by a RD / WR indicator bit. If this RD / WR bit is a logic ‘0’, then the SMBus Host is writing data to the client device. If this RD / WR bit is a logic ‘1’, then the SMBus Host is reading data from the client device. The SMBus client will respond to one of multiple SMBus addresses determined by the pull-up resistor on the ADDR_SEL pin. The ADDR_SEL pin decodes one of six pull-up resistors upon device power up. Depending on the resistor used, the CLK pin may also be used to select additional functionality. SMSC EMC2303 13 Revision 1.3 (05-18-11) DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet Table3.1 ADDR_SEL Pin Decode PULL-UP RESISTOR SMBUS ADDRESS ADDITIONAL FUNCTIONS 4.7k Ohm ±5% 0101_110(r/w) 6.8k Ohm ±5% 0101_111(r/w) None - CLK pin used as clock input 10k Ohm ±5% 0101_100(r/w) or output 15k Ohm ±5% 0101_101(r/w) 22k Ohm ±5% 1001_100(r/w) 33k Ohm ±5% 1001_101(r/w) CLK pin used to determine default fan drive - see Section4.5.1. The CLK pin cannot be used as a clock input or output 3.1.3 SMBus Data Bytes All SMBus Data bytes are sent most significant bit first and composed of 8-bits of information. 3.1.4 SMBus ACK and NACK Bits The SMBus client will acknowledge all data bytes that it receives (as well as the client address if it matches and the ARA address if the ALERT# pin is asserted). This is done by the client device pulling the SMBus Data line low after the 8th bit of each byte that is transmitted. The Host will NACK (not acknowledge) the data received from the client by holding the SMBus data line high after the 8th data bit has been sent. 3.1.5 SMBus Stop Bit The SMBus Stop bit is defined as a transition of the SMBus Data line from a logic ‘0’ state to a logic ‘1’ state while the SMBus clock line is in a logic ‘1’ state. When the EMC2303 detects an SMBus Stop bit has been communicating with the SMBus protocol, it will reset its client interface and prepare to receive further communications. 3.1.6 SMBus Time-out The EMC2303 includes an SMBus timeout feature. Following a 30ms period of inactivity on the SMBus, the device will time-out and reset the SMBus interface. The SMBus timeout feature is disabled by default and can be enabled via clearing the DIS_TO bit in the Configuration register (20h). 3.1.7 SMBus and I2C Compliance The major difference between SMBus and I2C devices is highlighted here. For complete compliance information refer to the SMBus 2.0 specification. 1. Minimum frequency for SMBus communications is 10kHz (I2C has no minimum frequency). 2. The slave protocol will reset if the clock is held low for longer than 30ms (I2C has no timeout). 3. The slave protocol will reset if both the clock and data lines are held high for longer than 150us. 4. I2C devices do not support the Alert Response Address functionality (which is optional for SMBus). Revision 1.3 (05-18-11) 14 SMSC EMC2303 DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet 5. The Block Read and Block Write protocols are only compliant with I2C data formatting. They do not support SMBus formatting for Block Read and Block Write protocols. 3.2 SMBus Protocols The EMC2303 is SMBus 2.0 compatible and supports Send Byte, Read Byte, Receive Byte and Write Byte as valid protocols as shown below. It will respond to the Alert Response Address protocol but is not in full compliance. All of the below protocols use the convention in Table3.2. When reading the protocol blocks, the value of YYYY_YYYb should be replaced with the respective SMBus addresses. Table3.2 Protocol Format DATA SENT DATA SENT TO TO DEVICE THE HOST # of bits sent # of bits sent 3.2.1 Write Byte The Write Byte is used to write one byte of data to the registers as shown below Table3.3. Table3.3 Write Byte Protocol SLAVE REGISTER REGISTER START ADDRESS WR ACK ADDRESS ACK DATA ACK STOP 1 -> 0 YYYY_YYYb 0 0 XXh 0 XXh 0 0 -> 1 3.2.2 Read Byte The Read Byte protocol is used to read one byte of data from the registers as shown in Table3.4. Table3.4 Read Byte Protocol START SLAVE WR ACK Register ACK START Slave RD ACK Register NACK STOP ADDRESS Address Address Data 1 -> 0 YYYY_YYYb 0 0 XXh 0 0 -> 1 YYYY_YYYb 1 0 XXh 1 0 -> 1 3.2.3 Send Byte The Send Byte protocol is used to set the internal address register pointer to the correct address location. No data is transferred during the Send Byte protocol as shown in Table3.5. Table3.5 Send Byte Protocol SLAVE REGISTER START ADDRESS WR ACK ADDRESS ACK STOP 1 -> 0 YYYY_YYYb 0 0 XXh 0 0 -> 1 SMSC EMC2303 15 Revision 1.3 (05-18-11) DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet 3.2.4 Receive Byte The Receive Byte protocol is used to read data from a register when the internal register address pointer is known to be at the right location (e.g. set via Send Byte). This is used for consecutive reads of the same register as shown in Table3.6. Table3.6 Receive Byte Protocol SLAVE START ADDRESS RD ACK REGISTER DATA NACK STOP 1 -> 0 YYYY_YYYb 1 0 XXh 1 0 -> 1 3.2.5 Block Write Protocol The Block Write is used to write multiple data bytes to a group of contiguous registers as shown in Table3.7. It is an extension of the Write Byte Protocol. Table3.7 Block Write Protocol SLAVE REGISTER REGISTER START ADDRESS WR ACK ADDRESS ACK DATA ACK 1 ->0 YYYY_YYYb 0 0 XXh 0 XXh 0 REGISTER REGISTER REGISTER DATA ACK DATA ACK . . . DATA ACK STOP XXh 0 XXh 0 . . . XXh 0 0 -> 1 3.2.6 Block Read Protocol The Block Read is used to read multiple data bytes from a group of contiguous registers as shown in Table3.8. It is an extension of the Read Byte Protocol. Table3.8 Block Read Protocol START SLAVE WR ACK REGISTER ACK START SLAVE RD ACK REGISTER ADDRESS ADDRESS ADDRESS DATA 1->0 YYYY_YYYb 0 0 XXh 0 1 ->0 YYYY_YYYb 1 0 XXh ACK REGISTER ACK REGISTER ACK REGISTER ACK . . . REGISTER NACK STOP DATA DATA DATA DATA 0 XXh 0 XXh 0 XXh 0 . . . XXh 1 0 -> 1 3.2.7 Alert Response Address The ALERT# output can be used as a processor interrupt or as an SMBus Alert when configured to operate as an interrupt. When it detects that the ALERT# pin is asserted, the host will send the Alert Response Address (ARA) to the general address of 0001_100xb. All devices with active interrupts will respond with their client address as shown in Table3.9. Revision 1.3 (05-18-11) 16 SMSC EMC2303 DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet Table3.9 Alert Response Address Protocol ALERT RESPONSE DEVICE START ADDRESS RD ACK ADDRESS NACK STOP 1 -> 0 0001_100b 1 0 YYYY_YYYb 1 0 -> 1 The EMC2303 will respond to the ARA in the following way if the ALERT# pin is asserted. 1. Send Slave Address and verify that full slave address was sent (i.e. the SMBus communication from the device was not prematurely stopped due to a bus contention event). 2. Set the MASK bit to clear the ALERT# pin. SMSC EMC2303 17 Revision 1.3 (05-18-11) DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet Chapter 4 Product Description The EMC2303 is an SMBus compliant fan controller with three programmable frequency PWM fan drivers. The fan drivers can be operated using two modes: the RPM-based Fan Speed Control Algorithm or the direct fan drive setting. Figure4.1 shows a system diagram of the EMC2303. 3.3V VDD tachometer SMCLK TACH3 MCU SMDATA Drive PWM3 Circuit ALERT# ADDR_SEL EMC2303 tachometer TACH2 tachometer Drive TACH1 PWM2 Circuit Drive PWM1 Circuit CLK 32.768KHz Clock GND Input or Output Figure4.1 System Diagram of EMC2303 4.1 Fan Control Modes of Operation The EMC2303 has two modes of operation for each fan driver. Each mode of operation uses the Ramp Rate control and Spin Up Routine. 1. Direct Setting Mode - in this mode of operation, the user directly controls the fan drive setting. Updating the Fan Driver Setting Register (see Section5.7) will instantly update the PWM fan drive. Ramp Rate control is optional and enabled via the EN_RRC bits. (cid:132) Whenever the Direct Setting Mode is enabled, the current drive will be changed to what was last written into the Fan Driver Setting Register. 2. Fan Speed Control Mode (FSC) - in this mode of operation, the user determines a target tachometer count and the PWM drive setting is automatically updated to achieve this target speed. The algorithm uses the Spin Up Routine and has user definable ramp rate controls. (cid:132) This mode is enabled setting the EN_ALGO bit in the Fan Configuration Register. Revision 1.3 (05-18-11) 18 SMSC EMC2303 DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet Table4.1 Fan Controls Active for Operating Mode DIRECT SETTING MODE FSC MODE Fan Driver Setting (read / write) Fan Driver Setting (read only) EDGES[1:0] EDGES[1:0] (Fan Configuration) - RANGE[1:0] (Fan Configuration) UPDATE[2:0] UPDATE[2:0] (Fan Configuration) (Fan Configuration) LEVEL LEVEL (Spin Up Configuration) (Spin Up Configuration) SPINUP_TIME[1:0] SPINUP_TIME[1:0] (Spin Up Configuration) (Spin Up Configuration) Fan Step Fan Step - Fan Minimum Drive Valid TACH Count Valid TACH Count - TACH Target (read / write) TACH Reading TACH Reading - DRIVE_FAIL_CNT[1:0] and Drive Band Fail Registers 4.2 PWM Fan Driver The EMC2303 supports 3 PWM output drivers. Each output driver can be configured to operate as an open-drain (default) or push-pull driver and each driver can be configured with normal or inverse polarity. Additionally, the PWM frequencies are independently programmable with ranges from 9.5Hz to 26kHz in four programmable frequency bands. 4.3 RPM-based Fan Speed Control Algorithm (FSC) The EMC2303 includes 3 RPM-based Fan Speed Control Algorithms. Each algorithm operates independently and controls a separate fan driver. Each algorithm is controlled manually (by setting the target fan speed). This fan control algorithm uses Proportional, Integral, and Derivative terms to automatically approach and maintain the system’s desired fan speed to an accuracy directly proportional to the accuracy of the clock source. The desired tachometer count is set by the user inputting the desired number of 32.768kHz cycles that occur per fan revolution. This is done by manually setting the TACH Target Register. The user may change the target count at any time. The user may also set the target count to FFh in order to disable the fan driver for lower current operation. For example, if a desired RPM rate for a 2-pole fan is 3000 RPMs, then the user would input the hexidecimal equivalent of 1296 (51h in the TACH Target Register). This number represents the number of 32.768KHz cycles that would occur during the time it takes the fan to complete a single revolution when it is spinning at 3000RPMs. SMSC EMC2303 19 Revision 1.3 (05-18-11) DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet The EMC2303’s RPM-based Fan Speed Control Algorithm has programmable configuration settings for parameters such as ramp-rate control and spin up conditions. The fan driver automatically detects and attempts to alleviate a stalled/stuck fan condition while also asserting the ALERT# pin. The EMC2303 works with fans that operate up to 16,000 RPMs and provide a valid tachometer signal. The fan controller will function either with an externally supplied 32.768kHz clock source or with it’s own internal 32kHz oscillator depending on the required accuracy. The EMC2303 offers a clock output that enables additional devices to be slaved to the same clock source. 4.3.1 Programming the RPM-based Fan Speed Control Algorithm The RPM-based Fan Speed Control Algorithm is disabled upon device power up. The following registers control the algorithm. The EMC2303 fan control registers are pre-loaded with defaults that will work for a wide variety of fans so only the TACH Target Register is required to set a fan speed. The other fan control registers can be used to fine-tune the algorithm behavior based on application requirements. Note that steps 1 - 6 are optional and need only be performed if the default settings do not provide the desired fan response. 1. Set the Spin Up Configuration Register to the Spin Up Level and Spin Time desired. 2. Set the Fan Step Register to the desired step size. 3. Set the Fan Minimum Drive Register to the minimum drive value that will maintain fan operation. 4. Set the Update Time and Edges options in the Fan Configuration Register. 5. Set the Valid TACH Count Register to the highest tach count that indicates the fan is spinning. Refer to AN17.4 RPM to TACH Counts Conversion for examples and tables for supported RPM ranges (500, 1k, 2k, 4k). 6. Set the TACH Target Register to the desired tachometer count. 7. Enable the RPM-based Fan Speed Control Algorithm by setting the EN_ALGO bit. 4.4 Tachometer Measurement The tachometer measurement circuitry is used in conjunction with the RPM-based Fan Speed Control Algorithm to update the fan driver output. Additionally, it can be used in Direct Setting mode as a diagnostic for host based fan control. This method monitors the TACHx signal in real time. It constantly updates the tachometer measurement by reporting the number of clocks between a user programmed number of edges on the TACHx signal (see Table5.12). The tachometer measurement provides fast response times for the RPM-based Fan Speed Control Algorithm and the data is presented as a count value that represents the fan RPM period. APPLICATION NOTE: The tachometer measurement method works independently of the drive settings. If the device is put into Direct Setting and the fan drive is set at a level that is lower than the fan can operate (including zero drive), then the tachometer measurement may signal a Stalled Fan condition and assert an interrupt. 4.4.1 Stalled Fan A Stalled fan is detected if the tach counter exceeds the user-programmable Valid TACH Count setting. If a stall is detected, the device will flag the fan as stalled and trigger an interrupt. If the RPM-based Fan Speed Control Algorithm is enabled, the algorithm will automatically attempt to restart the fan until it detects a valid tachometer level or is disabled. Revision 1.3 (05-18-11) 20 SMSC EMC2303 DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet The FAN_STALL Status bit indicates that a stalled fan was detected. This bit is checked conditionally depending on the mode of operation. (cid:132) Whenever the Direct Setting Mode or the Spin Up Routine is enabled, the FAN_STALL interrupt will be masked for the duration of the programmed Spin Up Time (see Table5.22) to allow the fan to reach a valid speed without generating unnecessary interrupts. (cid:132) In Direct Setting Mode, whenever the TACH Reading Register value exceeds the Valid TACH Count Register setting, the FAN_STALL status bit will be set. (cid:132) When using the RPM-based Fan Speed Control Algorithm, the stalled fan condition is checked whenever the Update Time is met and the fan drive setting is updated. It is not a continuous check. 4.4.2 Aging Fan or Invalid Drive Detection This is useful to detect aging fan conditions (where the fan’s natural maximum speed degrades over time) or a speed setting that is faster than the fan is capable of. The EMC2303 contains circuitry that detects that the programmed fan speed can be reached by the fan. If the target fan speed cannot be reached within a user defined band of tach counts at maximum drive, the DRIVE_FAIL status bits are set and the ALERT# pin is asserted. 4.5 CLK Pin The CLK pin has multiple functionality as determined by the pull-up decode of the ADDR_SEL pin and the settings of the Configuration register. The functionality associated with the CLK pin upon device power up is independent of the CLK pin functionality after the device has been configured. 4.5.1 Pull Up Decode If additional functionality is enabled via the ADDR_SEL pin (see Section3.1.2), then the CLK pin should be configured with a pull-up resistor to VDD and should not be used. The value of the pull-up resistor on the CLK pin is used to determine the default drive state of all fan drivers as shown in Table4.2. Table4.2 CLK Pin Pull-Up Decode PULL-UP RESISTOR FAN DEFAULT DRIVE SETTING 4.7k Ohm ±5% 0% - OFF 6.8k Ohm ±5% 30% 10k Ohm ±5% 50% 15k Ohm ±5% 75% 22k Ohm ±5% 100% 33k Ohm ±5% 0% - OFF 4.5.2 External Clock The EMC2303 allows the user to choose between supplying an external 32.768kHz clock or use of the internal 32kHz oscillator to measure the tachometer signal. This clock source is used by the RPM- based Fan Speed Control Algorithm to calculate the current fan speed. This fan controller accuracy is directly proportional to the accuracy of the clock source. When this function is used, the external clock is driven into the device via the CLK pin. SMSC EMC2303 21 Revision 1.3 (05-18-11) DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet 4.5.3 Internal Clock Alternately, the EMC2303 may be configured to use its internal clock as a clock output to drive other fan driver devices. When configured to operate in this mode, the device uses its internal clock for tachometer reading and drives the CLK pin using a push-pull driver. 4.6 Spin Up Routine The EMC2303 also contains programmable circuitry to control the spin up behavior of the fan driver to ensure proper fan operation. The Spin Up Routine is initiated in Direct Setting mode when the setting value changes from 00h to anything else. When the Fan Speed Control Algorithm is enabled, the Spin Up Routine is initiated under the following conditions: 1. The TACH Target Register value changes from a value of FFh to a value that is less than the Valid TACH Count (see Section5.15). 2. The RPM-based Fan Speed Control Algorithm’s measured TACH Reading Register value is greater than the Valid TACH Count setting. When the Spin Up Routine is operating, the fan driver is set to full scale (optional) for one quarter of the total user defined spin up time. For the remaining spin up time, the fan driver output is set at a user defined level (30% through 65% drive). After the Spin Up Routine has finished, the EMC2303 measures the TACHx signal. If the measured TACH Reading Register value is higher than the Valid TACH Count Register setting, the FAN_SPIN status bit is set and the Spin Up Routine will automatically attempt to restart the fan. Figure4.2 shows an example of the Spin Up Routine in response to a programmed fan speed change based on the first condition above. Revision 1.3 (05-18-11) 22 SMSC EMC2303 DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet 100% (optional) 30% through 65% Fan Step New Target Count Algorithm controlled drive Prev Target Count = FFh ¼ of Spin Up Time Update Time Spin Up Time Target Count Check TACH Target Count Changed Reached Figure4.2 Spin Up Routine 4.6.1 Power Up Options The EMC2303 allows for one of four fan speed options upon device power up depending on the status of the pull-up resistor on the ADDR_SEL pin and the CLK pin. If the ADDR_SEL pin decode enables the CLK pin (see Table3.1), then the value of the pull-up resistor on the CLK pin is used to determine the default fan drive setting (see Section4.5.1). If the Fan drive setting is set at a non-zero value (as determined by the CLK pin), then the drive setting will be set to the desired setting. The Spin Up Routine will not be activated. This function does not disable the Watchdog timer which will continue to function normally. See Section4.8. 4.7 Ramp Rate Control The Fan Driver can be configured with automatic ramp rate control. Ramp rate control is accomplished by adjusting the drive output settings based on the Maximum Fan Step Register settings and the Update Time settings. If the RPM-based Fan Speed Control Algorithm is used, then this ramp rate control is automatically used. The user programs a maximum step size for the fan drive setting and an update time. The update time varies from 100ms to 1.6s while the fan drive maximum step can vary from 1 count to 31 counts. When a new fan drive setting is entered, the delta from the next fan drive setting and the previous fan drive setting is determined. If this delta is greater than the Max Step settings, then the fan drive setting is incrementally adjusted every 100ms to 1.6s as determined by the Update Time until the target fan drive setting is reached. See Figure4.3. SMSC EMC2303 23 Revision 1.3 (05-18-11) DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet Next Desired Setting Max Step Max Step Previous Setting Update Update Time Time Setting Changed Figure4.3 Ramp Rate Control 4.8 Watchdog Timer The EMC2303 contains an internal Watchdog Timer for all fan drivers. The Watchdog timer monitors the SMBus traffic for signs of activity and works in two different modes based upon device operation. These modes are Power Up Operation and Continuous Operation as described below. For either mode of operation, if four (4) seconds elapse without activity detected by the host, then the watchdog will be triggered and the following will occur: 1. The WATCH status bit will be set. 2. The fan driver will be set to full scale drive. It will remain at full scale drive until it is disabled. 3. The ALERT# pin is asserted. APPLICATION NOTE: When the Watchdog timer is activated, the Fan Speed Control Algorithm is automatically disabled. Disabling the Watchdog will not automatically set the fan drive nor re-activate the Fan Speed Control Algorithm. This must be done manually. 4.8.1 Power Up Operation The Watchdog Timer only starts immediately after power-up. Once it has been triggered or deactivated, it will not restart although it can be configured to operate in Continuous operation. While the Watchdog timer is active, the device will not check for a Stalled Fan condition. Revision 1.3 (05-18-11) 24 SMSC EMC2303 DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet In the Power Up Operation, the Watchdog Timer is disabled by any of the following actions: 1. Writing the Fan Setting Register will disable the Watchdog Timer. 2. Enabling the RPM-based Fan Speed Control Algorithm by setting the EN_ALGO bit will disable the Watchdog Timer. The fan driver will be set based on the RPM-based Fan Speed Control Algorithm. Writing any other configuration registers will not disable the Watchdog Timer upon power up. 4.8.2 Continuous Operation When configured to operate in Continuous Operation, the Watchdog timer will start immediately. The timer will be reset by any access (read or write) to the SMBus register set. The four second Watchdog timer will restart upon completion of SMBus activity. SMSC EMC2303 25 Revision 1.3 (05-18-11) DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet Chapter 5 Register Set 5.1 Register Map The following registers are accessible through the SMBus Interface. All register bits marked as ‘-’ will always read ‘0’. A write to these bits will have no effect. Table5.1 EMC2303 Register Set REGISTER DEFAULT ADDR R/W NAME FUNCTION VALUE LOCK PAGE Configuration and control Configures the clocking and watchdog 20h R/W Configuration 40h SWL Page 29 functionality Stores the status bits for the RPM- 24h R-C Fan Status 00h No Page 30 based Fan Speed Control Algorithm Stores status bits associated with a 25h R-C Fan Stall Status 00h No Page 30 stalled fan Stores status bits associated with a 26h R-C Fan Spin Status 00h No Page 30 spin-up failure Stores status bits associated with drive 27h R-C Drive Fail Status 00h No Page 30 failure Fan Interrupt Controls the masking of interrupts on all 29h R/W 00h No Page 31 Enable Register fan related channels PWM Polarity 2Ah R/W Configures Polarity of all PWM drivers 00h No Page 32 Config PWM Output 2Bh R/W Configures Output type of PWM drivers 00h No Page 32 Config PWM Base Selects the base frequency for PWM 2Dh R/W 00h No Page 33 Frequency outputs 3 - 1 Fan 1 Control Registers Always displays the most recent fan driver input setting for Fan 1. If the 30h R/W Fan 1 Setting RPM-based Fan Speed Control 00h No Page 33 Algorithm is disabled, allows direct user control of the fan driver. Stores the divide ratio to set the 31h R/W PWM 1 Divide 01h No Page 34 frequency for Fan 1 Sets configuration values for the RPM- Fan 1 32h R/W based Fan Speed Control Algorithm for 2Bh No Page 34 Configuration 1 the Fan 1 driver Fan 1 Sets additional configuration values for 33h R/W 28h SWL Page 36 Configuration 2 the Fan 1driver Revision 1.3 (05-18-11) 26 SMSC EMC2303 DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet Table5.1 EMC2303 Register Set (continued) REGISTER DEFAULT ADDR R/W NAME FUNCTION VALUE LOCK PAGE Holds the gain terms used by the RPM- 35h R/W Gain 1 based Fan Speed Control Algorithm for 2Ah SWL Page 37 the Fan 1 driver Fan 1 Spin Up Sets the configuration values for Spin 36h R/W 19h SWL Page 38 Configuration Up Routine of the Fan 1driver Sets the maximum change per update 37h R/W Fan 1 Max Step 10h SWL Page 40 for the Fan 1 driver Fan 1 Minimum Sets the minimum drive value for the 66h 38h R/W SWL Page 41 Drive Fan 1 driver (40%) Fan 1 Valid TACH Holds the tachometer reading that 39h R/W F5h SWL Page 41 Count indicates Fan 1 is spinning properly Fan 1 Drive Fail 3Ah R/W Stores the number of Tach counts used 00h SWL Band Low Byte to determine how the actual fan speed Page42 must match the target fan speed at full Fan 1 Drive Fail 3Bh R/W scale drive 00h SWL Band High Byte TACH 1 Target Holds the target tachometer reading low 3Ch R/W F8h No Page 42 Low Byte byte for Fan 1 TACH 1 Target Holds the target tachometer reading 3Dh R/W FFh No Page 42 High Byte high byte for Fan 1 TACH 1 Reading Holds the tachometer reading high byte 3Eh R FFh No Page 43 High Byte for Fan 1 TACH 1 Reading Holds the tachometer reading low byte 3Fh R F8h No Page 43 Low Byte for Fan 1 Fan 2 Control Registers Always displays the most recent fan driver input setting for Fan 2. If the 40h R/W Fan 2 Setting RPM-based Fan Speed Control 00h No Page 33 Algorithm is disabled, allows direct user control of the fan driver. Stores the divide ratio to set the 41h R/W PWM 2 Divide 01h No Page 34 frequency for Fan 2 Sets configuration values for the RPM- Fan 2 42h R/W based Fan Speed Control Algorithm for 2Bh No Page 34 Configuration1 Fan 2 Fan 2 Sets additional configuration values for 43h R/W 28h SWL Page 36 Configuration 2 the Fan 2 driver Holds the gain terms used by the RPM- 45h R/W Gain 2 based Fan Speed Control Algorithm for 2Ah SWL Page 37 Fan 2 Fan 2 Spin Up Sets the configuration values for Spin 46h R/W 19h SWL Page 38 Configuration Up Routine of the Fan 2 driver SMSC EMC2303 27 Revision 1.3 (05-18-11) DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet Table5.1 EMC2303 Register Set (continued) REGISTER DEFAULT ADDR R/W NAME FUNCTION VALUE LOCK PAGE Sets the maximum change per update 47h R/W Fan 2 Max Step 10h SWL Page 40 for Fan 2 Fan 2 Minimum Sets the minimum drive value for the 66h 48h R/W SWL Page 41 Drive Fan 2 driver (40%) Fan 2 Valid TACH Holds the tachometer reading that 49h R/W F5h SWL Page 41 Count indicates Fan 2 is spinning properly Fan 2 Drive Fail 4Ah R/W Stores the number of Tach counts used 00h SWL Band Low Byte to determine how the actual fan speed Page42 must match the target fan speed at full Fan 2 Drive Fail 4Bh R/W scale drive 00h SWL Band High Byte TACH 2 Target Holds the target tachometer setting low 4Ch R/W F8h No Page 42 Low Byte byte for Fan 2 TACH 2 Target Holds the target tachometer setting high 4Dh R/W FFh No Page 42 High Byte byte for Fan 2 TACH 2 Reading Holds the tachometer reading high byte 4Eh R FFh No Page 43 High Byte for Fan 2 TACH 2 Reading Holds the tachometer reading low byte 4Fh R F8h No Page 43 Low Byte for Fan 2 Fan 3 Control Registers Always displays the most recent fan driver input setting for Fan 3. If the 50h R/W Fan 3 Setting RPM-based Fan Speed Control 00h No Page 33 Algorithm is disabled, allows direct user control of the fan driver. Stores the divide ratio to set the 51h R/W PWM 3 Divide 01h No Page 34 frequency for Fan 3 Sets configuration values for the RPM- Fan 3 52h R/W based Fan Speed Control Algorithm for 2Bh No Page 34 Configuration 1 the Fan 3 driver Fan 3 Sets additional configuration values for 53h R/W 28h SWL Page 36 Configuration 2 the Fan 3 driver Holds the gain terms used by the RPM- 55h R/W Gain 3 based Fan Speed Control Algorithm for 2Ah SWL Page 37 the Fan 3 driver Fan 3 Spin Up Sets the configuration values for Spin 56h R/W 19h SWL Page 38 Configuration Up Routine of the Fan 3 driver Sets the maximum change per update 57h R/W Fan 3 Max Step 10h SWL Page 40 for the Fan 3 driver Fan 3 Minimum Sets the minimum drive value for the 66h 58h R/W SWL Page 41 Drive Fan 3 driver (40%) Fan 3 Valid TACH Holds the tachometer reading that 59h R/W F5h SWL Page 41 Count indicates Fan 3 is spinning properly Revision 1.3 (05-18-11) 28 SMSC EMC2303 DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet Table5.1 EMC2303 Register Set (continued) REGISTER DEFAULT ADDR R/W NAME FUNCTION VALUE LOCK PAGE Fan 3 Drive Fail 5Ah R/W Stores the number of Tach counts used 00h SWL Band Low Byte to determine how the actual fan speed Page42 must match the target fan speed at full Fan 3 Drive Fail 5Bh R/W scale drive 00h SWL Band High Byte TACH 3 Target Holds the target tachometer reading low 5Ch R/W F8h No Page 42 Low Byte byte for Fan 3 TACH 3 Target Holds the target tachometer reading 5Dh R/W FFh No Page 42 High Byte high byte for Fan 3 TACH 3 Reading Holds the tachometer reading high byte 5Eh R FFh No Page 43 High Byte for Fan 3 TACH 3 Reading Holds the tachometer reading low byte 5Fh R F8h No Page 43 Low Byte for Fan 3 Lock Register EF R/W Software Lock Locks all SWL registers 00h SWL Page 44 Revision Registers Indicates functions determined upon FCh R Product Features 00h No Page 44 device power up by external pin states FDh R Product ID Stores the unique Product ID 35h No Page 45 FEh R Manufacturer ID Stores the Manufacturer ID 5Dh No Page 46 FFh R Revision Revision 80h No Page 46 During Power-On-Reset (POR), the default values are stored in the registers. A POR is initiated when power is first applied to the part and the voltage on the VDD supply surpasses the POR level as specified in the electrical characteristics. Any reads to undefined registers will return 00h. Writes to undefined registers will not have an effect. 5.1.1 Lock Entries The Lock Column describes the locking mechanism, if any, used for individual registers. All SWL registers are Software Locked and therefore made read-only when the LOCK bit is set. 5.2 Configuration Register Table5.2 Configuration Register ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT USE_ DR_EXT_ 20h R/W Configuration MASK DIS_TO WD_EN - - - EXT_ 40h CLK CLK The Configuration Register controls the basic functionality of the EMC2303. The bits are described below. The Configuration Register is software locked. SMSC EMC2303 29 Revision 1.3 (05-18-11) DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet Bit 7 - MASK - Blocks the ALERT# pin from being asserted. (cid:132) ‘0’ (default) - The ALERT# pin is unmasked. If any bit in the status registers is set, the ALERT# pin will be asserted (unless individually masked via the Fan Interrupt Enable Register). (cid:132) ‘1’ - The ALERT# pin is masked and will not be asserted. Bit 6 - DIS_TO - Disables the SMBus timeout function for the SMBus client (if enabled). (cid:132) ‘0’ - The SMBus timeout function is enabled. (cid:132) ‘1’ (default) - The SMBus timeout function is disabled allowing the device to be fully I2C compliant. Bit 5 - WD_EN - Enables the Watchdog timer (see Section4.8) to operate in Continuous Mode. (cid:132) ‘0’ (default) - The Watchdog timer does not operate continuously. It will function upon power up and at no other time (see Section4.8.1). (cid:132) ‘1’ - The Watchdog timer operates continuously as described in Section4.8.2. Bit 1 - DR_EXT_CLK - Enables the internal tachometer clock to be driven out on the CLK pin so that multiple devices can be synced to the same source. (cid:132) ‘0’ (default) - The CLK pin acts as a clock input. (cid:132) ‘1’ - The CLK pin acts as a clock output and is a push-pull driver. Bit 0 - USE_EXT_CLK - Enables the EMC2303 to use a clock present on the CLK pin as the tachometer clock. If the DR_EXT_CLK bit is set, then this bit is ignored and the device will use the internal oscillator. (cid:132) ‘0’ (default) - The EMC2303 will use its internal oscillator for all Tachometer measurements. (cid:132) ‘1’ - The EMC2303 will use the oscillator presented on the CLK pin for all Tachometer measurements. 5.3 Fan Status Registers Table5.3 Fan Status Registers ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT DRIVE_ FAN_ FAN_ 24h R-C Fan Status WATCH - - - - 00h FAIL SPIN STALL Fan Stall FAN3_ FAN2_ FAN1_ 25h R-C - - - - - 00h Status STALL STALL STALL Fan Spin FAN3_ FAN2_ FAN1_ 26h R-C - - - - - 00h Status SPIN SPIN SPIN Fan Drive DRIVE_ DRIVE_ DRIVE_ 27h R-C - - - - - 00h Fail Status FAIL3 FAIL2 FAIL1 The Fan Status registers contain the status bits associated with each fan driver. 5.3.1 Fan Status - 24h The Fan Status register indicates that one or more of the fan drivers has stalled or failed or that the Watchdog Timer has expired (see Section4.8). Bit 7 - WATCH - Indicates that the Watchdog Timer has expired. When set, each fan is driven to 100% duty cycle and will remain at 100% duty cycle until they are programmed. This bit is cleared when it is read. Revision 1.3 (05-18-11) 30 SMSC EMC2303 DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet Bit 2 - DRIVE_FAIL - Indicates that one or more fan drivers cannot meet the programmed fan speed at maximum PWM duty cycle. This bit is set when any bit in the Fan Drive Fail Status register is set and cleared when all bits in the Fan Drive Fail Status register are cleared. Bit 1 - FAN_SPIN - Indicates that one or more fan drivers cannot spin up. This bit is set when any bit in the Fan Spin Status register is set and cleared when all of the bits in the Fan Spin Status register are cleared. Bit 0 - FAN_STALL - Indicates that one or more fan drivers have stalled. This bit is set when any bit in the Fan Stall Status register is set and cleared when all of the bits in the Fan Stall Status register are cleared. 5.3.2 Fan Stall Status - 25h The Fan Stall Status register indicates which fan driver has detected a stalled condition (see Section4.4.1). All bits are cleared upon a read if the error condition has been removed. Bit 2 - FAN3_STALL - Indicates that Fan 3 has stalled. Bit 1 - FAN2_STALL - Indicates that Fan 2 has stalled. Bit 0 - FAN1_STALL - Indicates that Fan 1 has stalled. 5.3.3 Fan Spin Status - 26h The Fan Spin Status register indicates which fan driver has failed to spin-up (see Section4.6). All bits are cleared upon a read if the error condition has been removed. Bit 2 - FAN3_SPIN - Indicates that Fan 3 has failed to spin up. Bit 1 - FAN2_SPIN - Indicates that Fan 2 has failed to spin up. Bit 0 - FAN1_SPIN - Indicates that Fan 1 has failed to spin up. 5.3.4 Fan Drive Fail Status - 27h The Fan Drive Fail Status register indicates which fan driver cannot drive to the programmed speed even at 100% duty cycle (see Section4.4.2 and Section5.12). All bits are cleared upon a read if the error condition has been removed. Bit 2 - DRIVE_FAIL3 - Indicates that Fan 3 cannot reach its programmed fan speed even at 100% duty cycle. This may be due to an aging fan or invalid programming. Bit 1 - DRIVE_FAIL2 - Indicates that Fan 2 cannot reach its programmed fan speed even at 100% duty cycle. This may be due to an aging fan or invalid programming. Bit 0 - DRIVE_FAIL1 - Indicates that Fan 1 cannot reach its programmed fan speed even at 100% duty cycle. This may be due to an aging fan or invalid programming. 5.4 Fan Interrupt Enable Register Table5.4 Fan Interrupt Enable Register ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT Fan FAN3_ FAN2_ FAN1_ 29h R/W Interrupt - - - - - 00h INT_EN INT_EN INT_EN Enable SMSC EMC2303 31 Revision 1.3 (05-18-11) DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet The Fan Interrupt Enable controls the masking for each Fan channel. When a channel is enabled, it will cause the ALERT# pin to be asserted when an error condition is detected. Bit 2 - FAN3_INT_EN - Allows Fan 3 to assert the ALERT# pin if an error is detected. Bit 1 - FAN2_INT_EN - Allows Fan 2 to assert the ALERT# pin if an error is detected. Bit 0 - FAN1_INT_EN - Allows Fan 1 to assert the ALERT# pin if an error condition is detected. (cid:132) ‘0’ (default) - An error condition on Fan X will not cause the ALERT# pin to be asserted, however the status registers will be updated normally. (cid:132) ‘1’ - An error condition (Stall, Spin Up, Drive Fail) on Fan X will cause the ALERT# pin to be asserted. 5.5 PWM Configuration Registers Table5.5 PWM Configuration Registers ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT PWM Polarity POLARITY POLARITY POLARITY 2Ah R/W - - - - - 00h Config 3 2 1 PWM Output 2Bh R/W - - - - - PWM3_OT PWM2_OT PWM1_OT 00h Config The PWM Config registers control the output type and polarity of all PWM outputs. 5.5.1 PWM Polarity Config - 2Ah Bit 2 - POLARITY3 - Determines the polarity of PWM 3. Bit 1 - POLARITY2 - Determines the polarity of PWM 2. Bit 0 - POLARITY1 - Determines the polarity of PWM 1. (cid:132) ‘0’ (default) - the Polarity of the PWM driver is normal. A drive setting of 00h will cause the output to be set at 0% duty cycle and a drive setting of FFh will cause the output to be set at 100% duty cycle. (cid:132) ‘1’ - The Polarity of the PWM driver is inverted. A drive setting of 00h will cause the output to be set at 100% duty cycle and a drive setting of FFh will cause the output to be set at 0% duty cycle. 5.5.2 PWM Output Config - 2Bh Bit 2 - PWM3_OT - Determines the output type of the of PWM 3 driver. Bit 1 - PWM2_OT - Determines the output type of PWM 2 driver. Bit 0 - PWM1_OT - Determines the output type of the PWM 1 driver. (cid:132) ‘0’ (default) - The PWM 1 output is configured as an open drain output. (cid:132) ‘1’ - The PWM 1 output is configured as a push-pull output. Revision 1.3 (05-18-11) 32 SMSC EMC2303 DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet 5.6 PWM Base Frequency Register Table5.6 PWM Base Frequency Register ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT PWM_ PWM_ PWM_ PWM_ PWM_ PWM_ PWM Base 2Dh R/W - - BASE BASE BASE BASE BASE BASE 00h Frequency 3_1 3_0 2_1 2_0 1_1 1_0 The PWM Base Frequency register determines the base frequency that is used with the PWM Divide register to determine the final PWM frequency. Each PWM frequency is set by the base frequency and its respective divide ratio (see Section5.8). Controls the base frequency of PWM drivers 1-3 Bits 5-6 - PWM_BASE3[1:0] - Determines the base frequency of the PWM3 driver. Bits 3-2 - PWM_BASE2[1:0] - Determines the base frequency of the PWM2 driver. Bits 1-0 - PWM_BASE1[1:0] - Determines the base frequency of the PWM1 driver. Table5.7 PWM_BASEx[1:0] Bit Decode PWM_BASEX[1:0] 1 0 BASE FREQUENCY 0 0 26.00kHz (default) 0 1 19.531kHz 1 0 4,882Hz 1 1 2,441Hz 5.7 Fan Setting Registers Table5.8 Fan Driver Setting Registers ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 30h R/W Fan 1 Setting 128 64 32 16 8 4 2 1 00h 40h R/W Fan 2 Setting 128 64 32 16 8 4 2 1 00h 50h R/W Fan 3 Setting 128 64 32 16 8 4 2 1 00h The Fan Setting register always displays the current setting of the respective fan driver. Reading from any of the registers will report the current fan speed setting of the appropriate fan driver regardless of the operating mode. Therefore it is possible that reading from this register will not report data that was previously written into this register. While the RPM-based Fan Speed Control Algorithm is active, the register is read only. Writing to the register will have no effect and the data will not be stored. SMSC EMC2303 33 Revision 1.3 (05-18-11) DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet The contents of the register represent the weighting of each bit in determining the final output voltage. The output drive for a PWM output is given by Equation [1]. Drive = ⎛V-----A----L----U-----E---⎞ ×100% [1] ⎝ 255 ⎠ 5.8 PWM Divide Registers Table5.9 PWM Divide Registers ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 31h R/W Fan 1 Divide 128 64 32 16 8 4 2 1 01h 41h R/W Fan 2 Divide 128 64 32 16 8 4 2 1 01h 51h R/W Fan 3 Divide 128 64 32 16 8 4 2 1 01h The PWM Divide registers determine the final frequency of the respective PWM Fan Driver. Each driver base frequency is divided by the value of the respective PWM Divide Register to determine the final frequency. The duty cycle settings are not affected by these settings, only the final frequency of the PWM driver. A value of 00h will be decoded as 01h. 5.9 Fan Configuration 1 Registers Table5.10 Fan Configuration 1 Registers ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT Fan 1 EN_ 32h R/W RANGE1[1:0] EDGES1[1:0] UPDATE1[2:0] 2Bh Configuration 1 ALGO1 Fan 2 EN_ 42h R/W RANGE2[1:0] EDGES2[1:0] UPDATE2[2:0] 2Bh Configuration 1 ALGO2 Fan 3 EN_ 52h R/W RANGE3[1:0] EDGES3[1:0] UPDATE3[2:0] 2Bh Configuration 1 ALGO3 The Fan Configuration 1 registers control the general operation of the RPM-based Fan Speed Control Algorithm used for the respective Fan Driver. Bit 7 - EN_ALGOx - enables the RPM-based Fan Speed Control Algorithm. (cid:132) ‘0’ - (default) the control circuitry is disabled and the fan driver output is determined by the Fan Driver Setting Register. (cid:132) ‘1’ - the control circuitry is enabled and the Fan Driver output will be automatically updated to maintain the programmed fan speed as indicated by the TACH Target Register. Bits 6- 5 - RANGEx[1:0] - Adjusts the range of reported and programmed tachometer reading values. The RANGE bits determine the weighting of all TACH values (including the Valid TACH Count, TACH Target, and TACH reading) as shown in Table5.11. Revision 1.3 (05-18-11) 34 SMSC EMC2303 DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet Table5.11 Range Decode RANGEX[1:0] REPORTED MINIMUM TACH COUNT 1 0 RPM MULTIPLIER 0 0 500 1 0 1 1000 (default) 2 1 0 2000 4 1 1 4000 8 Bits 4-3 - EDGESx[1:0] - determines the minimum number of edges that must be detected on the TACHx signal to determine a single rotation. A typical fan measured 5 edges (for a 2-pole fan). For more accurate tachometer measurement, the minimum number of edges measured may be increased. Increasing the number of edges measured with respect to the number of poles of the fan will cause the TACH Reading registers to indicate a fan speed that is higher or lower than the actual speed. In order for the FSC Algorithm to operate correctly, the TACH Target must be updated by the user to accommodate this shift. The Effective Tach Multiplier shown in Table5.12 is used as a direct multiplier term that is applied to the Actual RPM to achieve the Reported RPM. It should only be applied if the number of edges measured does not match the number of edges expected based on the number of poles of the fan (which is fixed for any given fan). Contact SMSC for recommended settings when using fans with more or less than 2 poles. Table5.12 Minimum Edges for Fan Rotation EDGESX[1:0] EFFECTIVE TACH MINIMUM TACH MULTIPLIER (BASED ON 2 1 0 EDGES NUMBER OF FAN POLES POLE FANS) 0 0 3 1 pole 0.5 0 1 5 2 poles (default) 1 1 0 7 3 poles 1.5 1 1 9 4 poles 2 Bit 2-0 - UPDATEx[2:0] - determines the base time between fan driver updates. The Update Time, along with the Fan Step Register, is used to control the ramp rate of the drive response to provide a cleaner transition of the actual fan operation as the desired fan speed changes. The Update Time is set as shown in Table5.13. Table5.13 Update Time UPDATEX[2:0] 2 1 0 UPDATE TIME 0 0 0 100ms 0 0 1 200ms SMSC EMC2303 35 Revision 1.3 (05-18-11) DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet Table5.13 Update Time (continued) UPDATEX[2:0] 2 1 0 UPDATE TIME 0 1 0 300ms 0 1 1 400ms (default) 1 0 0 500ms 1 0 1 800ms 1 1 0 1200ms 1 1 1 1600ms 5.10 Fan Configuration 2 Registers Table5.14 Fan Configuration 2 Registers ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT Fan 1 EN_ GLITCH_ 33h R/W - DER_OPT1 [1:0] ERR_RNG1[1:0] - 28h Configuration 2 RRC1 EN1 Fan 2 EN_ GLITCH_ 43h R/W - DER_OPT2 [1:0] ERR_RNG2[1:0] - 28h Configuration 2 RRC2 EN2 Fan 3 EN_ GLITCH_ 53h R/W - DER_OPT3 [1:0] ERR_RNG3[1:0] - 28h Configuration 2 RRC3 EN3 The Fan Configuration 2 register control the tachometer measurement and advanced features of the RPM-based Fan Speed Control Algorithm. Bit 6 - EN_RRCx - Enables ramp rate control when the corresponding fan driver is operated in the Direct Setting Mode. (cid:132) ‘0’ (default) - Ramp rate control is disabled. When the fan driver is operating in Direct Setting mode, the fan setting will instantly transition to the next programmed setting. (cid:132) ‘1’ - Ramp rate control is enabled. When the fan driver is operating in Direct Setting mode, the fan drive setting will follow the ramp rate controls as determined by the Fan Step and Update Time settings. The maximum fan drive setting step is capped at the Fan Step setting and is updated based on the Update Time as given by Table5.13. Bit 5 - GLITCH_ENx - Disables the low pass glitch filter that removes high frequency noise injected on the TACHx pin. (cid:132) ‘0’ - The glitch filter is disabled. (cid:132) ‘1’ (default) - The glitch filter is enabled. Bits 4 - 3 - DER_OPTx[1:0] - Control some of the advanced options that affect the derivative portion of the RPM-based Fan Speed Control Algorithm as shown in Table5.15. Revision 1.3 (05-18-11) 36 SMSC EMC2303 DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet Table5.15 Derivative Options DER_OPTX[1:0] 1 0 OPERATION 0 0 No derivative options used Basic derivative. The derivative of the error from the current drive setting and the target is added 0 1 to the iterative Fan Drive Register setting (in addition to proportional and integral terms) (default) Step derivative. The derivative of the error from the current drive setting and the target is added 1 0 to the iterative Fan Drive Register setting and is not capped by the Fan Step Register. Both the basic derivative and the step derivative 1 1 are used effectively causing the derivative term to have double the effect of the derivative term. Bit 2 - 1 - ERR_RNGx[1:0] - Control some of the advanced options that affect the error window. When the measured fan speed is within the programmed error window around the target speed, then the fan drive setting is not updated. The algorithm will continue to monitor the fan speed and calculate necessary drive setting changes based on the error; however, these changes are ignored. Table5.16 Error Range Options ERR_RNGX[1:0] 1 0 OPERATION 0 0 0 RPM (default) 0 1 50 RPM 1 0 100 RPM 1 1 200 RPM 5.11 Gain Registers Table5.17 Gain Registers ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT Gain 1 35h R/W - - GAIND1[1:0] GAINI1[1:0] GAINP1[1:0] 2Ah Register Gain 2 45h R/W - - GAIND2[1:0] GAINI2[1:0] GAINP2[1:0] 2Ah Register Gain 3 55h R/W - - GAIND3[1:0] GAINI3[1:0] GAINP3[1:0] 2Ah Register SMSC EMC2303 37 Revision 1.3 (05-18-11) DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet The Gain registers store the gain terms used by the proportional and integral portions of each of the RPM-based Fan Speed Control Algorithms. These gain terms are used as the KD, KI, and KP gain terms in a classic PID control solution. Bits 5 - 4 - GAINDX[1:0] - Controls the derivative gain term used by the FSC algorithm as shown in Table5.18. Bits 3-2 - GAINIX[1:0] - Controls the integral gain term used by the FSC algorithm as shown in Table5.18. Bits 1-0 - GAINP[1:0] - Controls the proportional gain term used by the FSC algorithm as shown in Table5.18. Table5.18 Gain Decode GAIND OR GAINP OR GAINI [1:0] 1 0 RESPECTIVE GAIN FACTOR 0 0 1x 0 1 2x 1 0 4x (default) 1 1 8x 5.12 Fan Spin Up Configuration Registers Table5.19 Fan Spin Up Configuration Registers ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT Fan 1 Spin Up DRIVE_FAIL_ SPINUP_TIME 36h R/W NOKICK1 SPIN_LVL1[2:0] 19h Configuration CNT1 [1:0] 1 [1:0] Fan 2 Spin up DRIVE_FAIL_ SPINUP_TIME 46h R/W NOKICK2 SPIN_LVL2[2:0] 19h Configuration CNT2 [1:0] 2 [1:0] Fan 3 Spin up DRIVE_FAIL_ SPINUP_TIME 56h R/W NOKICK3 SPIN_LVL3[2:0] 19h Configuration CNT3 [1:0] 3[1:0] The Fan Spin Up Configuration registers control the settings of Spin Up Routine. The Fan Spin Up Configuration registers are software locked. Bit 7 - 6 - DRIVE_FAIL_CNTx[1:0] - Determines how many update cycles are used for the Drive Fail detection function as shown in Table5.20. This circuitry determines whether the fan can be driven to the desired tach target. Revision 1.3 (05-18-11) 38 SMSC EMC2303 DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet Table5.20 DRIVE_FAIL_CNT[1:0] Bit Decode DRIVE_FAIL_CNTX[1:0] 1 0 NUMBER OF UPDATE PERIODS 0 0 Disabled - the Drive Fail detection circuitry is disabled (default) 16 - the Drive Fail detection circuitry will count for 16 update 0 1 periods 32 - the Drive Fail detection circuitry will count for 32 update 1 0 periods 64 - the Drive Fail detection circuitry will count for 64 update 1 1 periods Bit 5 - NOKICKx - Determines if the Spin Up Routine will drive the fan to 100% duty cycle for 1/4 of the programmed spin up time before driving it at the programmed level. (cid:132) ‘0’ (default) - The Spin Up Routine will drive the fan driver to 100% for 1/4 of the programmed spin up time before reverting to the programmed spin level. (cid:132) ‘1’ - The Spin Up Routine will not drive the fan driver to 100%. It will set the drive at the programmed spin level for the entire duration of the programmed spin up time. Bits 4 - 2 - SPIN_LVLx[2:0] - Determines the final drive level that is used by the Spin Up Routine as shown in Table5.21. Table5.21 Spin Level SPIN_LVLX[2:0] 2 1 0 SPIN UP DRIVE LEVEL 0 0 0 30% 0 0 1 35% 0 1 0 40% 0 1 1 45% 1 0 0 50% 1 0 1 55% 1 1 0 60% (default) 1 1 1 65% Bit 1 -0 - SPINUP_TIMEx[1:0] - determines the maximum Spin Time that the Spin Up Routine will run for (see Section4.6). If a valid tachometer measurement is not detected before the Spin Time has elapsed, an interrupt will be generated. When the RPM-based Fan Speed Control Algorithm is active, the fan driver will attempt to re-start the fan immediately after the end of the last spin up attempt. The Spin Time is set as shown in Table5.22. SMSC EMC2303 39 Revision 1.3 (05-18-11) DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet Table5.22 Spin Time SPINUP_TIMEX[1:0] 1 0 TOTAL SPIN UP TIME 0 0 250 ms 0 1 500 ms (default) 1 0 1 sec 1 1 2 sec 5.13 Fan Max Step Registers Table5.23 Fan Max Step Registers ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT Fan 1 Max 37h R/W - - 32 16 8 4 2 1 10h Step Fan 2 Max 47h R/W - - 32 16 8 4 2 1 10h Step Fan 3 Max 57h R/W - - 32 16 8 4 2 1 10h Step The Fan Max Step registers, along with the Update Time, control the ramp rate of the fan driver response calculated by the RPM-based Fan Speed Control Algorithm. The value of the register represents the maximum step size each fan driver will take between update times (see Section5.9). When the FSC algorithm is enabled, Ramp Rate control is automatically used. When the FSC is not active, then Ramp Rate control can be enabled by asserting the EN_RRC bit (see Section5.10). APPLICATION NOTE: The UPDATE bits and Fan Step Register settings operate independently of the RPM-based Fan Speed Control Algorithm and will always limit the fan drive setting. That is, if the programmed fan drive setting (either as determined by the RPM-based Fan Speed Control Algorithm or by manual settings) exceeds the current fan drive setting by greater than the Fan Step Register setting, the EMC2303 will limit the fan drive change to the value of the Fan Step Register. It will use the Update Time to determine how often to update the drive settings. APPLICATION NOTE: If the Fan Speed Control Algorithm is used, the default settings in the Fan Configuration 2 Register will cause the maximum fan step settings to be ignored. The Fan Max Step registers are software locked. Revision 1.3 (05-18-11) 40 SMSC EMC2303 DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet 5.14 Fan Minimum Drive Registers Table5.24 Minimum Fan Drive Registers ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT Fan 1 66h 38h R/W Minimum 128 64 32 16 8 4 2 1 (40%) Drive Fan 2 66h 48h R/W Minimum 128 64 32 16 8 4 2 1 (40%) Drive Fan 3 66h 58h R/W Minimum 128 64 32 16 8 4 2 1 (40%) Drive The Fan Minimum Drive registers store the minimum drive setting for each RPM-based Fan Speed Control Algorithm. The RPM-based Fan Speed Control Algorithm will not drive the fan at a level lower than the minimum drive unless the target Fan Speed is set at FFh (see Section5.17). During normal operation, if the fan stops for any reason (including low drive), the RPM-based Fan Speed Control Algorithm will attempt to restart the fan. Setting the Fan Minimum Drive Register to a setting that will maintain fan operation is a useful way to avoid potential fan oscillations as the control circuitry attempts to drive it at a level that cannot support fan operation. The Fan Minimum Drive Registers are software locked. 5.15 Valid TACH Count Registers Table5.25 Valid TACH Count Registers ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT Valid TACH 39h R/W 4096 2048 1024 512 256 128 64 32 F5h Count 1 Valid TACH 49h R/W 4096 2048 1024 512 256 128 64 32 F5h Count 2 Valid TACH 59h R/W 4096 2048 1024 512 256 128 64 32 F5h Count 3 The Valid TACH Count registers store the maximum TACH Reading Register value to indicate that each fan is spinning properly. The value is referenced at the end of the Spin Up Routine to determine if the fan has started operating and decide if the device needs to retry. See Equation [2] in Section5.18 for translating the count to an RPM. If the TACH Reading Register value exceeds the Valid TACH Count Register (indicating that the Fan RPM is below the threshold set by this count), then a stalled fan is detected. In this condition, the algorithm will automatically begin its Spin Up Routine. If a TACH Target setting is set above the Valid TACH Count setting, then that setting will be ignored and the algorithm will use the current fan drive setting. The Valid TACH Count registers are software locked. SMSC EMC2303 41 Revision 1.3 (05-18-11) DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet 5.16 Fan Drive Fail Band Registers Table5.26 Fan Drive Fail Band Registers ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT Fan 1 Drive 3Ah R/W Fail Band 16 8 4 2 1 - - - 00h Low Byte Fan 1 Drive 3Bh R/W Fail Band 4096 2048 1024 512 256 128 64 32 00h High Byte Fan 2 Drive 4Ah R/W Fail Band 16 8 4 2 1 - - - 00h Low Byte Fan 2 Drive 4Bh R/W Fall Band 4096 2048 1024 512 256 128 64 32 00h High Byte Fan 3 Drive 5Ah R/W Fail Band 16 8 4 2 1 - - - 00h Low Byte Fan 3 Drive 5Bh R/W Fail Band 4096 2048 1024 512 256 128 64 32 00h High Byte The Fan Drive Fail Band Registers store the number of tach counts used by the Fan Drive Fail detection circuitry. This circuitry is activated when the fan drive setting high byte is at FFh. When it is enabled, the actual measured fan speed is compared against the target fan speed. These registers are only used when the FSC is active. This circuitry is used to indicate that the target fan speed at full drive is higher than the fan is actually capable of reaching. If the measured fan speed does not exceed the target fan speed minus the Fan Drive Fail Band Register settings for a period of time longer than set by the DRIVE_FAIL_CNTx[1:0] bits, then the DRIVE_FAIL status bit will be set and an interrupt generated. 5.17 TACH Target Registers Table5.27 TACH Target Registers ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT TACH Target 3Ch R/W 16 8 4 2 1 - - - F8h 1 Low Byte TACH Target 3Dh R/W 4096 2048 1024 512 256 128 64 32 FFh 1 High Byte TACH Target 4Ch R 16 8 4 2 1 - - - F8h 2 Low Byte TACH Target 4Dh R/W 4096 2048 1024 512 256 128 64 32 FFh 2 High Byte Revision 1.3 (05-18-11) 42 SMSC EMC2303 DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet Table5.27 TACH Target Registers (continued) ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT TACH Target 5Ch R 16 8 4 2 1 - - - F8h 3 Low Byte TACH Target 5Dh R/W 4096 2048 1024 512 256 128 64 32 FFh 3 High Byte The TACH Target Registers hold the target tachometer value that is maintained by the RPM-based Fan Speed Control Algorithm. The value in the TACH Target Registers will always reflect the current TACH Target value. If one of the algorithms is enabled, setting the TACH Target Register to FFh will disable the fan driver (set the fan drive setting to 0%). Setting the TACH Target to any other value (from a setting of FFh) will cause the algorithm to invoke the Spin Up Routine after which it will function normally. The Tach Target is not applied until the high byte is written. Once the high byte is written, the current value of both high and low bytes will be used as the next Tach target. 5.18 TACH Reading Registers Table5.28 TACH Reading Registers ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 3Eh R Fan 1 TACH 4096 2048 1024 512 256 128 64 32 FFh Fan 1 TACH 3Fh R 16 8 4 2 1 - - - F8h Low Byte 4Eh R Fan 2 TACH 4096 2048 1024 512 256 128 64 32 FFh Fan 2 TACH 4Fh R 16 8 4 2 1 - - - F8h Low Byte 5Eh R Fan 3 TACH 4096 2048 1024 512 256 128 64 32 FFh Fan 3 TACH 5Fh R 16 8 4 2 1 - - - F8h Low Byte The TACH Reading Registers’ contents describe the current tachometer reading for each of the fans. By default, the data represents the fan speed as the number of 32kHz clock periods that occur for a single revolution of the fan. Equation [2] shows the detailed conversion from TACH measurement (COUNT) to RPM while Equation [3] shows the simplified translation of TACH Reading Register count to RPM assuming a 2-pole fan, measuring 5 edges, with a frequency of 32.768kHz. These equations are solved and tabulated for ease of use in AN17.4 RPM to TACH Counts Conversion. Whenever the high byte register is read, the corresponding low byte data will be loaded to internal shadow registers so that when the low byte is read, the data will always coincide with the previously read high byte. SMSC EMC2303 43 Revision 1.3 (05-18-11) DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet where: poles = number of poles of the fan (typically 2) 1 (n–1) RPM = --------------------×----------------------------------×f ×60 f = the tachometer [2] (poles) 1 TACH TACH COUNT×----- measurement frequency (typically m 32.768kHz) n = number of edges measured (typically 5 for a 2 pole fan) m = the multiplier defined by the RANGE bits 3,932,160×m RPM = -------------------------------------- [3] COUNT COUNT = TACH Reading Register value (in decimal) 5.19 Software Lock Register Table5.29 Software Lock Register ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT Software EFh R/W - - - - - - - LOCK 00h Lock The Software Lock Register controls the software locking of critical registers. This register is software locked. Bit 0 - LOCK - this bit acts on all registers that are designated SWL. When this bit is set, the locked registers become read only and cannot be updated. (cid:132) ‘0’ (default) - all SWL registers can be updated normally. (cid:132) ‘1’ - all SWL registers cannot be updated and a hard-reset is required to unlock them. 5.20 Product Features Register Table5.30 Product Features Register ADDRESS R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT Product FCh R - - ADR[2:0] FAN_SPD [2:0] 00h Features The Product Features register shows those functions that are enabled by external pin states. Bits 5-3 - ADR[2:0] - Indicates the selected SMBus address as determined by the ADDR_SEL pin. Revision 1.3 (05-18-11) 44 SMSC EMC2303 DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet Table5.31 ADDR_SEL Pin Configuration ADR[2:0] SLAVE ADDRESS 2 1 0 0 0 0 0101_110(r/w) 0 0 1 0101_111(r/w) 0 1 0 0101_100(r/w) 0 1 1 0101_101(r/w) 1 0 0 1001_100(r/w) 1 0 1 1001_101(r/w) Bits 2-0 - FAN_SPD[2:0] - Indicates the selected fan speed if the CLK pin pull-up decode is enabled via the ADDR_SEL pin. Table5.32 FAN_SPD Pin Configuration FAN_SPD [2:0] FAN SPEED 2 1 0 0 0 0 0% Drive 0 0 1 30% Drive 0 1 0 50% Drive 0 1 1 75% Drive 1 0 0 100% Drive 5.21 Product ID Register Table5.33 Product ID Register ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT FDh R Product ID 0 0 1 1 0 1 0 1 35h The Product ID Register contains a unique 8-bit word that identifies the product. SMSC EMC2303 45 Revision 1.3 (05-18-11) DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet 5.22 Manufacturer ID Register Table5.34 Manufacturer ID Register ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT FEh R Manufacturer ID 0 1 0 1 1 1 0 1 5Dh The Manufacturer ID Register contains an 8-bit word that identifies SMSC. 5.23 Revision Register Table5.35 Revision Register ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT FFh R Revision 1 0 0 0 0 0 0 0 80h The Revision Register contains an 8-bit word that identifies the die revision. Revision 1.3 (05-18-11) 46 SMSC EMC2303 DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet Chapter 6 Typical Operating Curves The following Typical Operating Curves are included. (cid:132) Supply Current vs. Temperature (cid:132) Supply Current vs. Supply Voltage (cid:132) Fan TACH Accuracy vs. Temperature (cid:132) Fan TACH Accuracy vs. Supply Voltage (cid:132) PWM output frequency vs. Supply Voltage (cid:132) PWM output frequency vs. Temperature (cid:132) FSC Operation Supply Current vs. Ambient Temperature Supply Current vs. Supply Voltage 600 600 550 550 Supply Current (uA)Supply Current (uA) 445050000 Supply Current (uA) Supply Current (uA) 445050000 350 350 300 300 2.95 3.05 3.15 3.25 3.35 3.45 3.55 3.65 -50 0 50 100 150 SuSppulpy pVloyl tVagoelt a(Vg)e (V) AmbieTnte Tmempeprearatuturree ((C°C)) Tachometer Measurement Accuracy vs. Ambient Temperature Tachometer Measurement Accuracy vs. Supply Voltage 1 1 Tach Measurement Accuracy (%Tach Measurement Accuracy (%)----00000000........864202468 ach Measurement Accuracy (%)Tach Measurement Accuracy (% ----00000000........864202468 T -1 -1 2.95 3.05 3.15 3.25 3.35 3.45 3.55 3.65 -50 0 50 100 150 AmbienTt Teemmppeerraatuutrree ( °(CC)) Supply Voltage (V) SMSC EMC2303 47 Revision 1.3 (05-18-11) DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet PWM Frequency vs. Ambient Temperature PWM Frequency vs. Supply Voltage VDD = 3.3V, Base Frequncy = 26Khz TA = 25C, Base Frequncy = 26Khz 27000 27000 26800 26800 26600 26600 WM Frequency (Hz) 2222255666680240000000000 WM Frequency (Hz) 2222255666680240000000000 P 25400 P 25400 25200 25200 25000 25000 -50 0 50 100 150 2.95 3.05 3.15 3.25 3.35 3.45 3.55 3.65 Ambient TTeemmppeerraatuturere ( C(°)C) Supply Voltage (V) FSC Algorithm Spin Up Routine FSC Algorithm Spin Up Routine – NoKick Spin Time = 1.0s; Spin Level = 55%; Updated Time = 200ms; Spin Time = 1.0s; Spin Level = 50%; UpdateTime = 200ms; RPM Target from 0 RPM -> 8000 RPM @ time t = 0 RPM Target from 0 RPM -> 8000 RPM @ time t = 0 PWM PWM Output Output 10x 10x Zoom on Zoom on PWM PWM Output Output t = 0 Duty Cycle Measured = 53.8% t = 0 Duty Cycle Measured = 50% FSC Algorithm PWM Ramping Update Time = 200ms; Max Step = 16 PWM counts RPM Target from 0 RPM -> 8000 RPM @ time t = 0 PWM Output 10x Zoom on PWM Output Spin Up Routine Ends – beginosp enroarmtioanl DMuetya Csuyrcelde Update Time ends, PWM duty Update Time ends, PWM duty cycle changed cycle changed Revision 1.3 (05-18-11) 48 SMSC EMC2303 DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet Chapter 7 Package Drawing 7.1 EMC2303 Package Information Figure7.1 Package Drawing - 12-Pin QFN 4mm x 4mm SMSC EMC2303 49 Revision 1.3 (05-18-11) DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet Figure7.2 Package Dimensions - 12-Pin QFN 4mm x 4mm Revision 1.3 (05-18-11) 50 SMSC EMC2303 DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet Figure7.3 PCB Footprint - 12-Pin QFN 4mm x 4mm 7.2 Package Markings TOP 0.41 LINE: 1 – SMSC Logo without circled (R) symbol 3x 0.56 LINE: 2 – Device Number 2 30 3 - 1 LINE: 3 – Last 7 digits of Lot Number 1 2 34 5 6 a LINE: 4 – Revision and Country Code (RCC) RCC e3 PIN 1 PB-FREE/GREEN SYMBOL (Matte Sn) LINES 1 to 3: CENTER HORIZONTAL ALIGNMENT LINE 4: LEFT HORIZONTAL ALIGNMENT BOTTOM BOTTOM MARKING NOT ALLOWED Figure7.4 EMC2303 Package Markings SMSC EMC2303 51 Revision 1.3 (05-18-11) DATASHEET

Multiple RPM-Based PWM Fan Controller for Three Fans Datasheet Chapter 8 Datasheet Revision History Table8.1 Customer Revision History REVISION LEVEL & DATE SECTION/FIGURE/ENTRY CORRECTION Rev. 1.3 (05-18-11) Section 4.8, "Watchdog The ALERT# pin is asserted when the watchdog is Timer" triggered. Section 5.2, "Configuration Corrected description for MASK bit. Changed “If Register" any bit in either status register is set, the ALERT# pins will be asserted (unless individually masked via the Mask Register)” to “If any bit in the status registers is set, the ALERT# pin will be asserted (unless individually masked via the Fan Interrupt Enable Register)”. Rev. 1.2 (03-22-10) Table2.3, "SMBus Electrical Updated SMBus Data Hold Time spec to 0 us Specifications" Rev. 1.1 (10-12-09) Table2.2, "Electrical Tachometer Setting Accuracy max was changed Specifications" from +/-3% to +/-2%. Chapter6, Typical Added typical operating curves Operating Curves Rev. 1.0 (05-15-09) Initial release of datasheet Revision 1.3 (05-18-11) 52 SMSC EMC2303 DATASHEET

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