dsPIC33FJXXXGPX06/X08/X10 Data Sheet High-Performance, 16-Bit Digital Signal Controllers © 2009 Microchip Technology Inc. DS70286C

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, rfPIC, SmartShunt and UNI/O are registered MICROCHIP MAKES NO REPRESENTATIONS OR trademarks of Microchip Technology Incorporated in the WARRANTIES OF ANY KIND WHETHER EXPRESS OR U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Linear Active Thermistor, MXDEV, MXLAB, INCLUDING BUT NOT LIMITED TO ITS CONDITION, SEEVAL, SmartSensor and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard, devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, In-Circuit Serial hold harmless Microchip from any and all damages, claims, Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB suits, or expenses resulting from such use. No licenses are Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP, conveyed, implicitly or otherwise, under any Microchip PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, intellectual property rights. PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS70286C-page ii © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 High-Performance, 16-Bit Digital Signal Controllers Operating Range: Digital I/O: • Up to 40 MIPS operation (at 3.0-3.6V): • Up to 85 programmable digital I/O pins - Industrial temperature range • Wake-up/Interrupt-on-Change on up to 24 pins (-40°C to +85°C) • Output pins can drive from 3.0V to 3.6V High-Performance DSC CPU: • All digital input pins are 5V tolerant • 4 mA sink on all I/O pins • Modified Harvard architecture • C compiler optimized instruction set On-Chip Flash and SRAM: • 16-bit wide data path • Flash program memory, up to 256 Kbytes • 24-bit wide instructions • Data SRAM, up to 30 Kbytes (includes 2 Kbytes • Linear program memory addressing up to 4M of DMA RAM): instruction words • Linear data memory addressing up to 64 Kbytes System Management: • 83 base instructions: mostly 1 word/1 cycle • Sixteen 16-bit General Purpose Registers • Flexible clock options: • Two 40-bit accumulators: - External, crystal, resonator, internal RC - With rounding and saturation options - Fully integrated PLL • Flexible and powerful addressing modes: - Extremely low jitter PLL - Indirect, Modulo and Bit-Reversed • Power-up Timer • Software stack • Oscillator Start-up Timer/Stabilizer • 16 x 16 fractional/integer multiply operations • Watchdog Timer with its own RC oscillator • 32/16 and 16/16 divide operations • Fail-Safe Clock Monitor • Single-cycle multiply and accumulate: • Reset by multiple sources - Accumulator write back for DSP operations Power Management: - Dual data fetch • Up to ±16-bit shifts for up to 40-bit data • On-chip 2.5V voltage regulator Direct Memory Access (DMA): • Switch between clock sources in real time • Idle, Sleep and Doze modes with fast wake-up • 8-channel hardware DMA: • 2 Kbytes dual ported DMA buffer area Timers/Capture/Compare/PWM: (DMA RAM) to store data transferred via DMA: • Timer/Counters, up to nine 16-bit timers: - Allows data transfer between RAM and a peripheral while CPU is executing code - Can pair up to make four 32-bit timers (no cycle stealing) - 1 timer runs as Real-Time Clock with external • Most peripherals support DMA 32.768 kHz oscillator - Programmable prescaler Interrupt Controller: • Input Capture (up to eight channels): • 5-cycle latency - Capture on up, down or both edges • Up to 63 available interrupt sources - 16-bit capture input functions • Up to five external interrupts - 4-deep FIFO on each capture • Seven programmable priority levels • Output Compare (up to eight channels): • Five processor exceptions - Single or Dual 16-Bit Compare mode - 16-bit Glitchless PWM mode © 2009 Microchip Technology Inc. DS70286C-page 1

dsPIC33FJXXXGPX06/X08/X10 Communication Modules: Analog-to-Digital Converters (ADCs): • 3-wire SPI (up to two modules): • Up to two ADC modules in a device - Framing supports I/O interface to simple • 10-bit, 1.1 Msps or 12-bit, 500 ksps conversion: codecs - Two, four or eight simultaneous samples - Supports 8-bit and 16-bit data - Up to 32 input channels with auto-scanning - Supports all serial clock formats and - Conversion start can be manual or sampling modes synchronized with one of four trigger sources • I2C™ (up to two modules): - Conversion possible in Sleep mode - Full Multi-Master Slave mode support - ±1 LSb max integral nonlinearity - 7-bit and 10-bit addressing - ±1 LSb max differential nonlinearity - Bus collision detection and arbitration - Integrated signal conditioning CMOS Flash Technology: - Slave address masking • Low-power, high-speed Flash technology • UART (up to two modules): • Fully static design - Interrupt on address bit detect • 3.3V (±10%) operating voltage - Interrupt on UART error • Industrial temperature - Wake-up on Start bit from Sleep mode • Low-power consumption - 4-character TX and RX FIFO buffers - LIN bus support Packaging: - IrDA® encoding and decoding in hardware • 100-pin TQFP (14x14x1 mm and 12x12x1 mm) - High-Speed Baud mode • 80-pin TQFP (12x12x1 mm) - Hardware Flow Control with CTS and RTS • 64-pin TQFP (10x10x1 mm) • Data Converter Interface (DCI) module: - Codec interface Note: See the device variant tables for exact - Supports I2S and AC’97 protocols peripheral features per device. - Up to 16-bit data words, up to 16 words per frame - 4-word deep TX and RX buffers • Enhanced CAN (ECAN™ module) 2.0B active (up to 2 modules): - Up to eight transmit and up to 32 receive buffers - 16 receive filters and three masks - Loopback, Listen Only and Listen All Messages modes for diagnostics and bus monitoring - Wake-up on CAN message - Automatic processing of Remote Transmission Requests - FIFO mode using DMA - DeviceNet™ addressing support DS70286C-page 2 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 dsPIC33F PRODUCT FAMILIES The device names, pin counts, memory sizes and peripheral availability of each family are listed below, The dsPIC33F General Purpose Family of devices followed by their pinout diagrams. areideal for a wide variety of 16-bit MCU embedded applications. The controllers with codec interfaces are well-suited for speech and audio processing applications. dsPIC33F General Purpose Family Controllers Device Pins PM(KrFeolbmagysrotaherm y) (KRbyAtMe)(1) 16-bit Timer nput Capture utput CompareStd. PWM CodecInterface ADC UART SPI 2IC™ EnhancedCAN™ (2)O Pins (Max) Packages I O I/ dsPIC33FJ64GP206 64 64 8 9 8 8 1 1 ADC, 18 2 2 1 0 53 PT ch dsPIC33FJ64GP306 64 64 16 9 8 8 1 1 ADC, 18 2 2 2 0 53 PT ch dsPIC33FJ64GP310 100 64 16 9 8 8 1 1 ADC, 32 2 2 2 0 85 PF, PT ch dsPIC33FJ64GP706 64 64 16 9 8 8 1 2 ADC, 18 2 2 2 2 53 PT ch dsPIC33FJ64GP708 80 64 16 9 8 8 1 2 ADC, 24 2 2 2 2 69 PT ch dsPIC33FJ64GP710 100 64 16 9 8 8 1 2 ADC, 32 2 2 2 2 85 PF, PT ch dsPIC33FJ128GP206 64 128 8 9 8 8 1 1 ADC, 18 2 2 1 0 53 PT ch dsPIC33FJ128GP306 64 128 16 9 8 8 1 1 ADC, 18 2 2 2 0 53 PT ch dsPIC33FJ128GP310 100 128 16 9 8 8 1 1 ADC, 32 2 2 2 0 85 PF, PT ch dsPIC33FJ128GP706 64 128 16 9 8 8 1 2 ADC, 18 2 2 2 2 53 PT ch dsPIC33FJ128GP708 80 128 16 9 8 8 1 2 ADC, 24 2 2 2 2 69 PT ch dsPIC33FJ128GP710 100 128 16 9 8 8 1 2 ADC, 32 2 2 2 2 85 PF, PT ch dsPIC33FJ256GP506 64 256 16 9 8 8 1 1 ADC, 18 2 2 2 1 53 PT ch dsPIC33FJ256GP510 100 256 16 9 8 8 1 1 ADC, 32 2 2 2 1 85 PF, PT ch dsPIC33FJ256GP710 100 256 30 9 8 8 1 2 ADC, 32 2 2 2 2 85 PF, PT ch Note 1: RAM size is inclusive of 2 Kbytes DMA RAM. 2: Maximum I/O pin count includes pins shared by the peripheral functions. © 2009 Microchip Technology Inc. DS70286C-page 3

dsPIC33FJXXXGPX06/X08/X10 Pin Diagrams 64-Pin TQFP = Pins are up to 5V tolerant 54 DD RR SDO/RG13SDI/RG12SCK/RG14G0G1F1F0 DD/VCAPDDCOREC8/CN16/RD7C7/CN15/RD6C6/IC6/CN14/C5/IC5/CN13/C4/RD3C3/RD2C2/RD1 CCCRRRRVVOOOOOOO 4321098765432109 6666655555555554 COFS/RG15 1 48 PGEC2/SOSCO/T1CK/CN0/RC14 AN16/T2CK/T7CK/RC1 2 47 PGED2/SOSCI/T4CK/CN1/RC13 AN17/T3CK/T6CK/RC2 3 46 OC1/RD0 SCK2/CN8/RG6 4 45 IC4/INT4/RD11 SDI2/CN9/RG7 5 44 IC3/INT3/RD10 SDO2/CN10/RG8 6 43 IC2/U1CTS/INT2/RD9 MCLR 7 42 IC1/INT1/RD8 SS2/CN11/RG9 8 dsPIC33FJ64GP206 41 VSS VSS 9 dsPIC33FJ128GP206 40 OSC2/CLKO/RC15 VDD 10 39 OSC1/CLKIN/RC12 AN5/IC8/CN7/RB5 11 38 VDD AN4/IC7/CN6/RB4 12 37 SCL1/RG2 AN3/CN5/RB3 13 36 SDA1/RG3 AN2/SS1/CN4/RB2 14 35 U1RTS/SCK1/INT0/RF6 PGEC3/AN1/VREF-/CN3/RB1 15 34 U1RX/SDI1/RF2 PGED3/AN0/VREF+/CN2/RB0 16 33 U1TX/SDO1/RF3 7890123456789012 1112222222222333 6 D S8901 S D234545 B D SBB11 S D1111FF R VVRRBBVVBBBBRR PGEC1/AN6/OCFA/PGED1/AN7/RB7AAU2CTS/AN8/AN9/TMS/AN10/RTDO/AN11/R TCK/AN12/RTDI/AN13/RU2RTS/AN14/RAN15/OCFB/CN12/RU2RX/CN17/U2TX/CN18/ DS70286C-page 4 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 Pin Diagrams (Continued) 64-Pin TQFP = Pins are up to 5V tolerant 54 DD RR SDO/RG13SDI/RG12SCK/RG14G0G1F1F0 DD/VCAPDDCOREC8/CN16/RD7C7/CN15/RD6C6/IC6/CN14/C5/IC5/CN13/C4/RD3C3/RD2C2/RD1 CCCRRRRVVOOOOOOO 4321098765432109 6666655555555554 COFS/RG15 1 48 PGEC2/SOSCO/T1CK/CN0/RC14 AN16/T2CK/T7CK/RC1 2 47 PGED2/SOSCI/T4CK/CN1/RC13 AN17/T3CK/T6CK/RC2 3 46 OC1/RD0 SCK2/CN8/RG6 4 45 IC4/INT4/RD11 SDI2/CN9/RG7 5 44 IC3/INT3/RD10 SDO2/CN10/RG8 6 43 IC2/U1CTS/INT2/RD9 MCLR 7 42 IC1/INT1/RD8 dsPIC33FJ64GP306 SS2/CN11/RG9 8 41 VSS VSS 9 dsPIC33FJ128GP306 40 OSC2/CLKO/RC15 VDD 10 39 OSC1/CLKIN/RC12 AN5/IC8/CN7/RB5 11 38 VDD AN4/IC7/CN6/RB4 12 37 SCL1/RG2 AN3/CN5/RB3 13 36 SDA1/RG3 AN2/SS1/CN4/RB2 14 35 U1RTS/SCK1/INT0/RF6 PGEC3/AN1/VREF-/CN3/RB1 15 34 U1RX/SDI1/RF2 PGED3/AN0/VREF+/CN2/RB0 16 33 U1TX/SDO1/RF3 7890123456789012 1112222222222333 6 D S8901 S D234545 B D SBB11 S D1111FF R VVRRBBVVBBBBRR PGEC1/AN6/OCFA/PGED1/AN7/RB7AAU2CTS/AN8/AN9/TMS/AN10/RTDO/AN11/R TCK/AN12/RTDI/AN13/RU2RTS/AN14/RAN15/OCFB/CN12/RU2RX/SDA2/CN17/U2TX/SCL2/CN18/ © 2009 Microchip Technology Inc. DS70286C-page 5

dsPIC33FJXXXGPX06/X08/X10 Pin Diagrams (Continued) 64-Pin TQFP = Pins are up to 5V tolerant 54 DD RR SDO/RG13SDI/RG12SCK/RG14G0G11TX/RF11RX/RF0 DD/VCAPDDCOREC8/CN16/RD7C7/CN15/RD6C6/IC6/CN14/C5/IC5/CN13/C4/RD3C3/RD2C2/RD1 CCCRRCCVVOOOOOOO 4321098765432109 6666655555555554 COFS/RG15 1 48 PGEC2/SOSCO/T1CK/CN0/RC14 AN16/T2CK/T7CK/RC1 2 47 PGED2/SOSCI/T4CK/CN1/RC13 AN17/T3CK/T6CK/RC2 3 46 OC1/RD0 SCK2/CN8/RG6 4 45 IC4/INT4/RD11 SDI2/CN9/RG7 5 44 IC3/INT3/RD10 SDO2/CN10/RG8 6 43 IC2/U1CTS/INT2/RD9 MCLR 7 42 IC1/INT1/RD8 SS2/CN11/RG9 8 41 VSS dsPIC33FJ256GP506 VSS 9 40 OSC2/CLKO/RC15 VDD 10 39 OSC1/CLKIN/RC12 AN5/IC8/CN7/RB5 11 38 VDD AN4/IC7/CN6/RB4 12 37 SCL1/RG2 AN3/CN5/RB3 13 36 SDA1/RG3 AN2/SS1/CN4/RB2 14 35 U1RTS/SCK1/INT0/RF6 PGEC3/AN1/VREF-/CN3/RB1 15 34 U1RX/SDI1/RF2 PGED3/AN0/VREF+/CN2/RB0 16 33 U1TX/SDO1/RF3 7890123456789012 1112222222222333 6 D S8901 S D234545 B D SBB11 S D1111FF R VVRRBBVVBBBBRR PGEC1/AN6/OCFA/PGED1/AN7/RB7AAU2CTS/AN8/AN9/TMS/AN10/RTDO/AN11/R TCK/AN12/RTDI/AN13/RU2RTS/AN14/RAN15/OCFB/CN12/RU2RX/SDA2/CN17/U2TX/SCL2/CN18/ DS70286C-page 6 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 Pin Diagrams (Continued) 64-Pin TQFP = Pins are up to 5V tolerant 54 DD RR SDO/RG13SDI/RG12SCK/RG142RX/RG02TX/RG11TX/RF11RX/RF0 DD/VCAPDDCOREC8/CN16/RD7C7/CN15/RD6C6/IC6/CN14/C5/IC5/CN13/C4/RD3C3/RD2C2/RD1 CCCCCCCVVOOOOOOO 4321098765432109 6666655555555554 COFS/RG15 1 48 PGEC2/SOSCO/T1CK/CN0/RC14 AN16/T2CK/T7CK/RC1 2 47 PGED2/SOSCI/T4CK/CN1/RC13 AN17/T3CK/T6CK/RC2 3 46 OC1/RD0 SCK2/CN8/RG6 4 45 IC4/INT4/RD11 SDI2/CN9/RG7 5 44 IC3/INT3/RD10 SDO2/CN10/RG8 6 43 IC2/U1CTS/INT2/RD9 MCLR 7 42 IC1/INT1/RD8 dsPIC33FJ64GP706 SS2/CN11/RG9 8 41 VSS VSS 9 dsPIC33FJ128GP706 40 OSC2/CLKO/RC15 VDD 10 39 OSC1/CLKIN/RC12 AN5/IC8/CN7/RB5 11 38 VDD AN4/IC7/CN6/RB4 12 37 SCL1/RG2 AN3/CN5/RB3 13 36 SDA1/RG3 AN2/SS1/CN4/RB2 14 35 U1RTS/SCK1/INT0/RF6 PGEC3/AN1/VREF-/CN3/RB1 15 34 U1RX/SDI1/RF2 PGED3/AN0/VREF+/CN2/RB0 16 33 U1TX/SDO1/RF3 7890123456789012 1112222222222333 6 D S8901 S D234545 B D SBB11 S D1111FF R VVRRBBVVBBBBRR PGEC1/AN6/OCFA/PGED1/AN7/RB7AAU2CTS/AN8/AN9/TMS/AN10/RTDO/AN11/R TCK/AN12/RTDI/AN13/RU2RTS/AN14/RAN15/OCFB/CN12/RU2RX/SDA2/CN17/U2TX/SCL2/CN18/ © 2009 Microchip Technology Inc. DS70286C-page 7

dsPIC33FJXXXGPX06/X08/X10 Pin Diagrams (Continued) 80-Pin TQFP = Pins are up to 5V tolerant CSDO/RG13 CSDI/RG12 CSCK/RG14 AN23/CN23/RA7 AN22/CN22/RA6C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD V/VCAPDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/CN14/RD5OC5/CN13/RD4 IC6/CN19/RD13 IC5/RD12OC4/RD3 OC3/RD2 OC2/RD1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 8 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 COFS/RG15 1 60 PGEC2/SOSCO/T1CK/CN0/RC14 AN16/T2CK/T7CK/RC1 2 59 PGED2/SOSCI/CN1/RC13 AN17/T3CK/T6CK/RC2 3 58 OC1/RD0 AN18/T4CK/T9CK/RC3 4 57 IC4/RD11 AN19/T5CK/T8CK/RC4 5 56 IC3/RD10 SCK2/CN8/RG6 6 55 IC2/RD9 SDI2/CN9/RG7 7 54 IC1/RD8 SDO2/CN10/RG8 8 53 SDA2/INT4/RA3 MCLR 9 52 SCL2/INT3/RA2 SS2/CN11/RG9 10 dsPIC33FJ64GP708 51 VSS VSS 11 dsPIC33FJ128GP708 50 OSC2/CLKO/RC15 VDD 12 49 OSC1/CLKIN/RC12 TMS/AN20/INT1/RA12 13 48 VDD TDO/AN21/INT2/RA13 14 47 SCL1/RG2 AN5/CN7/RB5 15 46 SDA1/RG3 AN4/CN6/RB4 16 45 SCK1/INT0/RF6 AN3/CN5/RB3 17 44 SDI1/RF7 AN2/SS1/CN4/RB2 18 43 SDO1/RF8 PGEC3/AN1/CN3/RB1 19 42 U1RX/RF2 PGED3/AN0/CN2/RB0 20 41 U1TX/RF3 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 4 PGEC1/AN6/OCFA/RB6 PGED1/AN7/RB7 V-/RA9REF V+/RA10REF AVDD AVSS U2CTS/AN8/RB8 AN9/RB9 AN10/RB10 AN11/RB11 VSS VDD TCK/AN12/RB12 TDI/AN13/RB13 U2RTS/AN14/RB14 AN15/OCFB/CN12/RB15 IC7/U1CTS/CN20/RD14 IC8/U1RTS/CN21/RD15 U2RX/CN17/RF4 U2TX/CN18/RF5 DS70286C-page 8 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 Pin Diagrams (Continued) 100-Pin TQFP = Pins are up to 5V tolerant AN28/RE4AN27/RE3AN26/RE2CSDO/RG13CSDI/RG12CSCK/RG14AN25/RE1AN24/RE0AN23/CN23/RA7AN22/CN22/RA6RG0RG1RF1RF0VDDV/VCAPDDCOREOC8/CN16/RD7OC7/CN15/RD6OC6/CN14/RD5OC5/CN13/RD4IC6/CN19/RD13IC5/RD12OC4/RD3OC3/RD2OC2/RD1 0987654321098765432109876 0999999999988888888887777 1 COFS/RG15 1 75 VSS VDD 2 74 PGEC2/SOSCO/T1CK/CN0/RC14 AN29/RE5 3 73 PGED2/SOSCI/CN1/RC13 AN30/RE6 4 72 OC1/RD0 AN31/RE7 5 71 IC4/RD11 AN16/T2CK/T7CK/RC1 6 70 IC3/RD10 AN17/T3CK/T6CK/RC2 7 69 IC2/RD9 AN18/T4CK/T9CK/RC3 8 68 IC1/RD8 AN19/T5CK/T8CK/RC4 9 67 INT4/RA15 SCK2/CN8/RG6 10 66 INT3/RA14 SDI2/CN9/RG7 11 65 VSS SDO2/CN10/RG8 12 64 OSC2/CLKO/RC15 MCLR 13 dsPIC33FJ64GP310 63 OSC1/CLKIN/RC12 SS2/CN11/RG9 14 dsPIC33FJ128GP310 62 VDD VSS 15 61 TDO/RA5 VDD 16 60 TDI/RA4 TMS/RA0 17 59 SDA2/RA3 AN20/INT1/RA12 18 58 SCL2/RA2 AN21/INT2/RA13 19 57 SCL1/RG2 AN5/CN7/RB5 20 56 SDA1/RG3 AN4/CN6/RB4 21 55 SCK1/INT0/RF6 AN3/CN5/RB3 22 54 SDI1/RF7 AN2/SS1/CN4/RB2 23 53 SDO1/RF8 PGEC3/AN1/CN3/RB1 24 52 U1RX/RF2 PGED3/AN0/CN2/RB0 25 51 U1TX/RF3 6789012345678901234567890 2222333333333344444444445 PGEC1/AN6/OCFA/RB6PGED1/AN7/RB7V-/RA9REFV+/RA10REFAVDDAVSSAN8/RB8AN9/RB9AN10/RB10AN11/RB11VSSVDDTCK/RA1U2RTS/RF13U2CTS/RF12AN12/RB12AN13/RB13AN14/RB14AN15/OCFB/CN12/RB15VSSVDDIC7/U1CTS/CN20/RD14IC8/U1RTS/CN21/RD15U2RX/CN17/RF4U2TX/CN18/RF5 © 2009 Microchip Technology Inc. DS70286C-page 9

dsPIC33FJXXXGPX06/X08/X10 Pin Diagrams (Continued) 100-Pin TQFP = Pins are up to 5V tolerant AN28/RE4AN27/RE3AN26/RE2CSDO/RG13CSDI/RG12CSCK/RG14AN25/RE1AN24/RE0AN23/CN23/RA7AN22/CN22/RA6RG0RG1C1TX/RF1C1RX/RF0VDDV/VCAPDDCOREOC8/CN16/RD7OC7/CN15/RD6OC6/CN14/RD5OC5/CN13/RD4IC6/CN19/RD13IC5/RD12OC4/RD3OC3/RD2OC2/RD1 0987654321098765432109876 0999999999988888888887777 1 COFS/RG15 1 75 VSS VDD 2 74 PGEC2/SOSCO/T1CK/CN0/RC14 AN29/RE5 3 73 PGED2/SOSCI/CN1/RC13 AN30/RE6 4 72 OC1/RD0 AN31/RE7 5 71 IC4/RD11 AN16/T2CK/T7CK/RC1 6 70 IC3/RD10 AN17/T3CK/T6CK/RC2 7 69 IC2/RD9 AN18/T4CK/T9CK/RC3 8 68 IC1/RD8 AN19/T5CK/T8CK/RC4 9 67 INT4/RA15 SCK2/CN8/RG6 10 66 INT3/RA14 SDI2/CN9/RG7 11 65 VSS SDO2/CN10/RG8 12 64 OSC2/CLKO/RC15 MCLR 13 dsPIC33FJ256GP510 63 OSC1/CLKIN/RC12 SS2/CN11/RG9 14 62 VDD VSS 15 61 TDO/RA5 VDD 16 60 TDI/RA4 TMS/RA0 17 59 SDA2/RA3 AN20/INT1/RA12 18 58 SCL2/RA2 AN21/INT2/RA13 19 57 SCL1/RG2 AN5/CN7/RB5 20 56 SDA1/RG3 AN4/CN6/RB4 21 55 SCK1/INT0/RF6 AN3/CN5/RB3 22 54 SDI1/RF7 AN2/SS1/CN4/RB2 23 53 SDO1/RF8 PGEC3/AN1/CN3/RB1 24 52 U1RX/RF2 PGED3/AN0/CN2/RB0 25 51 U1TX/RF3 6789012345678901234567890 2222333333333344444444445 PGEC1/AN6/OCFA/RB6PGED1/AN7/RB7V-/RA9REFV+/RA10REFAVDDAVSSAN8/RB8AN9/RB9AN10/RB10AN11/RB11VSSVDDTCK/RA1U2RTS/RF13U2CTS/RF12AN12/RB12AN13/RB13AN14/RB14AN15/OCFB/CN12/RB15VSSVDDIC7/U1CTS/CN20/RD14IC8/U1RTS/CN21/RD15U2RX/CN17/RF4U2TX/CN18/RF5 DS70286C-page 10 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 Pin Diagrams (Continued) 100-Pin TQFP = Pins are up to 5V tolerant AN28/RE4AN27/RE3AN26/RE2CSDO/RG13CSDI/RG12CSCK/RG14AN25/RE1AN24/RE0AN23/CN23/RA7AN22/CN22/RA6C2RX/RG0C2TX/RG1C1TX/RF1C1RX/RF0VDD/VVCAPDDCOREOC8/CN16/RD7OC7/CN15/RD6OC6/CN14/RD5OC5/CN13/RD4IC6/CN19/RD13IC5/RD12OC4/RD3OC3/RD2OC2/RD1 0987654321098765432109876 0999999999988888888887777 1 COFS/RG15 1 75 VSS VDD 2 74 PGEC2/SOSCO/T1CK/CN0/RC14 AN29/RE5 3 73 PGED2/SOSCI/CN1/RC13 AN30/RE6 4 72 OC1/RD0 AN31/RE7 5 71 IC4/RD11 AN16/T2CK/T7CK/RC1 6 70 IC3/RD10 AN17/T3CK/T6CK/RC2 7 69 IC2/RD9 AN18/T4CK/T9CK/RC3 8 68 IC1/RD8 AN19/T5CK/T8CK/RC4 9 67 INT4/RA15 SCK2/CN8/RG6 10 66 INT3/RA14 SDI2/CN9/RG7 11 65 VSS SDO2/CN10/RG8 12 dsPIC33FJ64GP710 64 OSC2/CLKO/RC15 MCLR 13 dsPIC33FJ128GP710 63 OSC1/CLKIN/RC12 SS2/CN11/RG9 14 dsPIC33FJ256GP710 62 VDD VSS 15 61 TDO/RA5 VDD 16 60 TDI/RA4 TMS/RA0 17 59 SDA2/RA3 AN20/INT1/RA12 18 58 SCL2/RA2 AN21/INT2/RA13 19 57 SCL1/RG2 AN5/CN7/RB5 20 56 SDA1/RG3 AN4/CN6/RB4 21 55 SCK1/INT0/RF6 AN3/CN5/RB3 22 54 SDI1/RF7 AN2/SS1/CN4/RB2 23 53 SDO1/RF8 PGEC3/AN1/CN3/RB1 24 52 U1RX/RF2 PGED3/AN0/CN2/RB0 25 51 U1TX/RF3 6789012345678901234567890 2222333333333344444444445 PGEC1/AN6/OCFA/RB6PGED1/AN7/RB7V-/RA9REFV+/RA10REFAVDDAVSSAN8/RB8AN9/RB9AN10/RB10AN11/RB11VSSVDDTCK/RA1U2RTS/RF13U2CTS/RF12AN12/RB12AN13/RB13AN14/RB14AN15/OCFB/CN12/RB15VSSVDDIC7/U1CTS/CN20/RD14IC8/U1RTS/CN21/RD15U2RX/CN17/RF4U2TX/CN18/RF5 © 2009 Microchip Technology Inc. DS70286C-page 11

dsPIC33FJXXXGPX06/X08/X10 Table of Contents dsPIC33F Product Families...................................................................................................................................................................3 1.0 Device Overview........................................................................................................................................................................13 2.0 Guidelines for Getting Started with 16-Bit Digital Signal Controllers..........................................................................................17 3.0 CPU............................................................................................................................................................................................21 4.0 Memory Organization.................................................................................................................................................................33 5.0 Flash Program Memory..............................................................................................................................................................71 6.0 Reset .........................................................................................................................................................................................77 7.0 Interrupt Controller.....................................................................................................................................................................81 8.0 Direct Memory Access (DMA)..................................................................................................................................................127 9.0 Oscillator Configuration............................................................................................................................................................137 10.0 Power-Saving Features............................................................................................................................................................147 11.0 I/O Ports...................................................................................................................................................................................155 12.0 Timer1......................................................................................................................................................................................157 13.0 Timer2/3, Timer4/5, Timer6/7 and Timer8/9 ............................................................................................................................159 14.0 Input Capture............................................................................................................................................................................165 15.0 Output Compare.......................................................................................................................................................................167 16.0 Serial Peripheral Interface (SPI)...............................................................................................................................................171 17.0 Inter-Integrated Circuit™ (I2C™)..............................................................................................................................................177 18.0 Universal Asynchronous Receiver Transmitter (UART)...........................................................................................................185 19.0 Enhanced CAN (ECAN™) Module...........................................................................................................................................191 20.0 Data Converter Interface (DCI) Module....................................................................................................................................217 21.0 10-Bit/12-Bit Analog-to-Digital Converter (ADC)......................................................................................................................225 22.0 Special Features......................................................................................................................................................................237 23.0 Instruction Set Summary..........................................................................................................................................................245 24.0 Development Support...............................................................................................................................................................253 25.0 Electrical Characteristics..........................................................................................................................................................257 26.0 Packaging Information..............................................................................................................................................................297 Appendix A: Revision History.............................................................................................................................................................307 Index................................................................................................................................................................................................. 313 The Microchip Web Site.....................................................................................................................................................................317 Customer Change Notification Service..............................................................................................................................................317 Customer Support..............................................................................................................................................................................317 Reader Response..............................................................................................................................................................................318 Product Identification System.............................................................................................................................................................319 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS70286C-page 12 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 1.0 DEVICE OVERVIEW This feature makes the family suitable for a wide variety of high-performance digital signal control applications. Note: This data sheet summarizes the features The device is pin compatible with the PIC24H family of of the dsPIC33FJXXXGPX06/X08/X10 devices, and also share a very high degree of family of devices. However, it is not compatibility with the dsPIC30F family devices. This intended to be a comprehensive reference allows for easy migration between device families as may source. To complement the information in be necessitated by the specific functionality, this data sheet, refer to the latest family computational resource and system cost requirements of reference sections of the “dsPIC33F the application. Family Reference Manual”, which is The dsPIC33FJXXXGPX06/X08/X10 device family available from the Microchip web site employs a powerful 16-bit architecture that seamlessly (www.microchip.com). integrates the control features of a Microcontroller This document contains device specific information for (MCU) with the computational capabilities of a Digital the following devices: Signal Processor (DSP). The resulting functionality is ideal for applications that rely on high-speed, repetitive • dsPIC33FJ64GP206 computations, as well as control. • dsPIC33FJ64GP306 The DSP engine, dual 40-bit accumulators, hardware • dsPIC33FJ64GP310 support for division operations, barrel shifter, 17 x 17 • dsPIC33FJ64GP706 multiplier, a large array of 16-bit working registers and • dsPIC33FJ64GP708 a wide variety of data addressing modes, together • dsPIC33FJ64GP710 provide the dsPIC33FJXXXGPX06/X08/X10 Central • dsPIC33FJ128GP206 Processing Unit (CPU) with extensive mathematical processing capability. Flexible and deterministic • dsPIC33FJ128GP306 interrupt handling, coupled with a powerful array of • dsPIC33FJ128GP310 peripherals, renders the • dsPIC33FJ128GP706 dsPIC33FJXXXGPX06/X08/X10 devices suitable for • dsPIC33FJ128GP708 control applications. Further, Direct Memory Access • dsPIC33FJ128GP710 (DMA) enables overhead-free transfer of data between several peripherals and a dedicated DMA RAM. • dsPIC33FJ256GP506 Reliable, field programmable Flash program memory • dsPIC33FJ256GP510 ensures scalability of applications that use • dsPIC33FJ256GP710 dsPIC33FJXXXGPX06/X08/X10 devices. The dsPIC33FJXXXGPX06/X08/X10 General Purpose Figure1-1 illustrates a general block diagram of the Family of device includes devices with a wide range of various core and peripheral modules in the pin counts (64, 80 and 100), different program memory dsPIC33FJXXXGPX06/X08/X10 family of devices. sizes (64 Kbytes, 128 Kbytes and 256 Kbytes) and Table1-1 provides the functions of the various pins different RAM sizes (8 Kbytes, 16 Kbytes and illustrated in the pinout diagrams. 30Kbytes). © 2009 Microchip Technology Inc. DS70286C-page 13

dsPIC33FJXXXGPX06/X08/X10 FIGURE 1-1: dsPIC33FJXXXGPX06/X08/X10 GENERAL BLOCK DIAGRAM PSV and Table Data Access Control Block Y Data Bus Interrupt X Data Bus PORTA Controller 16 8 16 16 16 DMA Data Latch Data Latch RAM 23 PCU PCH PCL X RAM Y RAM 23 PORTB Program Counter Stack Loop Address Address Control Control Latch Latch Logic Logic DMA 16 23 Controller 16 16 PORTC Address Generator Units Address Latch Program Memory EA MUX PORTD Data Latch ROM Latch 24 16 16 a at Instruction D Decode and al Control Instruction Reg er Lit 16 PORTE Control Signals to Various Blocks DSP Engine OSC2/CLKO Timing Power-up OSC1/CLKI Generation Timer PORTF Oscillator 16 x 16 FRC/LPRC Start-up Timer W Register Array Oscillators Divide Support Power-on 16 Reset Precision Band Gap Watchdog Reference Timer PORTG Brown-out 16-bit ALU Voltage Reset Regulator 16 VCAP/VDDCORE VDD, VSS MCLR Timers OC/ DCI ADC1,2 ECAN1,2 1-9 PWM1-8 IC1-8 CN1-23 SPI1,2 I2C1,2 UART1,2 Note: Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins and features present on each device. DS70286C-page 14 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Buffer Pin Name Description Type Type AN0-AN31 I Analog Analog input channels. AVDD P P Positive supply for analog modules. This pin must be connected at all times. AVSS P P Ground reference for analog modules. CLKI I ST/CMOS External clock source input. Always associated with OSC1 pin function. CLKO O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. CN0-CN23 I ST Input change notification inputs. Can be software programmed for internal weak pull-ups on all inputs. COFS I/O ST Data Converter Interface frame synchronization pin. CSCK I/O ST Data Converter Interface serial clock input/output pin. CSDI I ST Data Converter Interface serial data input pin. CSDO O — Data Converter Interface serial data output pin. C1RX I ST ECAN1 bus receive pin. C1TX O — ECAN1 bus transmit pin. C2RX I ST ECAN2 bus receive pin. C2TX O — ECAN2 bus transmit pin. PGED1 I/O ST Data I/O pin for programming/debugging communication channel 1. PGEC1 I ST Clock input pin for programming/debugging communication channel 1. PGED2 I/O ST Data I/O pin for programming/debugging communication channel 2. PGEC2 I ST Clock input pin for programming/debugging communication channel 2. PGED3 I/O ST Data I/O pin for programming/debugging communication channel 3. PGEC3 I ST Clock input pin for programming/debugging communication channel 3. IC1-IC8 I ST Capture inputs 1 through 8. INT0 I ST External interrupt 0. INT1 I ST External interrupt 1. INT2 I ST External interrupt 2. INT3 I ST External interrupt 3. INT4 I ST External interrupt 4. MCLR I/P ST Master Clear (Reset) input. This pin is an active-low Reset to the device. OCFA I ST Compare Fault A input (for Compare Channels 1, 2, 3 and 4). OCFB I ST Compare Fault B input (for Compare Channels 5, 6, 7 and 8). OC1-OC8 O — Compare outputs 1 through 8. OSC1 I ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. OSC2 I/O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. RA0-RA7 I/O ST PORTA is a bidirectional I/O port. RA9-RA10 I/O ST RA12-RA15 I/O ST RB0-RB15 I/O ST PORTB is a bidirectional I/O port. RC1-RC4 I/O ST PORTC is a bidirectional I/O port. RC12-RC15 I/O ST RD0-RD15 I/O ST PORTD is a bidirectional I/O port. RE0-RE7 I/O ST PORTE is a bidirectional I/O port. RF0-RF8 I/O ST PORTF is a bidirectional I/O port. RF12-RF13 I/O ST Legend: CMOS = CMOS compatible input or output; Analog = Analog input; P = Power ST = Schmitt Trigger input with CMOS levels; O = Output; I = Input © 2009 Microchip Technology Inc. DS70286C-page 15

dsPIC33FJXXXGPX06/X08/X10 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name Description Type Type RG0-RG3 I/O ST PORTG is a bidirectional I/O port. RG6-RG9 I/O ST RG12-RG15 I/O ST SCK1 I/O ST Synchronous serial clock input/output for SPI1. SDI1 I ST SPI1 data in. SDO1 O — SPI1 data out. SS1 I/O ST SPI1 slave synchronization or frame pulse I/O. SCK2 I/O ST Synchronous serial clock input/output for SPI2. SDI2 I ST SPI2 data in. SDO2 O — SPI2 data out. SS2 I/O ST SPI2 slave synchronization or frame pulse I/O. SCL1 I/O ST Synchronous serial clock input/output for I2C1. SDA1 I/O ST Synchronous serial data input/output for I2C1. SCL2 I/O ST Synchronous serial clock input/output for I2C2. SDA2 I/O ST Synchronous serial data input/output for I2C2. SOSCI I ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS otherwise. SOSCO O — 32.768 kHz low-power oscillator crystal output. TMS I ST JTAG Test mode select pin. TCK I ST JTAG test clock input pin. TDI I ST JTAG test data input pin. TDO O — JTAG test data output pin. T1CK I ST Timer1 external clock input. T2CK I ST Timer2 external clock input. T3CK I ST Timer3 external clock input. T4CK I ST Timer4 external clock input. T5CK I ST Timer5 external clock input. T6CK I ST Timer6 external clock input. T7CK I ST Timer7 external clock input. T8CK I ST Timer8 external clock input. T9CK I ST Timer9 external clock input. U1CTS I ST UART1 clear to send. U1RTS O — UART1 ready to send. U1RX I ST UART1 receive. U1TX O — UART1 transmit. U2CTS I ST UART2 clear to send. U2RTS O — UART2 ready to send. U2RX I ST UART2 receive. U2TX O — UART2 transmit. VDD P — Positive supply for peripheral logic and I/O pins. VCAP/VDDCORE P — CPU logic filter capacitor connection. VSS P — Ground reference for logic and I/O pins. VREF+ I Analog Analog voltage reference (high) input. VREF- I Analog Analog voltage reference (low) input. Legend: CMOS = CMOS compatible input or output; Analog = Analog input; P = Power ST = Schmitt Trigger input with CMOS levels; O = Output; I = Input DS70286C-page 16 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 2.0 GUIDELINES FOR GETTING 2.2 Decoupling Capacitors STARTED WITH 16-BIT The use of decoupling capacitors on every pair of DIGITAL SIGNAL power supply pins, such as VDD, VSS, AVDD and CONTROLLERS AVSS is required. Consider the following criteria when using decoupling Note: This data sheet summarizes the features capacitors: of the dsPIC33FJXXXGPX06/X08/X10 • Value and type of capacitor: Recommendation family of devices. It is not intended to be a of 0.1 µF (100 nF), 10-20V. This capacitor should comprehensive reference source. To be a low-ESR and have resonance frequency in complement the information in this data the range of 20MHz and higher. It is sheet, refer to the “dsPIC33F Family recommended that ceramic capacitors be used. Reference Manual”, which is available from the Microchip website • Placement on the printed circuit board: The (www.microchip.com). decoupling capacitors should be placed as close to the pins as possible. It is recommended to 2.1 Basic Connection Requirements place the capacitors on the same side of the board as the device. If space is constricted, the Getting started with the capacitor can be placed on another layer on the dsPIC33FJXXXGPX06/X08/X10 family of 16-bit Digital PCB using a via; however, ensure that the trace Signal Controllers (DSCs) requires attention to a length from the pin to the capacitor is within minimal set of device pin connections before one-quarter inch (6mm) in length. proceeding with development. The following is a list of • Handling high frequency noise: If the board is pin names, which must always be connected: experiencing high frequency noise, upward of • All VDD and VSS pins tens of MHz, add a second ceramic-type capacitor (see Section2.2 “Decoupling Capacitors”) in parallel to the above described decoupling capacitor. The value of the second capacitor can • All AVDD and AVSS pins (regardless if ADC module be in the range of 0.01µF to 0.001µF. Place this is not used) second capacitor next to the primary decoupling (see Section2.2 “Decoupling Capacitors”) capacitor. In high-speed circuit designs, consider • VCAP/VDDCORE implementing a decade pair of capacitances as (see Section2.3 “Capacitor on Internal Voltage close to the power and ground pins as possible. Regulator (VCAP/VDDCORE)”) For example, 0.1 µF in parallel with 0.001 µF. • MCLR pin • Maximizing performance: On the board layout (see Section2.4 “Master Clear (MCLR) Pin”) from the power supply circuit, run the power and • PGECx/PGEDx pins used for In-Circuit Serial return traces to the decoupling capacitors first, Programming™ (ICSP™) and debugging purposes and then to the device pins. This ensures that the (see Section2.5 “ICSP Pins”) decoupling capacitors are first in the power chain. • OSC1 and OSC2 pins when external oscillator Equally important is to keep the trace length source is used between the capacitor and the power pins to a (see Section2.6 “External Oscillator Pins”) minimum thereby reducing PCB track inductance. Additionally, the following pins may be required: • VREF+/VREF- pins used when external voltage reference for ADC module is implemented Note: The AVDD and AVSS pins must be connected independent of the ADC voltage reference source. © 2009 Microchip Technology Inc. DS70286C-page 17

dsPIC33FJXXXGPX06/X08/X10 FIGURE 2-1: RECOMMENDED 2.4 Master Clear (MCLR) Pin MINIMUM CONNECTION The MCLR pin provides for two specific device functions: 0.1 µF • Device Reset VDD Ceramic • Device programming and debugging During device programming and debugging, the R RE DD SS O V V resistance and capacitance that can be added to the R1 C MCLR VDD pin must be considered. Device programmers and /P debuggers drive the MCLR pin. Consequently, A C VC specific voltage levels (VIH and VIL) and fast signal dsPIC33F transitions must not be adversely affected. Therefore, specific values of R and C will need to be adjusted VSS VDD based on the application and PCB requirements. VDD VSS For example, as shown in Figure2-2, it is 0.1 µF D S 0.1 µF recommended that the capacitor C, be isolated from Ceramic AVD AVS VDD VSS Ceramic the MCLR pin during programming and debugging operations. 0.1 µF 0.1 µF 10Ω Ceramic Ceramic Place the components shown in Figure2-2 within one-quarter inch (6mm) from the MCLR pin. FIGURE 2-2: EXAMPLE OF MCLR PIN 2.2.1 TANK CAPACITORS CONNECTIONS On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits including DSCs to supply a local VDD power source. The value of the tank capacitor should be determined based on the trace resistance that con- R nects the power supply source to the device, and the R1 MCLR maximum current drawn by the device in the applica- tion. In other words, select the tank capacitor so that it JP dsPIC33F meets the acceptable voltage sag at the device. Typical values range from 4.7µF to 47µF. C 2.3 Capacitor on Internal Voltage Regulator (VCAP/VDDCORE) Note 1: R≤ 10kΩ is recommended. A suggested starting value is 10kΩ. Ensure that the A low-ESR (< 5 Ohms) capacitor is required on the MCLR pin VIH and VIL specifications are met. VCAP/VDDCORE pin, which is used to stabilize the 2: R1≤ 470Ω will limit any current flowing into voltage regulator output voltage. The VCAP/VDDCORE MCLR from the external capacitor C, in the pin must not be connected to VDD, and must have a event of MCLR pin breakdown, due to capacitor between 4.7µF and 10 µF, 16V connected to Electrostatic Discharge (ESD) or Electrical ground. The type can be ceramic or tantalum. Refer to Overstress (EOS). Ensure that the MCLR pin Section25.0 “Electrical Characteristics” for VIH and VIL specifications are met. additional information. The placement of this capacitor should be close to the VCAP/VDDCORE. It is recommended that the trace length not exceed one-quarter inch (6 mm). Refer to Section22.2 “On-Chip Voltage Regulator” for details. DS70286C-page 18 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 2.5 ICSP Pins 2.6 External Oscillator Pins The PGECx and PGEDx pins are used for In-Circuit Many DSCs have options for at least two oscillators: a Serial Programming™ (ICSP™) and debugging pur- high-frequency primary oscillator and a low-frequency poses. It is recommended to keep the trace length secondary oscillator (refer to Section9.0 “Oscillator between the ICSP connector and the ICSP pins on the Configuration” for details). device as short as possible. If the ICSP connector is The oscillator circuit should be placed on the same expected to experience an ESD event, a series resistor side of the board as the device. Also, place the is recommended, with the value in the range of a few oscillator circuit close to the respective oscillator pins, tens of Ohms, not to exceed 100 Ohms. not exceeding one-half inch (12mm) distance Pull-up resistors, series diodes, and capacitors on the between them. The load capacitors should be placed PGECx and PGEDx pins are not recommended as they next to the oscillator itself, on the same side of the will interfere with the programmer/debugger communi- board. Use a grounded copper pour around the cations to the device. If such discrete components are oscillator circuit to isolate them from surrounding an application requirement, they should be removed circuits. The grounded copper pour should be routed from the circuit during programming and debugging. directly to the MCU ground. Do not run any signal Alternatively, refer to the AC/DC characteristics and traces or power traces inside the ground pour. Also, if timing requirements information in the respective using a two-sided board, avoid any traces on the device Flash programming specification for information other side of the board where the crystal is placed. A on capacitive loading limits and pin input voltage high suggested layout is shown in Figure2-3. (VIH) and input low (VIL) requirements. FIGURE 2-3: SUGGESTED PLACEMENT Ensure that the “Communication Channel Select” (i.e., PGECx/PGEDx pins) programmed into the device OF THE OSCILLATOR matches the physical connections for the ICSP to CIRCUIT MPLAB® ICD 2, MPLAB ICD 3, or MPLAB REAL ICE™. Main Oscillator For more information on ICD 2, ICD 3 and REAL ICE 13 connection requirements, refer to the following Guard Ring 14 documents that are available on the Microchip website. 15 • “MPLAB® ICD 2 In-Circuit Debugger User’s Guard Trace Guide” DS51331 16 • “Using MPLAB® ICD 2” (poster) DS51265 Secondary 17 • “MPLAB® ICD 2 Design Advisory” DS51566 Oscillator 18 • “Using MPLAB® ICD 3 In-Circuit Debugger” 19 (poster) DS51765 20 • “MPLAB® ICD 3 Design Advisory” DS51764 • “MPLAB® REAL ICE™ In-Circuit Emulator User’s Guide” DS51616 • “Using MPLAB® REAL ICE™” (poster) DS51749 © 2009 Microchip Technology Inc. DS70286C-page 19

dsPIC33FJXXXGPX06/X08/X10 2.7 Oscillator Value Conditions on Device Start-up If the PLL of the target device is enabled and configured for the device start-up oscillator, the maximum oscillator source frequency must be limited to 4 MHz < FIN < 8 MHz to comply with device PLL start-up conditions. This means that if the external oscillator frequency is outside this range, the application must start-up in the FRC mode first. The default PLL settings after a POR with an oscillator frequency outside this range will violate the device operating speed. Once the device powers up, the application firmware can initialize the PLL SFRs, CLKDIV and PLLDBF to a suitable value, and then perform a clock switch to the Oscillator + PLL clock source. Note that clock switching must be enabled in the device Configuration word. 2.8 Configuration of Analog and Digital Pins During ICSP Operations If MPLAB ICD 2, ICD 3 or REAL ICE is selected as a debugger, it automatically initializes all of the A/D input pins (ANx) as “digital” pins, by setting all bits in the ADPCFG and ADPCFG2 registers. The bits in the registers that correspond to the A/D pins that are initialized by MPLAB ICD 2, ICD 3, or REAL ICE, must not be cleared by the user application firmware; otherwise, communication errors will result between the debugger and the device. If your application needs to use certain A/D pins as analog input pins during the debug session, the user application must clear the corresponding bits in the ADPCFG and ADPCFG2 registers during initialization of the ADC module. When MPLAB ICD 2, ICD 3 or REAL ICE is used as a programmer, the user application firmware must correctly configure the ADPCFG and ADPCFG2 registers. Automatic initialization of these registers is only done during debugger operation. Failure to correctly configure the register(s) will result in all A/D pins being recognized as analog input pins, resulting in the port value being read as a logic ‘0’, which may affect user application functionality. 2.9 Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic-low state. Alternatively, connect a 1k to 10k resistor to VSS on unused pins and drive the output to logic low. DS70286C-page 20 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 3.0 CPU Y AGUs to support dual operand reads, which splits the data address space into two parts. The X and Y data space Note: This data sheet summarizes the features boundary is device-specific. of the dsPIC33FJXXXGPX06/X08/X10 Overhead-free circular buffers (Modulo Addressing mode) family of devices. However, it is not are supported in both X and Y address spaces. The Modulo intended to be a comprehensive reference Addressing removes the software boundary checking over- source. To complement the information in head for DSP algorithms. Furthermore, the X AGU circular this data sheet, refer to Section 2. “CPU” addressing can be used with any of the MCU class of (DS70204) in the “dsPIC33F Family Ref- instructions. The X AGU also supports Bit-Reversed erence Manual”, which is available from Addressing to greatly simplify input or output data the Microchip web site reordering for radix-2 FFT algorithms. (www.microchip.com). The upper 32 Kbytes of the data space memory map can The dsPIC33FJXXXGPX06/X08/X10 CPU module has a optionally be mapped into program space at any 16K pro- 16-bit (data) modified Harvard architecture with an gram word boundary defined by the 8-bit Program Space enhanced instruction set, including significant support for Visibility Page (PSVPAG) register. The program to data DSP. The CPU has a 24-bit instruction word with a variable space mapping feature lets any instruction access program length opcode field. The Program Counter (PC) is 23bits space as if it were data space. The data space also includes wide and addresses up to 4M x 24 bits of user program 2 Kbytes of DMA RAM, which is primarily used for DMA memory space. The actual amount of program memory data transfers, but may be used as general purpose RAM. implemented varies by device. A single-cycle instruction prefetch mechanism is used to help maintain throughput 3.2 DSP Engine Overview and provides predictable execution. All instructions execute in a single cycle, with the exception of instructions that The DSP engine features a high-speed, 17-bit by 17-bit change the program flow, the double word move (MOV.D) multiplier, a 40-bit ALU, two 40-bit saturating accumula- instruction and the table instructions. Overhead-free pro- tors and a 40-bit bidirectional barrel shifter. The barrel gram loop constructs are supported using the DO and shifter is capable of shifting a 40-bit value, up to 16 bits REPEAT instructions, both of which are interruptible at any right or left, in a single cycle. The DSP instructions operate point. seamlessly with all other instructions and have been The dsPIC33FJXXXGPX06/X08/X10 devices have sixteen, designed for optimal real-time performance. The MAC 16-bit working registers in the programmer’s model. Each of instruction and other associated instructions can concur- the working registers can serve as a data, address or rently fetch two data operands from memory while multi- address offset register. The 16th working register (W15) plying two W registers and accumulating and optionally operates as a software Stack Pointer (SP) for interrupts and saturating the result in the same cycle. This instruction calls. functionality requires that the RAM memory data space be split for these instructions and linear for all others. Data The dsPIC33FJXXXGPX06/X08/X10 instruction set has space partitioning is achieved in a transparent and flexible two classes of instructions: MCU and DSP. These two manner through dedicating certain working registers to instruction classes are seamlessly integrated into a single each address space. CPU. The instruction set includes many addressing modes and is designed for optimum C compiler efficiency. For most 3.3 Special MCU Features instructions, the dsPIC33FJXXXGPX06/X08/X10 is capa- The dsPIC33FJXXXGPX06/X08/X10 features a 17-bit by ble of executing a data (or program data) memory read, a 17-bit, single-cycle multiplier that is shared by both the working register (data) read, a data memory write and a MCU ALU and DSP engine. The multiplier can perform program (instruction) memory read per instruction cycle. As signed, unsigned and mixed-sign multiplication. Using a a result, three parameter instructions can be supported, 17-bit by 17-bit multiplier for 16-bit by 16-bit multiplication allowing A + B = C operations to be executed in a single not only allows you to perform mixed-sign multiplication, it cycle. also achieves accurate results for special operations, A block diagram of the CPU is shown in Figure3-1. The such as (-1.0) x (-1.0). programmer’s model for the The dsPIC33FJXXXGPX06/X08/X10 supports 16/16 and dsPIC33FJXXXGPX06/X08/X10 is shown in Figure3-2. 32/16 divide operations, both fractional and integer. All divide instructions are iterative operations. They must be 3.1 Data Addressing Overview executed within a REPEAT loop, resulting in a total execu- The data space can be addressed as 32K words or tion time of 19 instruction cycles. The divide operation can 64Kbytes and is split into two blocks, referred to as X and be interrupted during any of those 19cycles without loss Y data memory. Each memory block has its own indepen- of data. dent Address Generation Unit (AGU). The MCU class of A 40-bit barrel shifter is used to perform up to a 16-bit, left instructions operates solely through the X memory AGU, or right shift in a single cycle. The barrel shifter can be used which accesses the entire memory map as one linear data by both MCU and DSP instructions. space. Certain DSP instructions operate through the X and © 2009 Microchip Technology Inc. DS70286C-page 21

dsPIC33FJXXXGPX06/X08/X10 FIGURE 3-1: dsPIC33FJXXXGPX06/X08/X10 CPU CORE BLOCK DIAGRAM PSV and Table Data Access Control Block Y Data Bus Interrupt X Data Bus Controller 8 16 16 16 16 Data Latch Data Latch 23 DMA 23 PCU PCH PCL X RAM Y RAM RAM 16 Program Counter Stack Loop Address Address Control Control Latch Latch Logic Logic 23 16 16 DMA Address Latch Address Generator Units Controller Program Memory EA MUX Data Latch ROM Latch 24 16 16 a at Instruction D Decode and al Control Instruction Reg er Lit 16 Control Signals to Various Blocks DSP Engine 16 x 16 W Register Array Divide Support 16 16-bit ALU 16 To Peripheral Modules DS70286C-page 22 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 FIGURE 3-2: dsPIC33FJXXXGPX06/X08/X10 PROGRAMMER’S MODEL D15 D0 W0/WREG PUSH.S Shadow W1 DO Shadow W2 W3 Legend W4 DSP Operand W5 Registers W6 W7 Working Registers W8 W9 DSP Address Registers W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM Stack Pointer Limit Register AD39 AD31 AD15 AD0 DSP AccA Accumulators AccB PC22 PC0 0 Program Counter 7 0 TBLPAG Data Table Page Address 7 0 PSVPAG Program Space Visibility Page Address 15 0 RCOUNT REPEAT Loop Counter 15 0 DCOUNT DO Loop Counter 22 0 DOSTART DO Loop Start Address 22 DOEND DO Loop End Address 15 0 CORCON Core Configuration Register OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C STATUS Register SRH SRL © 2009 Microchip Technology Inc. DS70286C-page 23

dsPIC33FJXXXGPX06/X08/X10 3.4 CPU Control Registers CPU control registers include: • SR: CPU STATUS REGISTER • CORCON: CORE CONTROL REGISTER REGISTER 3-1: SR: CPU STATUS REGISTER R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R -0 R/W-0 OA OB SA(1) SB(1) OAB SAB DA DC bit 15 bit 8 R/W-0(2) R/W-0(3) R/W-0(3) R-0 R/W-0 R/W-0 R/W-0 R/W-0 IPL<2:0>(2) RA N OV Z C bit 7 bit 0 Legend: C = Clear only bit R = Readable bit U = Unimplemented bit, read as ‘0’ S = Set only bit W = Writable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 OA: Accumulator A Overflow Status bit 1 = Accumulator A overflowed 0 = Accumulator A has not overflowed bit 14 OB: Accumulator B Overflow Status bit 1 = Accumulator B overflowed 0 = Accumulator B has not overflowed bit 13 SA: Accumulator A Saturation ‘Sticky’ Status bit(1) 1 = Accumulator A is saturated or has been saturated at some time 0 = Accumulator A is not saturated bit 12 SB: Accumulator B Saturation ‘Sticky’ Status bit(1) 1 = Accumulator B is saturated or has been saturated at some time 0 = Accumulator B is not saturated bit 11 OAB: OA || OB Combined Accumulator Overflow Status bit 1 = Accumulators A or B have overflowed 0 = Neither Accumulators A or B have overflowed bit 10 SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit 1 = Accumulators A or B are saturated or have been saturated at some time in the past 0 = Neither Accumulator A or B are saturated Note: This bit may be read or cleared (not set). Clearing this bit will clear SA and SB. bit 9 DA: DO Loop Active bit 1 = DO loop in progress 0 = DO loop not in progress Note1: This bit may be read or cleared (not set). 2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3>=1. 3: The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>). DS70286C-page 24 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED) bit 8 DC: MCU ALU Half Carry/Borrow bit 1 = A carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized data) of the result occurred 0 = No carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized data) of the result occurred bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2) 111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) bit 4 RA: REPEAT Loop Active bit 1 = REPEAT loop in progress 0 = REPEAT loop not in progress bit 3 N: MCU ALU Negative bit 1 = Result was negative 0 = Result was non-negative (zero or positive) bit 2 OV: MCU ALU Overflow bit This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the magnitude which causes the sign bit to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 1 Z: MCU ALU Zero bit 1 = An operation which affects the Z bit has set it at some time in the past 0 = The most recent operation which affects the Z bit has cleared it (i.e., a non-zero result) bit 0 C: MCU ALU Carry/Borrow bit 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note1: This bit may be read or cleared (not set). 2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3>=1. 3: The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>). © 2009 Microchip Technology Inc. DS70286C-page 25

dsPIC33FJXXXGPX06/X08/X10 REGISTER 3-2: CORCON: CORE CONTROL REGISTER U-0 U-0 U-0 R/W-0 R/W-0 R-0 R-0 R-0 — — — US EDT(1) DL<2:0> bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0 SATA SATB SATDW ACCSAT IPL3(2) PSV RND IF bit 7 bit 0 Legend: C = Clear only bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set 0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’ bit 15-13 Unimplemented: Read as ‘0’ bit 12 US: DSP Multiply Unsigned/Signed Control bit 1 = DSP engine multiplies are unsigned 0 = DSP engine multiplies are signed bit 11 EDT: Early DO Loop Termination Control bit(1) 1 = Terminate executing DO loop at end of current loop iteration 0 = No effect bit 10-8 DL<2:0>: DO Loop Nesting Level Status bits 111 = 7 DO loops active • • • 001 = 1 DO loop active 000 = 0 DO loops active bit 7 SATA: AccA Saturation Enable bit 1 = Accumulator A saturation enabled 0 = Accumulator A saturation disabled bit 6 SATB: AccB Saturation Enable bit 1 = Accumulator B saturation enabled 0 = Accumulator B saturation disabled bit 5 SATDW: Data Space Write from DSP Engine Saturation Enable bit 1 = Data space write saturation enabled 0 = Data space write saturation disabled bit 4 ACCSAT: Accumulator Saturation Mode Select bit 1 = 9.31 saturation (super saturation) 0 = 1.31 saturation (normal saturation) bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(2) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less bit 2 PSV: Program Space Visibility in Data Space Enable bit 1 = Program space visible in data space 0 = Program space not visible in data space bit 1 RND: Rounding Mode Select bit 1 = Biased (conventional) rounding enabled 0 = Unbiased (convergent) rounding enabled bit 0 IF: Integer or Fractional Multiplier Mode Select bit 1 = Integer mode enabled for DSP multiply ops 0 = Fractional mode enabled for DSP multiply ops Note1: This bit will always read as ‘0’. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. DS70286C-page 26 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 3.5 Arithmetic Logic Unit (ALU) 3.6 DSP Engine The dsPIC33FJXXXGPX06/X08/X10 ALU is 16 bits The DSP engine consists of a high-speed, wide and is capable of addition, subtraction, bit shifts 17-bitx17-bit multiplier, a barrel shifter and a 40-bit and logic operations. Unless otherwise mentioned, adder/subtracter (with two target accumulators, round arithmetic operations are 2’s complement in nature. and saturation logic). Depending on the operation, the ALU may affect the The dsPIC33FJXXXGPX06/X08/X10 is a single-cycle, values of the Carry (C), Zero (Z), Negative (N), instruction flow architecture; therefore, concurrent Overflow (OV) and Digit Carry (DC) Status bits in the operation of the DSP engine with MCU instruction flow is SR register. The C and DC Status bits operate as Bor- not possible. However, some MCU ALU and DSP engine row and Digit Borrow bits, respectively, for subtraction resources may be used concurrently by the same operations. instruction (e.g., ED, EDAC). The ALU can perform 8-bit or 16-bit operations, The DSP engine also has the capability to perform depending on the mode of the instruction that is used. inherent accumulator-to-accumulator operations which Data for the ALU operation can come from the W require no additional data. These instructions are ADD, register array, or data memory, depending on the SUB and NEG. addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array The DSP engine has various options selected through or a data memory location. various bits in the CPU Core Control register (CORCON), as listed below: Refer to the “dsPIC30F/33F Programmer’s Reference Manual” (DS70157) for information on the SR bits 1. Fractional or integer DSP multiply (IF). affected by each instruction. 2. Signed or unsigned DSP multiply (US). 3. Conventional or convergent rounding (RND). The dsPIC33FJXXXGPX06/X08/X10 CPU 4. Automatic saturation on/off for AccA (SATA). incorporates hardware support for both multiplication and division. This includes a dedicated hardware 5. Automatic saturation on/off for AccB (SATB). multiplier and support hardware for 16-bit-divisor 6. Automatic saturation on/off for writes to data division. memory (SATDW). 7. Accumulator Saturation mode selection (ACCSAT). 3.5.1 MULTIPLIER Table3-1 provides a summary of DSP instructions. A Using the high-speed 17-bit x 17-bit multiplier of the DSP block diagram of the DSP engine is shown in engine, the ALU supports unsigned, signed or mixed-sign Figure3-3. operation in several MCU multiplication modes: 1. 16-bit x 16-bit signed TABLE 3-1: DSP INSTRUCTIONS 2. 16-bit x 16-bit unsigned SUMMARY 3. 16-bit signed x 5-bit (literal) unsigned Algebraic ACC Write Instruction 4. 16-bit unsigned x 16-bit unsigned Operation Back 5. 16-bit unsigned x 5-bit (literal) unsigned CLR A = 0 Yes 6. 16-bit unsigned x 16-bit signed ED A = (x – y)2 No 7. 8-bit unsigned x 8-bit unsigned EDAC A = A + (x – y)2 No 3.5.2 DIVIDER MAC A = A + (x * y) Yes The divide block supports 32-bit/16-bit and 16-bit/16-bit MAC A = A + x2 No signed and unsigned integer divide operations with the MOVSAC No change in A Yes following data sizes: MPY A = x * y No 1. 32-bit signed/16-bit signed divide MPY A = x 2 No 2. 32-bit unsigned/16-bit unsigned divide MPY.N A = – x * y No 3. 16-bit signed/16-bit signed divide MSC A = A – x * y Yes 4. 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends up in W0 and the remainder in W1. 16-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn) and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. © 2009 Microchip Technology Inc. DS70286C-page 27

dsPIC33FJXXXGPX06/X08/X10 FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM S a 40 40-bit Accumulator A 40 Round t 16 40-bit Accumulator B u Logic r Carry/Borrow Out a t Saturate e Adder Carry/Borrow In Negate 40 40 40 Barrel 16 Shifter 40 us B a at D Sign-Extend X s u B a 32 16 at Zero Backfill D Y 32 33 17-bit Multiplier/Scaler 16 16 To/From W Array DS70286C-page 28 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 3.6.1 MULTIPLIER 3.6.2.1 Adder/Subtracter, Overflow and Saturation The 17-bit x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a The adder/subtracter is a 40-bit adder with an optional scaler to support either 1.31 fractional (Q31) or 32-bit zero input into one side, and either true, or complement integer results. Unsigned operands are zero-extended data into the other input. In the case of addition, the into the 17th bit of the multiplier input value. Signed Carry/Borrow input is active-high and the other input is operands are sign-extended into the 17th bit of the true data (not complemented), whereas in the case of multiplier input value. The output of the 17-bit x 17-bit subtraction, the Carry/Borrow input is active-low and multiplier/scaler is a 33-bit value which is the other input is complemented. The adder/subtracter sign-extended to 40 bits. Integer data is inherently generates Overflow Status bits, SA/SB and OA/OB, represented as a signed two’s complement value, which are latched and reflected in the STATUS where the Most Significant bit (MSb) is defined as a register: sign bit. Generally speaking, the range of an N-bit two’s • Overflow from bit 39: this is a catastrophic complement integer is -2N-1 to 2N-1 - 1. For a 16-bit overflow in which the sign of the accumulator is integer, the data range is -32768 (0x8000) to 32767 destroyed. (0x7FFF) including 0. For a 32-bit integer, the data • Overflow into guard bits 32 through 39: this is a range is -2,147,483,648 (0x80000000) to recoverable overflow. This bit is set whenever all 2,147,483,647 (0x7FFF FFFF). the guard bits are not identical to each other. When the multiplier is configured for fractional The adder has an additional saturation block which multiplication, the data is represented as a two’s controls accumulator data saturation, if selected. It complement fraction, where the MSb is defined as a uses the result of the adder, the Overflow Status bits sign bit and the radix point is implied to lie just after the described above and the SAT<A:B> (CORCON<7:6>) sign bit (QX format). The range of an N-bit two’s and ACCSAT (CORCON<4>) mode control bits to complement fraction with this implied radix point is -1.0 to (1 - 21-N). For a 16-bit fraction, the Q15 data range is determine when and to what value to saturate. -1.0 (0x8000) to 0.999969482 (0x7FFF) including 0 Six STATUS register bits have been provided to and has a precision of 3.01518x10-5. In Fractional support saturation and overflow; they are: mode, the 16x 16 multiply operation generates a 1.31 1. OA: product which has a precision of 4.65661 x 10-10. AccA overflowed into guard bits The same multiplier is used to support the MCU 2. OB: multiply instructions which include integer 16-bit AccB overflowed into guard bits signed, unsigned and mixed sign multiplies. 3. SA: The MUL instruction may be directed to use byte or AccA saturated (bit 31 overflow and saturation) word sized operands. Byte operands will direct a 16-bit or result, and word operands will direct a 32-bit result to AccA overflowed into guard bits and saturated the specified register(s) in the W array. (bit 39 overflow and saturation) 4. SB: 3.6.2 DATA ACCUMULATORS AND AccB saturated (bit 31 overflow and saturation) ADDER/SUBTRACTER or The data accumulator consists of a 40-bit AccB overflowed into guard bits and saturated adder/subtracter with automatic sign extension logic. It (bit 39 overflow and saturation) can select one of two accumulators (A or B) as its 5. OAB: pre-accumulation source and post-accumulation Logical OR of OA and OB destination. For the ADD and LAC instructions, the data 6. SAB: to be accumulated or loaded can be optionally scaled Logical OR of SA and SB via the barrel shifter prior to accumulation. The OA and OB bits are modified each time data passes through the adder/subtracter. When set, they indicate that the most recent operation has overflowed into the accumulator guard bits (bits 32 through 39). The OA and OB bits can also optionally generate an arithmetic warning trap when set and the corresponding Overflow Trap Flag Enable bits (OVATE, OVBTE) in the INTCON1 register (refer to Section7.0 “Interrupt Controller”) are set. This allows the user to take immediate action, for example, to correct system gain. © 2009 Microchip Technology Inc. DS70286C-page 29

dsPIC33FJXXXGPX06/X08/X10 The SA and SB bits are modified each time data 3.6.2.2 Accumulator ‘Write Back’ passes through the adder/subtracter, but can only be The MAC class of instructions (with the exception of cleared by the user. When set, they indicate that the MPY, MPY.N, ED and EDAC) can optionally write a accumulator has overflowed its maximum range (bit 31 rounded version of the high word (bits 31 through 16) for 32-bit saturation or bit 39 for 40-bit saturation) and of the accumulator that is not targeted by the instruction will be saturated (if saturation is enabled). When into data space memory. The write is performed across saturation is not enabled, SA and SB default to bit 39 the X bus into combined X and Y address space. The overflow and, thus, indicate that a catastrophic following addressing modes are supported: overflow has occurred. If the COVTE bit in the INTCON1 register is set, SA and SB bits will generate 1. W13, Register Direct: an arithmetic warning trap when saturation is disabled. The rounded contents of the non-target accumulator are written into W13 as a The Overflow and Saturation Status bits can optionally 1.15fraction. be viewed in the STATUS Register (SR) as the logical 2. [W13]+ = 2, Register Indirect with Post-Increment: OR of OA and OB (in bit OAB) and the logical OR of SA The rounded contents of the non-target and SB (in bit SAB). This allows programmers to check accumulator are written into the address pointed one bit in the STATUS register to determine if either to by W13 as a 1.15 fraction. W13 is then accumulator has overflowed, or one bit to determine if incremented by 2 (for a word write). either accumulator has saturated. This would be useful for complex number arithmetic which typically uses 3.6.2.3 Round Logic both the accumulators. The round logic is a combinational block which The device supports three Saturation and Overflow performs a conventional (biased) or convergent modes: (unbiased) round function during an accumulator write 1. Bit 39 Overflow and Saturation: (store). The Round mode is determined by the state of When bit 39 overflow and saturation occurs, the the RND bit in the CORCON register. It generates a saturation logic loads the maximally positive 9.31 16-bit, 1.15 data value which is passed to the data (0x7FFFFFFFFF), or maximally negative 9.31 space write saturation logic. If rounding is not indicated value (0x8000000000), into the target by the instruction, a truncated 1.15 data value is stored accumulator. The SA or SB bit is set and remains and the least significant word is simply discarded. set until cleared by the user. This is referred to as Conventional rounding zero-extends bit 15 of the ‘super saturation’ and provides protection against accumulator and adds it to the ACCxH word (bits 16 erroneous data or unexpected algorithm through 31 of the accumulator). If the ACCxL word problems (e.g., gain calculations). (bits0 through 15 of the accumulator) is between 2. Bit 31 Overflow and Saturation: 0x8000 and 0xFFFF (0x8000 included), ACCxH is When bit 31 overflow and saturation occurs, the incremented. If ACCxL is between 0x0000 and 0x7FFF, saturation logic then loads the maximally ACCxH is left unchanged. A consequence of this positive 1.31 value (0x007FFFFFFF), or algorithm is that over a succession of random rounding maximally negative 1.31 value (0x0080000000), operations, the value tends to be biased slightly into the target accumulator. The SA or SB bit is positive. set and remains set until cleared by the user. Convergent (or unbiased) rounding operates in the When this Saturation mode is in effect, the same manner as conventional rounding, except when guard bits are not used (so the OA, OB or OAB ACCxL equals 0x8000. In this case, the Least bits are never set). Significant bit (bit16 of the accumulator) of ACCxH is 3. Bit 39 Catastrophic Overflow: examined. If it is ‘1’, ACCxH is incremented. If it is ‘0’, The bit 39 Overflow Status bit from the adder is ACCxH is not modified. Assuming that bit 16 is used to set the SA or SB bit, which remains set effectively random in nature, this scheme removes any until cleared by the user. No saturation operation rounding bias that may accumulate. is performed and the accumulator is allowed to overflow (destroying its sign). If the COVTE bit in The SAC and SAC.R instructions store either a the INTCON1 register is set, a catastrophic truncated (SAC), or rounded (SAC.R) version of the overflow can initiate a trap exception. contents of the target accumulator to data memory via the X bus, subject to data saturation (see Section3.6.2.4 “Data Space Write Saturation”). For the MAC class of instructions, the accumulator write-back operation will function in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. DS70286C-page 30 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 3.6.2.4 Data Space Write Saturation 3.6.3 BARREL SHIFTER In addition to adder/subtracter saturation, writes to data The barrel shifter is capable of performing up to 16-bit space can also be saturated but without affecting the arithmetic or logic right shifts, or up to 16-bit left shifts contents of the source accumulator. The data space in a single cycle. The source can be either of the two write saturation logic block accepts a 16-bit, 1.15 DSP accumulators or the X bus (to support multi-bit fractional value from the round logic block as its input, shifts of register or memory data). together with overflow status from the original source The shifter requires a signed binary value to determine (accumulator) and the 16-bit round adder. These inputs both the magnitude (number of bits) and direction of the are combined and used to select the appropriate 1.15 shift operation. A positive value shifts the operand right. fractional value as output to write to data space A negative value shifts the operand left. A value of ‘0’ memory. does not modify the operand. If the SATDW bit in the CORCON register is set, data The barrel shifter is 40 bits wide, thereby obtaining a (after rounding or truncation) is tested for overflow and 40-bit result for DSP shift operations and a 16-bit result adjusted accordingly, For input data greater than for MCU shift operations. Data from the X bus is 0x007FFF, data written to memory is forced to the presented to the barrel shifter between bit positions 16 maximum positive 1.15 value, 0x7FFF. For input data to 31 for right shifts, and between bit positions 0 to 16 less than 0xFF8000, data written to memory is forced for left shifts. to the maximum negative 1.15 value, 0x8000. The Most Significant bit of the source (bit 39) is used to determine the sign of the operand being tested. If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. © 2009 Microchip Technology Inc. DS70286C-page 31

dsPIC33FJXXXGPX06/X08/X10 NOTES: DS70286C-page 32 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 4.0 MEMORY ORGANIZATION 4.1 Program Address Space The program address memory space of the Note: This data sheet summarizes the features dsPIC33FJXXXGPX06/X08/X10 devices is 4M of the dsPIC33FJXXXGPX06/X08/X10 instructions. The space is addressable by a 24-bit family of devices. However, it is not value derived from either the 23-bit Program Counter intended to be a comprehensive reference (PC) during program execution, or from table operation source. To complement the information in or data space remapping as described in Section4.6 this data sheet, refer to Section 3. “Data “Interfacing Program and Data Memory Spaces”. Memory” (DS70202) and Section 4. “Program Memory” (DS70203) in the User access to the program memory space is restricted “dsPIC33F Family Reference Manual”, to the lower half of the address range (0x000000 to which is available from the Microchip web 0x7FFFFF). The exception is the use of TBLRD/TBLWT site (www.microchip.com). operations, which use TBLPAG<7> to permit access to the Configuration bits and Device ID sections of the The dsPIC33FJXXXGPX06/X08/X10 architecture configuration memory space. Memory usage for the features separate program and data memory spaces dsPIC33FJXXXGPX06/X08/X10 of devices is shown in and buses. This architecture also allows the direct Figure4-1. access of program memory from the data space during code execution. FIGURE 4-1: PROGRAM MEMORY FOR dsPIC33FJXXXGPX06/X08/X10 DEVICES dsPIC33FJ64GPXXX dsPIC33FJ128GPXXX dsPIC33FJ256GPXXX GOTO Instruction GOTO Instruction GOTO Instruction 0x000000 Reset Address Reset Address Reset Address 0x000002 0x000004 Interrupt Vector Table Interrupt Vector Table Interrupt Vector Table 0x0000FE Reserved Reserved Reserved 0x000100 0x000104 Alternate Vector Table Alternate Vector Table Alternate Vector Table 0x0001FE 0x000200 User Program Flash Memory e Spac (22K instructions) FUlsaesrh PMroegmraomry FUlsaesrh PMroegmraomry 00xx0000AACBF00E y (44K instructions) (88K instructions) or m e 0x0157FE M 0x015800 er Us Unimplemented (Read ‘0’s) Unimplemented (Read ‘0’s) 0x02ABFE 0x02AC00 Unimplemented (Read ‘0’s) 0x7FFFFE 0x800000 Reserved Reserved Reserved e c a p S y 0xF7FFFE or Device Configuration Device Configuration Device Configuration 0xF80000 m e Registers Registers Registers 0xF80017 M 0xF80010 n o ati ur Reserved Reserved Reserved g nfi o C 0xFEFFFE 0xFF0000 DEVID (2) DEVID (2) DEVID (2) 0xFFFFFE Note: Memory areas are not shown to scale. © 2009 Microchip Technology Inc. DS70286C-page 33

dsPIC33FJXXXGPX06/X08/X10 4.1.1 PROGRAM MEMORY 4.1.2 INTERRUPT AND TRAP VECTORS ORGANIZATION All dsPIC33FJXXXGPX06/X08/X10 devices reserve The program memory space is organized in the addresses between 0x00000 and 0x000200 for word-addressable blocks. Although it is treated as hard-coded program execution vectors. A hardware 24bits wide, it is more appropriate to think of each Reset vector is provided to redirect code execution address of the program memory as a lower and upper from the default value of the PC on device Reset to the word, with the upper byte of the upper word being actual start of code. A GOTO instruction is programmed unimplemented. The lower word always has an even by the user at 0x000000, with the actual address for the address, while the upper word has an odd address start of code at 0x000002. (Figure4-2). dsPIC33FJXXXGPX06/X08/X10 devices also have Program memory addresses are always word-aligned two interrupt vector tables, located from 0x000004 to on the lower word, and addresses are incremented or 0x0000FF and 0x000100 to 0x0001FF. These vector decremented by two during code execution. This tables allow each of the many device interrupt sources arrangement also provides compatibility with data to be handled by separate Interrupt Service Routines memory space addressing and makes it possible to (ISRs). A more detailed discussion of the interrupt access data in the program memory space. vector tables is provided in Section7.1 “Interrupt Vector Table”. FIGURE 4-2: PROGRAM MEMORY ORGANIZATION msw most significant word least significant word PC Address Address (lsw Address) 23 16 8 0 0x000001 00000000 0x000000 0x000003 00000000 0x000002 0x000005 00000000 0x000004 0x000007 00000000 0x000006 Program Memory Instruction Width ‘Phantom’ Byte (read as ‘0’) DS70286C-page 34 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 4.2 Data Address Space All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so The dsPIC33FJXXXGPX06/X08/X10 CPU has a care must be taken when mixing byte and word separate 16-bit wide data memory space. The data operations, or translating from 8-bit MCU code. If a space is accessed using separate Address Generation misaligned read or write is attempted, an address error Units (AGUs) for read and write operations. Data trap is generated. If the error occurred on a read, the memory maps of devices with different RAM sizes are instruction underway is completed; if it occurred on a shown in Figure4-3 through Figure4-5. write, the instruction will be executed but the write does All Effective Addresses (EAs) in the data memory space not occur. In either case, a trap is then executed, are 16 bits wide and point to bytes within the data space. allowing the system and/or user to examine the This arrangement gives a data space address range of machine state prior to execution of the address Fault. 64Kbytes or 32Kwords. The lower half of the data All byte loads into any W register are loaded into the memory space (that is, when EA<15> = 0) is used for Least Significant Byte. The Most Significant Byte is not implemented memory addresses, while the upper half modified. (EA<15> = 1) is reserved for the Program Space A sign-extend instruction (SE) is provided to allow Visibility area (see Section4.6.3 “Reading Data from users to translate 8-bit signed data to 16-bit signed Program Memory Using Program Space Visibility”). values. Alternatively, for 16-bit unsigned data, users dsPIC33FJXXXGPX06/X08/X10 devices implement a can clear the MSb of any W register by executing a total of up to 30Kbytes of data memory. Should an EA zero-extend (ZE) instruction on the appropriate point to a location outside of this area, an all-zero word address. or byte will be returned. 4.2.3 SFR SPACE 4.2.1 DATA SPACE WIDTH The first 2Kbytes of the Near Data Space, from 0x0000 The data memory space is organized in byte to 0x07FF, is primarily occupied by Special Function addressable, 16-bit wide blocks. Data is aligned in data Registers (SFRs). These are used by the memory and registers as 16-bit words, but all data dsPIC33FJXXXGPX06/X08/X10 core and peripheral space EAs resolve to bytes. The Least Significant modules for controlling the operation of the device. Bytes (LSBs) of each word have even addresses, while SFRs are distributed among the modules that they the Most Significant Bytes (MSBs) have odd control, and are generally grouped together by module. addresses. Much of the SFR space contains unused addresses; 4.2.2 DATA MEMORY ORGANIZATION these are read as ‘0’. A complete listing of implemented AND ALIGNMENT SFRs, including their addresses, is shown in Table4-1 through Table4-34. To maintain backward compatibility with PIC® MCU devices and improve data space memory usage Note: The actual set of peripheral features and efficiency, the dsPIC33FJXXXGPX06/X08/X10 interrupts varies by the device. Please instruction set supports both word and byte operations. refer to the corresponding device tables As a consequence of byte accessibility, all effective and pinout diagrams for device-specific address calculations are internally scaled to step information. through word-aligned memory. For example, the core 4.2.4 NEAR DATA SPACE recognizes that Post-Modified Register Indirect Addressing mode [Ws++] will result in a value of Ws +1 The 8-Kbyte area between 0x0000 and 0x1FFF is for byte operations and Ws + 2 for word operations. referred to as the Near Data Space. Locations in this Data byte reads will read the complete word that space are directly addressable via a 13-bit absolute contains the byte, using the LSb of any EA to determine address field within all memory direct instructions. which byte to select. The selected byte is placed onto Additionally, the whole data space is addressable using the LSb of the data path. That is, data memory and MOV instructions, which support Memory Direct registers are organized as two parallel byte-wide Addressing mode with a 16-bit address field, or by entities with shared (word) address decode but using Indirect Addressing mode using a working separate write lines. Data byte writes only write to the register as an Address Pointer. corresponding side of the array or register which matches the byte address. © 2009 Microchip Technology Inc. DS70286C-page 35

dsPIC33FJXXXGPX06/X08/X10 FIGURE 4-3: DATA MEMORY MAP FOR dsPIC33FJXXXGPX06/X08/X10 DEVICES WITH 8 KBS RAM MSB LSB Address 16 bits Address MSB LSB 0x0001 0x0000 2 Kbyte SFR Space SFR Space 0x07FF 0x07FE 0x0801 0x0800 8 Kbyte X Data RAM (X) Near Data Space 8 Kbyte 0x17FF 0x17FE SRAM Space 0x1801 0x1800 Y Data RAM (Y) 0x1FFF 0x1FFE 0x2001 0x2000 DMA RAM 0x27FF 0x27FE 0x2801 0x2800 0x8001 0x8000 X Data Optionally Unimplemented (X) Mapped into Program Memory 0xFFFF 0xFFFE DS70286C-page 36 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 FIGURE 4-4: DATA MEMORY MAP FOR dsPIC33FJXXXGPX06/X08/X10 DEVICES WITH 16 KB RAM LSB MSB Address Address 16 bits MSB LSB 0x0001 0x0000 2 Kbyte SFR Space SFR Space 0x07FF 0x07FE 8 Kbyte 0x0801 0x0800 Near Data Space X Data RAM (X) 0x1FFF 0x1FFE 16 Kbyte 0x27FF 0x27FE SRAM Space 0x2801 0x2800 Y Data RAM (Y) 0x3FFF 0x3FFE 0x4001 0x4000 DMA RAM 0x47FF 0x47FE 0x4801 0x4800 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF 0xFFFE © 2009 Microchip Technology Inc. DS70286C-page 37

dsPIC33FJXXXGPX06/X08/X10 FIGURE 4-5: DATA MEMORY MAP FOR dsPIC33FJXXXGPX06/X08/X10 DEVICES WITH 30 KB RAM MSB LSB Address 16 bits Address MSB LSB 0x0001 0x0000 2 Kbyte SFR Space SFR Space 0x07FF 0x07FE 8 Kbyte 0x0801 0x0800 Near Data Space X Data RAM (X) 30 Kbyte SRAM Space 0x47FF 0x47FE 0x4801 0x4800 Y Data RAM (Y) 0x77FF 0x77FE 0x7800 0x7800 DMA RAM 0x7FFF 0x7FFE 0x8001 0x8000 Optionally X Data Mapped Unimplemented (X) into Program Memory 0xFFFF 0xFFFE DS70286C-page 38 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 4.2.5 X AND Y DATA SPACES 4.2.6 DMA RAM The core has two data spaces, X and Y. These data Every dsPIC33FJXXXGPX06/X08/X10 device contains spaces can beconsidered either separate (for some 2 Kbytes of dual ported DMA RAM located at the end of DSP instructions), or as one unified linear address Y data space. Memory locations is part of Y data RAM range (for MCU instructions). The data spaces are and is in the DMA RAM space are accessible accessed using two Address Generation Units (AGUs) simultaneously by the CPU and the DMA controller and separate data paths. This feature allows certain module. DMA RAM is utilized by the DMA controller to instructions to concurrently fetch two words from RAM, store data to be transferred to various peripherals using thereby enabling efficient execution of DSP algorithms DMA, as well as data transferred from various such as Finite Impulse Response (FIR) filtering and peripherals using DMA. The DMA RAM can be Fast Fourier Transform (FFT). accessed by the DMA controller without having to steal cycles from the CPU. The X data space is used by all instructions and supports all addressing modes. There are separate When the CPU and the DMA controller attempt to read and write data buses for X data space. The X read concurrently write to the same DMA RAM location, the data bus is the read data path for all instructions that hardware ensures that the CPU is given precedence in view data space as combined X and Y address space. accessing the DMA RAM location. Therefore, the DMA It is also the X data prefetch path for the dual operand RAM provides a reliable means of transferring DMA DSP instructions (MAC class). data without ever having to stall the CPU. The Y data space is used in concert with the X data Note: DMA RAM can be used for general space by the MAC class of instructions (CLR, ED, purpose data storage if the DMA function EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to provide is not required in an application. two concurrent data read paths. Both the X and Y data spaces support Modulo Addressing mode for all instructions, subject to addressing mode restrictions. Bit-Reversed Addressing mode is only supported for writes to X data space. All data memory writes, including in DSP instructions, view data space as combined X and Y address space. The boundary between the X and Y data spaces is device-dependent and is not user-programmable. All effective addresses are 16 bits wide and point to bytes within the data space. Therefore, the data space address range is 64 Kbytes, or 32K words, though the implemented memory locations vary by device. © 2009 Microchip Technology Inc. DS70286C-page 39

D TABLE 4-1: CPU CORE REGISTERS MAP d S 702 SFR Name SFR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All s 8 Addr Resets P 6 C -p WREG0 0000 Working Register 0 0000 I ag WREG1 0002 Working Register 1 0000 C e 4 WREG2 0004 Working Register 2 0000 3 0 WREG3 0006 Working Register 3 0000 3 WREG4 0008 Working Register 4 0000 F WREG5 000A Working Register 5 0000 WREG6 000C Working Register 6 0000 J WREG7 000E Working Register 7 0000 X WREG8 0010 Working Register 8 0000 X WREG9 0012 Working Register 9 0000 WREG10 0014 Working Register 10 0000 X WREG11 0016 Working Register 11 0000 G WREG12 0018 Working Register 12 0000 WREG13 001A Working Register 13 0000 P WREG14 001C Working Register 14 0000 X WREG15 001E Working Register 15 0800 0 SPLIM 0020 Stack Pointer Limit Register xxxx ACCAL 0022 Accumulator A Low Word Register 0000 6 ACCAH 0024 Accumulator A High Word Register 0000 / X ACCAU 0026 Accumulator A Upper Word Register 0000 ACCBL 0028 Accumulator B Low Word Register 0000 0 ACCBH 002A Accumulator B High Word Register 0000 8 ACCBU 002C Accumulator B Upper Word Register 0000 / PCL 002E Program Counter Low Word Register 0000 X PCH 0030 — — — — — — — — Program Counter High Byte Register 0000 1 TBLPAG 0032 — — — — — — — — Table Page Address Pointer Register 0000 0 PSVPAG 0034 — — — — — — — — Program Memory Visibility Page Address Pointer Register 0000 RCOUNT 0036 Repeat Loop Counter Register xxxx DCOUNT 0038 DCOUNT<15:0> xxxx DOSTARTL 003A DOSTARTL<15:1> 0 xxxx © 2 DOSTARTH 003C — — — — — — — — — — DOSTARTH<5:0> 00xx 0 0 DOENDL 003E DOENDL<15:1> 0 xxxx 9 M DOENDH 0040 — — — — — — — — — — DOENDH 00xx icro SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C 0000 ch CORCON 0044 — — — US EDT DL<2:0> SATA SATB SATDW ACCSAT IPL3 PSV RND IF 0020 ip MODCON 0046 XMODEN YMODEN — — BWM<3:0> YWM<3:0> XWM<3:0> 0000 T e XMODSRT 0048 XS<15:1> 0 xxxx c hn XMODEND 004A XE<15:1> 1 xxxx o lo YMODSRT 004C YS<15:1> 0 xxxx g y YMODEND 004E YE<15:1> 1 xxxx In Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. c .

© TABLE 4-1: CPU CORE REGISTERS MAP (CONTINUED) 2 0 SFR All 0 SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 Addr Resets M ic XBREV 0050 BREN XB<14:0> xxxx roc DISICNT 0052 — — Disable Interrupts Counter Register xxxx h ip BSRAM 0750 — — — — — — — — — — — — — IW_BSR IR_BSR RL_BSR 0000 Te SSRAM 0752 — — — — — — — — — — — — — IW_SSR IR_SSR RL_SSR 0000 c h Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. n o lo g y In c . d s P I C 3 3 F J X X X G P X 0 6 / X D 0 S 70 8 2 86 / C X -p a 1 g e 4 0 1

D TABLE 4-2: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJXXXGPX10 DEVICES d S 70286 NSaFmRe ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts sP C -p CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 I a C ge CNEN2 0062 — — — — — — — — CN23IE CN22IE CN21IE CN20IE CN19IE CN18IE CN17IE CN16IE 0000 42 CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 3 CNPU2 006A — — — — — — — — CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE 0000 3 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. F J X TABLE 4-3: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJXXXGPX08 DEVICES X NSaFmRe ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts X G CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 CNEN2 0062 — — — — — — — — — — CN21IE CN20IE CN19IE CN18IE CN17IE CN16IE 0000 P CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 X CNPU2 006A — — — — — — — — — — CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE 0000 0 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 6 / X TABLE 4-4: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJXXXGPX06 DEVICES 0 SFR SFR All Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets 8 / CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 X CNEN2 0062 — — — — — — — — — — CN21IE CN20IE — CN18IE CN17IE CN16IE 0000 1 CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 0 CNPU2 006A — — — — — — — — — — CN21PUE CN20PUE — CN18PUE CN17PUE CN16PUE 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. © 2 0 0 9 M ic ro c h ip T e c h n o lo g y In c .

© TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP 2 0 0 SFR SFR All 9 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 M Name Addr Resets ic ro INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL — 0000 c h INTCON2 0082 ALTIVT DISI — — — — — — — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000 ip T IFS0 0084 — DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF 0000 e ch IFS1 0086 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF IC8IF IC7IF AD2IF INT1IF CNIF — MI2C1IF SI2C1IF 0000 n olo IFS2 0088 T6IF DMA4IF — OC8IF OC7IF OC6IF OC5IF IC6IF IC5IF IC4IF IC3IF DMA3IF C1IF C1RXIF SPI2IF SPI2EIF 0000 g y IFS3 008A — — DMA5IF DCIIF DCIEIF — — C2IF C2RXIF INT4IF INT3IF T9IF T8IF MI2C2IF SI2C2IF T7IF 0000 Inc IFS4 008C — — — — — — — — C2TXIF C1TXIF DMA7IF DMA6IF — U2EIF U1EIF — 0000 . IEC0 0094 — DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE 0000 IEC1 0096 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE IC8IE IC7IE AD2IE INT1IE CNIE — MI2C1IE SI2C1IE 0000 IEC2 0098 T6IE DMA4IE — OC8IE OC7IE OC6IE OC5IE IC6IE IC5IE IC4IE IC3IE DMA3IE C1IE C1RXIE SPI2IE SPI2EIE 0000 d IEC3 009A — — DMA5IE DCIIE DCIEIE — — C2IE C2RXIE INT4IE INT3IE T9IE T8IE MI2C2IE SI2C2IE T7IE 0000 s IEC4 009C — — — — — — — — C2TXIE C1TXIE DMA7IE DMA6IE — U2EIE U1EIE — 0000 P IPC0 00A4 — T1IP<2:0> — OC1IP<2:0> — IC1IP<2:0> — INT0IP<2:0> 4444 I IPC1 00A6 — T2IP<2:0> — OC2IP<2:0> — IC2IP<2:0> — DMA0IP<2:0> 4444 C IPC2 00A8 — U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0> 4444 3 IPC3 00AA — — — — — DMA1IP<2:0> — AD1IP<2:0> — U1TXIP<2:0> 0444 3 IPC4 00AC — CNIP<2:0> — — — — — MI2C1IP<2:0> — SI2C1IP<2:0> 4044 F IPC5 00AE — IC8IP<2:0> — IC7IP<2:0> — AD2IP<2:0> — INT1IP<2:0> 4444 J IPC6 00B0 — T4IP<2:0> — OC4IP<2:0> — OC3IP<2:0> — DMA2IP<2:0> 4444 X IPC7 00B2 — U2TXIP<2:0> — U2RXIP<2:0> — INT2IP<2:0> — T5IP<2:0> 4444 X IPC8 00B4 — C1IP<2:0> — C1RXIP<2:0> — SPI2IP<2:0> — SPI2EIP<2:0> 4444 IPC9 00B6 — IC5IP<2:0> — IC4IP<2:0> — IC3IP<2:0> — DMA3IP<2:0> 4444 X IPC10 00B8 — OC7IP<2:0> — OC6IP<2:0> — OC5IP<2:0> — IC6IP<2:0> 4444 G IPC11 00BA — T6IP<2:0> — DMA4IP<2:0> — — — — — OC8IP<2:0> 4404 P IPC12 00BC — T8IP<2:0> — MI2C2IP<2:0> — SI2C2IP<2:0> — T7IP<2:0> 4444 X IPC13 00BE — C2RXIP<2:0> — INT4IP<2:0> — INT3IP<2:0> — T9IP<2:0> 4444 IPC14 00C0 — DCIEIP<2:0> — — — — — — — — — C2IP<2:0> 4004 0 IPC15 00C2 — — — — — — — — — DMA5IP<2:0> — DCIIP<2:0> 0044 6 IPC16 00C4 — — — — — U2EIP<2:0> — U1EIP<2:0> — — — — 0440 / X IPC17 00C6 — C2TXIP<2:0> — C1TXIP<2:0> — DMA7IP<2:0> — DMA6IP<2:0> 4444 D 0 S INTTREG 00E0 — — — — ILR<3:0> — VECNUM<6:0> 0000 702 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 8 86 / C X -p a 1 g e 4 0 3

D TABLE 4-6: TIMER REGISTER MAP d S 70 SFR SFR All s 28 Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets P 6 C -p TMR1 0100 Timer1 Register xxxx I a C g PR1 0102 Period Register 1 FFFF e 4 T1CON 0104 TON — TSIDL — — — — — — TGATE TCKPS<1:0> — TSYNC TCS — 0000 3 4 TMR2 0106 Timer2 Register xxxx 3 TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only) xxxx F TMR3 010A Timer3 Register xxxx J PR2 010C Period Register 2 FFFF X PR3 010E Period Register 3 FFFF X T2CON 0110 TON — TSIDL — — — — — — TGATE TCKPS<1:0> T32 — TCS — 0000 X T3CON 0112 TON — TSIDL — — — — — — TGATE TCKPS<1:0> — — TCS — 0000 TMR4 0114 Timer4 Register xxxx G TMR5HLD 0116 Timer5 Holding Register (for 32-bit operations only) xxxx P TMR5 0118 Timer5 Register xxxx X PR4 011A Period Register 4 FFFF PR5 011C Period Register 5 FFFF 0 T4CON 011E TON — TSIDL — — — — — — TGATE TCKPS<1:0> T32 — TCS — 0000 6 T5CON 0120 TON — TSIDL — — — — — — TGATE TCKPS<1:0> — — TCS — 0000 / X TMR6 0122 Timer6 Register xxxx 0 TMR7HLD 0124 Timer7 Holding Register (for 32-bit operations only) xxxx 8 TMR7 0126 Timer7 Register xxxx / PR6 0128 Period Register 6 FFFF X PR7 012A Period Register 7 FFFF 1 T6CON 012C TON — TSIDL — — — — — — TGATE TCKPS<1:0> T32 — TCS — 0000 0 T7CON 012E TON — TSIDL — — — — — — TGATE TCKPS<1:0> — — TCS — 0000 TMR8 0130 Timer8 Register xxxx TMR9HLD 0132 Timer9 Holding Register (for 32-bit operations only) xxxx © 2 TMR9 0134 Timer9 Register xxxx 0 0 PR8 0136 Period Register 8 FFFF 9 M PR9 0138 Period Register 9 FFFF ic ro T8CON 013A TON — TSIDL — — — — — — TGATE TCKPS<1:0> T32 — TCS — 0000 c h T9CON 013C TON — TSIDL — — — — — — TGATE TCKPS<1:0> — — TCS — 0000 ip T Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. e c h n o lo g y In c .

© TABLE 4-7: INPUT CAPTURE REGISTER MAP 2 0 0 SFR All 9 SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 M Addr Resets ic ro IC1BUF 0140 Input 1 Capture Register xxxx c h IC1CON 0142 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 ip T IC2BUF 0144 Input 2 Capture Register xxxx e ch IC2CON 0146 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 n olo IC3BUF 0148 Input 3 Capture Register xxxx g y IC3CON 014A — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 Inc IC4BUF 014C Input 4 Capture Register xxxx . IC4CON 014E — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 IC5BUF 0150 Input 5 Capture Register xxxx IC5CON 0152 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 d IC6BUF 0154 Input 6 Capture Register xxxx s IC6CON 0156 — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 P IC7BUF 0158 Input 7 Capture Register xxxx I IC7CON 015A — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 C IC8BUF 015C Input 8 Capture Register xxxx 3 IC8CON 015E — — ICSIDL — — — — — ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 3 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. F J X X X G P X 0 6 / X D 0 S 70 8 2 86 / C X -p a 1 g e 4 0 5

D d S TABLE 4-8: OUTPUT COMPARE REGISTER MAP 70 s 2 SFR All 86 SFR Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets P C -pa OC1RS 0180 Output Compare 1 Secondary Register xxxx IC g e OC1R 0182 Output Compare 1 Register xxxx 4 3 6 OC1CON 0184 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 3 OC2RS 0186 Output Compare 2 Secondary Register xxxx F OC2R 0188 Output Compare 2 Register xxxx OC2CON 018A — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 J OC3RS 018C Output Compare 3 Secondary Register xxxx X OC3R 018E Output Compare 3 Register xxxx X OC3CON 0190 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 X OC4RS 0192 Output Compare 4 Secondary Register xxxx G OC4R 0194 Output Compare 4 Register xxxx OC4CON 0196 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 P OC5RS 0198 Output Compare 5 Secondary Register xxxx X OC5R 019A Output Compare 5 Register xxxx 0 OC5CON 019C — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 6 OC6RS 019E Output Compare 6 Secondary Register xxxx / OC6R 01A0 Output Compare 6 Register xxxx X OC6CON 01A2 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 0 OC7RS 01A4 Output Compare 7 Secondary Register xxxx 8 OC7R 01A6 Output Compare 7 Register xxxx / X OC7CON 01A8 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 OC8RS 01AA Output Compare 8 Secondary Register xxxx 1 OC8R 01AC Output Compare 8 Register xxxx 0 OC8CON 01AE — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM<2:0> 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. © 2 0 0 9 M ic ro c h ip T e c h n o lo g y In c .

TABLE 4-9: I2C1 REGISTER MAP © 2 009 SFR Name ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts M ic I2C1RCV 0200 — — — — — — — — Receive Register 0000 roc I2C1TRN 0202 — — — — — — — — Transmit Register 00FF h ip I2C1BRG 0204 — — — — — — — Baud Rate Generator Register 0000 T e I2C1CON 0206 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000 c h n I2C1STAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000 o lo I2C1ADD 020A — — — — — — Address Register 0000 g y In I2C1MSK 020C — — — — — — Address Mask Register 0000 c . Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-10: I2C2 REGISTER MAP d SFR All SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Addr Resets s I2C2RCV 0210 — — — — — — — — Receive Register 0000 P I2C2TRN 0212 — — — — — — — — Transmit Register 00FF I C I2C2BRG 0214 — — — — — — — Baud Rate Generator Register 0000 I2C2CON 0216 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000 3 I2C2STAT 0218 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000 3 I2C2ADD 021A — — — — — — Address Register 0000 F I2C2MSK 021C — — — — — — Address Mask Register 0000 J Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. X X X G P X 0 6 / X D 0 S 70 8 2 86 / C X -p a 1 g e 4 0 7

D d S TABLE 4-11: UART1 REGISTER MAP 70 s 2 SFR All 86 SFR Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets P C -p U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL 0000 I a C ge U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110 48 U1TXREG 0224 — — — — — — — UART Transmit Register xxxx 3 U1RXREG 0226 — — — — — — — UART Receive Register 0000 3 U1BRG 0228 Baud Rate Generator Prescaler 0000 F Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. J X TABLE 4-12: UART2 REGISTER MAP X SFR SFR All Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X Name Addr Resets G U2MODE 0230 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL 0000 U2STA 0232 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110 P U2TXREG 0234 — — — — — — — UART Transmit Register xxxx X U2RXREG 0236 — — — — — — — UART Receive Register 0000 0 U2BRG 0238 Baud Rate Generator Prescaler 0000 6 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. / X TABLE 4-13: SPI1 REGISTER MAP 0 SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All 8 Name Addr Resets / SPI1STAT 0240 SPIEN — SPISIDL — — — — — — SPIROV — — — — SPITBF SPIRBF 0000 X SPI1CON1 0242 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE<2:0> PPRE<1:0> 0000 1 SPI1CON2 0244 FRMEN SPIFSD FRMPOL — — — — — — — — — — — FRMDLY — 0000 0 SPI1BUF 0248 SPI1 Transmit and Receive Buffer Register 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. © 2 TABLE 4-14: SPI2 REGISTER MAP 0 09 M SFR Name ASdFdRr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts ic ro SPI2STAT 0260 SPIEN — SPISIDL — — — — — — SPIROV — — — — SPITBF SPIRBF 0000 c hip SPI2CON1 0262 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE<2:0> PPRE<1:0> 0000 T SPI2CON2 0264 FRMEN SPIFSD FRMPOL — — — — — — — — — — — FRMDLY — 0000 e c h SPI2BUF 0268 SPI2 Transmit and Receive Buffer Register 0000 n olo Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. g y In c .

TABLE 4-15: ADC1 REGISTER MAP © 2 0 All 0 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 Resets M ic ADC1BUF0 0300 ADC Data Buffer 0 xxxx ro c AD1CON1 0320 ADON — ADSIDL ADDMABM — AD12B FORM<1:0> SSRC<2:0> — SIMSAM ASAM SAMP DONE 0000 h ip T AD1CON2 0322 VCFG<2:0> — — CSCNA CHPS<1:0> BUFS — SMPI<3:0> BUFM ALTS 0000 ec AD1CON3 0324 ADRC — — SAMC<4:0> ADCS<7:0> 0000 h no AD1CHS123 0326 — — — — — CH123NB<1:0> CH123SB — — — — — CH123NA<1:0> CH123SA 0000 lo g AD1CHS0 0328 CH0NB — — CH0SB<4:0> CH0NA — — CH0SA<4:0> 0000 y In AD1PCFGH(1) 032A PCFG31 PCFG30 PCFG29 PCFG28 PCFG27 PCFG26 PCFG25 PCFG24 PCFG23 PCFG22 PCFG21 PCFG20 PCFG19 PCFG18 PCFG17 PCFG16 0000 c . AD1PCFGL 032C PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 AD1CSSH(1) 032E CSS31 CSS30 CSS29 CSS28 CSS27 CSS26 CSS25 CSS24 CSS23 CSS22 CSS21 CSS20 CSS19 CSS18 CSS17 CSS16 0000 AD1CSSL 0330 CSS15 CSS14 CSS13 CSS12 CSS11 CSS10 CSS9 CSS8 CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 0000 d AD1CON4 0332 — — — — — — — — — — — — — DMABL<2:0> 0000 s Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: Not all ANx inputs are available on all devices. See the device pin diagrams for available ANx inputs. P I TABLE 4-16: ADC2 REGISTER MAP C 3 All File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets 3 ADC2BUF0 0340 ADC Data Buffer 0 xxxx F AD2CON1 0360 ADON — ADSIDL ADDMABM — AD12B FORM<1:0> SSRC<2:0> — SIMSAM ASAM SAMP DONE 0000 J AD2CON2 0362 VCFG<2:0> — — CSCNA CHPS<1:0> BUFS — SMPI<3:0> BUFM ALTS 0000 X AD2CON3 0364 ADRC — — SAMC<4:0> ADCS<7:0> 0000 X AD2CHS123 0366 — — — — — CH123NB<1:0> CH123SB — — — — — CH123NA<1:0> CH123SA 0000 X AD2CHS0 0368 CH0NB — — — CH0SB<3:0> CH0NA — — — CH0SA<3:0> 0000 G Reserved 036A — — — — — — — — — — — — — — — — 0000 AD2PCFGL 036C PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 P Reserved 036E — — — — — — — — — — — — — — — — 0000 X AD2CSSL 0370 CSS15 CSS14 CSS13 CSS12 CSS11 CSS10 CSS9 CSS8 CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 0000 0 AD2CON4 0372 — — — — — — — — — — — — — DMABL<2:0> 0000 6 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. / X D 0 S 70 8 2 86 / C X -p a 1 g e 4 0 9

D TABLE 4-17: DMA REGISTER MAP d S 7028 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts sP 6 C-p DMA0CON 0380 CHEN SIZE DIR HALF NULLW — — — — — AMODE<1:0> — — MODE<1:0> 0000 I ag DMA0REQ 0382 FORCE — — — — — — — — IRQSEL<6:0> 0000 C e 5 DMA0STA 0384 STA<15:0> 0000 3 0 DMA0STB 0386 STB<15:0> 0000 3 DMA0PAD 0388 PAD<15:0> 0000 F DMA0CNT 038A — — — — — — CNT<9:0> 0000 J DMA1CON 038C CHEN SIZE DIR HALF NULLW — — — — — AMODE<1:0> — — MODE<1:0> 0000 X DMA1REQ 038E FORCE — — — — — — — — IRQSEL<6:0> 0000 X DMA1STA 0390 STA<15:0> 0000 DMA1STB 0392 STB<15:0> 0000 X DMA1PAD 0394 PAD<15:0> 0000 G DMA1CNT 0396 — — — — — — CNT<9:0> 0000 P DMA2CON 0398 CHEN SIZE DIR HALF NULLW — — — — — AMODE<1:0> — — MODE<1:0> 0000 X DMA2REQ 039A FORCE — — — — — — — — IRQSEL<6:0> 0000 DMA2STA 039C STA<15:0> 0000 0 DMA2STB 039E STB<15:0> 0000 6 DMA2PAD 03A0 PAD<15:0> 0000 / X DMA2CNT 03A2 — — — — — — CNT<9:0> 0000 0 DMA3CON 03A4 CHEN SIZE DIR HALF NULLW — — — — — AMODE<1:0> — — MODE<1:0> 0000 8 DMA3REQ 03A6 FORCE — — — — — — — — IRQSEL<6:0> 0000 / DMA3STA 03A8 STA<15:0> 0000 X DMA3STB 03AA STB<15:0> 0000 1 DMA3PAD 03AC PAD<15:0> 0000 0 DMA3CNT 03AE — — — — — — CNT<9:0> 0000 DMA4CON 03B0 CHEN SIZE DIR HALF NULLW — — — — — AMODE<1:0> — — MODE<1:0> 0000 DMA4REQ 03B2 FORCE — — — — — — — — IRQSEL<6:0> 0000 © DMA4STA 03B4 STA<15:0> 0000 2 0 DMA4STB 03B6 STB<15:0> 0000 0 9 M DMA4PAD 03B8 PAD<15:0> 0000 ic DMA4CNT 03BA — — — — — — CNT<9:0> 0000 ro ch DMA5CON 03BC CHEN SIZE DIR HALF NULLW — — — — — AMODE<1:0> — — MODE<1:0> 0000 ip T DMA5REQ 03BE FORCE — — — — — — — — IRQSEL<6:0> 0000 e c DMA5STA 03C0 STA<15:0> 0000 h no DMA5STB 03C2 STB<15:0> 0000 lo g DMA5PAD 03C4 PAD<15:0> 0000 y In Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. c .

© TABLE 4-17: DMA REGISTER MAP (CONTINUED) 2 0 0 All 9 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 M Resets icro DMA5CNT 03C6 — — — — — — CNT<9:0> 0000 c h DMA6CON 03C8 CHEN SIZE DIR HALF NULLW — — — — — AMODE<1:0> — — MODE<1:0> 0000 ip T DMA6REQ 03CA FORCE — — — — — — — — IRQSEL<6:0> 0000 e ch DMA6STA 03CC STA<15:0> 0000 n o DMA6STB 03CE STB<15:0> 0000 lo gy DMA6PAD 03D0 PAD<15:0> 0000 In DMA6CNT 03D2 — — — — — — CNT<9:0> 0000 c . DMA7CON 03D4 CHEN SIZE DIR HALF NULLW — — — — — AMODE<1:0> — — MODE<1:0> 0000 DMA7REQ 03D6 FORCE — — — — — — — — IRQSEL<6:0> 0000 DMA7STA 03D8 STA<15:0> 0000 d DMA7STB 03DA STB<15:0> 0000 s DMA7PAD 03DC PAD<15:0> 0000 P DMA7CNT 03DE — — — — — — CNT<9:0> 0000 I DMACS0 03E0 PWCOL7 PWCOL6 PWCOL5 PWCOL4 PWCOL3 PWCOL2 PWCOL1 PWCOL0 XWCOL7 XWCOL6 XWCOL5 XWCOL4 XWCOL3 XWCOL2 XWCOL1 XWCOL0 0000 C DMACS1 03E2 — — — — LSTCH<3:0> PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 0000 3 DSADR 03E4 DSADR<15:0> 0000 3 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. F J X X X G P X 0 6 / X D 0 S 70 8 2 86 / C X -p a 1 g e 5 0 1

DS T ABLE 4-18: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 0 OR 1 FOR dsPIC33FJXXXGP506/510/706/708/710 DEVICES ONLY d 70 s 2 All 8 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P 6 Resets C -pa C1CTRL1 0400 — — CSIDL ABAT — REQOP<2:0> OPMODE<2:0> — CANCAP — — WIN 0480 IC g e C1CTRL2 0402 — — — — — — — — — — — DNCNT<4:0> 0000 5 3 2 C1VEC 0404 — — — FILHIT<4:0> — ICODE<6:0> 0000 3 C1FCTRL 0406 DMABS<2:0> — — — — — — — — FSA<4:0> 0000 F C1FIFO 0408 — — FBP<5:0> — — FNRB<5:0> 0000 J C1INTF 040A — — TXBO TXBP RXBP TXWAR RXWAR EWARN IVRIF WAKIF ERRIF — FIFOIF RBOVIF RBIF TBIF 0000 X C1INTE 040C — — — — — — — — IVRIE WAKIE ERRIE — FIFOIE RBOVIE RBIE TBIE 0000 C1EC 040E TERRCNT<7:0> RERRCNT<7:0> 0000 X C1CFG1 0410 — — — — — — — — SJW<1:0> BRP<5:0> 0000 X C1CFG2 0412 — WAKFIL — — — SEG2PH<2:0> SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0> 0000 G C1FEN1 0414 FLTEN15 FLTEN14 FLTEN13 FLTEN12 FLTEN11 FLTEN10 FLTEN9 FLTEN8 FLTEN7 FLTEN6 FLTEN5 FLTEN4 FLTEN3 FLTEN2 FLTEN1 FLTEN0 FFFF C1FMSKSEL1 0418 F7MSK<1:0> F6MSK<1:0> F5MSK<1:0> F4MSK<1:0> F3MSK<1:0> F2MSK<1:0> F1MSK<1:0> F0MSK<1:0> 0000 P C1FMSKSEL2 041A F15MSK<1:0> F14MSK<1:0> F13MSK<1:0> F12MSK<1:0> F11MSK<1:0> F10MSK<1:0> F9MSK<1:0> F8MSK<1:0> 0000 X Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0 6 TABLE 4-19: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 0 FOR dsPIC33FJXXXGP506/510/706/708/710 DEVICES ONLY / X All File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets 0 0400- See definition when WIN = x 8 041E / C1RXFUL1 0420 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9 RXFUL8 RXFUL7 RXFUL6 RXFUL5 RXFUL4 RXFUL3 RXFUL2 RXFUL1 RXFUL0 0000 X C1RXFUL2 0422 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16 0000 1 C1RXOVF1 0428 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 RXOVF8 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 0000 0 C1RXOVF2 042A RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000 C1TR01CON 0430 TXEN1 TXABT1 TXLARB1 TXERR1 TXREQ1 RTREN1 TX1PRI<1:0> TXEN0 TXABAT0 TXLARB0 TXERR0 TXREQ0 RTREN0 TX0PRI<1:0> 0000 C1TR23CON 0432 TXEN3 TXABT3 TXLARB3 TXERR3 TXREQ3 RTREN3 TX3PRI<1:0> TXEN2 TXABAT2 TXLARB2 TXERR2 TXREQ2 RTREN2 TX2PRI<1:0> 0000 © 2 C1TR45CON 0434 TXEN5 TXABT5 TXLARB5 TXERR5 TXREQ5 RTREN5 TX5PRI<1:0> TXEN4 TXABAT4 TXLARB4 TXERR4 TXREQ4 RTREN4 TX4PRI<1:0> 0000 0 0 C1TR67CON 0436 TXEN7 TXABT7 TXLARB7 TXERR7 TXREQ7 RTREN7 TX7PRI<1:0> TXEN6 TXABAT6 TXLARB6 TXERR6 TXREQ6 RTREN6 TX6PRI<1:0> xxxx 9 M C1RXD 0440 Received Data Word xxxx ic ro C1TXD 0442 Transmit Data Word xxxx c hip Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. T e c h n o lo g y In c .

© 2 TABLE 4-20: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 FOR dsPIC33FJXXXGP506/510/706/708/710 DEVICES ONLY 0 0 9 M File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts ic ro 0400- See definition when WIN = x c h 041E ip T C1BUFPNT1 0420 F3BP<3:0> F2BP<3:0> F1BP<3:0> F0BP<3:0> 0000 e ch C1BUFPNT2 0422 F7BP<3:0> F6BP<3:0> F5BP<3:0> F4BP<3:0> 0000 n o C1BUFPNT3 0424 F11BP<3:0> F10BP<3:0> F9BP<3:0> F8BP<3:0> 0000 lo gy C1BUFPNT4 0426 F15BP<3:0> F14BP<3:0> F13BP<3:0> F12BP<3:0> 0000 In C1RXM0SID 0430 SID<10:3> SID<2:0> — MIDE — EID<17:16> xxxx c . C1RXM0EID 0432 EID<15:8> EID<7:0> xxxx C1RXM1SID 0434 SID<10:3> SID<2:0> — MIDE — EID<17:16> xxxx C1RXM1EID 0436 EID<15:8> EID<7:0> xxxx d C1RXM2SID 0438 SID<10:3> SID<2:0> — MIDE — EID<17:16> xxxx s C1RXM2EID 043A EID<15:8> EID<7:0> xxxx P C1RXF0SID 0440 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx I C1RXF0EID 0442 EID<15:8> EID<7:0> xxxx C C1RXF1SID 0444 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx 3 C1RXF1EID 0446 EID<15:8> EID<7:0> xxxx 3 C1RXF2SID 0448 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx F C1RXF2EID 044A EID<15:8> EID<7:0> xxxx J C1RXF3SID 044C SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx X C1RXF3EID 044E EID<15:8> EID<7:0> xxxx C1RXF4SID 0450 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx X C1RXF4EID 0452 EID<15:8> EID<7:0> xxxx X C1RXF5SID 0454 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx G C1RXF5EID 0456 EID<15:8> EID<7:0> xxxx P C1RXF6SID 0458 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx C1RXF6EID 045A EID<15:8> EID<7:0> xxxx X C1RXF7SID 045C SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx 0 C1RXF7EID 045E EID<15:8> EID<7:0> xxxx 6 C1RXF8SID 0460 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx / X C1RXF8EID 0462 EID<15:8> EID<7:0> xxxx DS C1RXF9SID 0464 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx 0 70 C1RXF9EID 0466 EID<15:8> EID<7:0> xxxx 8 2 86 C1RXF10SID 0468 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx / C X -p C1RXF10EID 046A EID<15:8> EID<7:0> xxxx a 1 g Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. e 5 0 3

TABLE 4-20: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 FOR dsPIC33FJXXXGP506/510/706/708/710 DEVICES ONLY (CONTINUED) D d S 70 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All s 2 Resets 8 P 6 C C1RXF11SID 046C SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx -p I a C1RXF11EID 046E EID<15:8> EID<7:0> xxxx C g e 5 C1RXF12SID 0470 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx 3 4 C1RXF12EID 0472 EID<15:8> EID<7:0> xxxx 3 C1RXF13SID 0474 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx F C1RXF13EID 0476 EID<15:8> EID<7:0> xxxx J C1RXF14SID 0478 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx X C1RXF14EID 047A EID<15:8> EID<7:0> xxxx C1RXF15SID 047C SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx X C1RXF15EID 047E EID<15:8> EID<7:0> xxxx X Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. G P X 0 6 / X 0 8 / X 1 0 © 2 0 0 9 M ic ro c h ip T e c h n o lo g y In c .

© 2 T ABLE 4-21: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 0 OR 1 FOR dsPIC33FJXXXGP706/708/710 DEVICES ONLY 0 09 M File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts ic ro C2CTRL1 0500 — — CSIDL ABAT — REQOP<2:0> OPMODE<2:0> — CANCAP — — WIN 0480 c hip C2CTRL2 0502 — — — — — — — — — — — DNCNT<4:0> 0000 Te C2VEC 0504 — — — FILHIT<4:0> — ICODE<6:0> 0000 c hn C2FCTRL 0506 DMABS<2:0> — — — — — — — — FSA<4:0> 0000 o lo C2FIFO 0508 — — FBP<5:0> — — FNRB<5:0> 0000 g y In C2INTF 050A — — TXBO TXBP RXBP TXWAR RXWAR EWARN IVRIF WAKIF ERRIF — FIFOIF RBOVIF RBIF TBIF 0000 c C2INTE 050C — — — — — — — — IVRIE WAKIE ERRIE — FIFOIE RBOVIE RBIE TBIE 0000 . C2EC 050E TERRCNT<7:0> RERRCNT<7:0> 0000 C2CFG1 0510 — — — — — — — — SJW<1:0> BRP<5:0> 0000 C2CFG2 0512 — WAKFIL — — — SEG2PH<2:0> SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0> 0000 d C2FEN1 0514 FLTEN15 FLTEN14 FLTEN13 FLTEN12 FLTEN11 FLTEN10 FLTEN9 FLTEN8 FLTEN7 FLTEN6 FLTEN5 FLTEN4 FLTEN3 FLTEN2 FLTEN1 FLTEN0 FFFF s C2FMSKSEL1 0518 F7MSK<1:0> F6MSK<1:0> F5MSK<1:0> F4MSK<1:0> F3MSK<1:0> F2MSK<1:0> F1MSK<1:0> F0MSK<1:0> 0000 P C2FMSKSEL2 051A F15MSK<1:0> F14MSK<1:0> F13MSK<1:0> F12MSK<1:0> F11MSK<1:0> F10MSK<1:0> F9MSK<1:0> F8MSK<1:0> 0000 I Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. C 3 TABLE 4-22: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 0 FOR dsPIC33FJXXXGP706/708/710 DEVICES ONLY 3 All F File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets J 0500- See definition when WIN = x X 051E C2RXFUL1 0520 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9 RXFUL8 RXFUL7 RXFUL6 RXFUL5 RXFUL4 RXFUL3 RXFUL2 RXFUL1 RXFUL0 0000 X C2RXFUL2 0522 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16 0000 X C2RXOVF1 0528 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF09 RXOVF08 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 0000 G C2RXOVF2 052A RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000 P C2TR01CON 0530 TXEN1 TX TX TX TX RTREN1 TX1PRI<1:0> TXEN0 TX TX TX TX RTREN0 TX0PRI<1:0> 0000 ABAT1 LARB1 ERR1 REQ1 ABAT0 LARB0 ERR0 REQ0 X C2TR23CON 0532 TXEN3 TX TX TX TX RTREN3 TX3PRI<1:0> TXEN2 TX TX TX TX RTREN2 TX2PRI<1:0> 0000 ABAT3 LARB3 ERR3 REQ3 ABAT2 LARB2 ERR2 REQ2 0 C2TR45CON 0534 TXEN5 TX TX TX TX RTREN5 TX5PRI<1:0> TXEN4 TX TX TX TX RTREN4 TX4PRI<1:0> 0000 6 ABAT5 LARB5 ERR5 REQ5 ABAT4 LARB4 ERR4 REQ4 / X C2TR67CON 0536 TXEN7 TX TX TX TX RTREN7 TX7PRI<1:0> TXEN6 TX TX TX TX RTREN6 TX6PRI<1:0> xxxx D ABAT7 LARB7 ERR7 REQ7 ABAT6 LARB6 ERR6 REQ6 0 S 70 C2RXD 0540 Recieved Data Word xxxx 8 286 C2TXD 0542 Transmit Data Word xxxx / C Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. X -p a 1 g e 5 0 5

D TABLE 4-23: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 1 FOR dsPIC33FJXXXGP706/708/710 DEVICES ONLY d S 70 All s 2 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 8 Resets P 6 C -p 0500 See definition when WIN = x I a - C g e 051E 5 3 6 C2BUFPNT1 0520 F3BP<3:0> F2BP<3:0> F1BP<3:0> F0BP<3:0> 0000 3 C2BUFPNT2 0522 F7BP<3:0> F6BP<3:0> F5BP<3:0> F4BP<3:0> 0000 F C2BUFPNT3 0524 F11BP<3:0> F10BP<3:0> F9BP<3:0> F8BP<3:0> 0000 C2BUFPNT4 0526 F15BP<3:0> F14BP<3:0> F13BP<3:0> F12BP<3:0> 0000 J C2RXM0SID 0530 SID<10:3> SID<2:0> — MIDE — EID<17:16> xxxx X C2RXM0EID 0532 EID<15:8> EID<7:0> xxxx X C2RXM1SID 0534 SID<10:3> SID<2:0> — MIDE — EID<17:16> xxxx X C2RXM1EID 0536 EID<15:8> EID<7:0> xxxx G C2RXM2SID 0538 SID<10:3> SID<2:0> — MIDE — EID<17:16> xxxx C2RXM2EID 053A EID<15:8> EID<7:0> xxxx P C2RXF0SID 0540 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx X C2RXF0EID 0542 EID<15:8> EID<7:0> xxxx 0 C2RXF1SID 0544 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx 6 C2RXF1EID 0546 EID<15:8> EID<7:0> xxxx / C2RXF2SID 0548 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx X C2RXF2EID 054A EID<15:8> EID<7:0> xxxx 0 C2RXF3SID 054C SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx 8 C2RXF3EID 054E EID<15:8> EID<7:0> xxxx / X C2RXF4SID 0550 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx C2RXF4EID 0552 EID<15:8> EID<7:0> xxxx 1 C2RXF5SID 0554 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx 0 C2RXF5EID 0556 EID<15:8> EID<7:0> xxxx C2RXF6SID 0558 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx C2RXF6EID 055A EID<15:8> EID<7:0> xxxx © 2 C2RXF7SID 055C SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx 0 09 C2RXF7EID 055E EID<15:8> EID<7:0> xxxx M C2RXF8SID 0560 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx ic ro C2RXF8EID 0562 EID<15:8> EID<7:0> xxxx c h ip C2RXF9SID 0564 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx Te C2RXF9EID 0566 EID<15:8> EID<7:0> xxxx c hn C2RXF10SID 0568 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx o lo Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. g y In c .

© TABLE 4-23: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 1 FOR dsPIC33FJXXXGP706/708/710 DEVICES ONLY (CONTINUED) 2 0 0 All 9 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 M Resets icro C2RXF10EID 056A EID<15:8> EID<7:0> xxxx c h C2RXF11SID 056C SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx ip T C2RXF11EID 056E EID<15:8> EID<7:0> xxxx e ch C2RXF12SID 0570 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx n o C2RXF12EID 0572 EID<15:8> EID<7:0> xxxx lo gy C2RXF13SID 0574 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx Inc C2RXF13EID 0576 EID<15:8> EID<7:0> xxxx . C2RXF14SID 0578 SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx C2RXF14EID 057A EID<15:8> EID<7:0> xxxx C2RXF15SID 057C SID<10:3> SID<2:0> — EXIDE — EID<17:16> xxxx d C2RXF15EID 057E EID<15:8> EID<7:0> xxxx s Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. P I C 3 3 F J X X X G P X 0 6 / X D 0 S 70 8 2 86 / C X -p a 1 g e 5 0 7

D TABLE 4-24: DCI REGISTER MAP d S 70286 NSaFmRe Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State sP C -p DCICON1 0280 DCIEN — DCISIDL — DLOOP CSCKD CSCKE COFSD UNFM CSDOM DJST — — — COFSM1 COFSM0 0000 0000 0000 0000 I a C ge DCICON2 0282 — — — — BLEN1 BLEN0 — COFSG<3:0> — WS<3:0> 0000 0000 0000 0000 58 DCICON3 0284 — — — — BCG<11:0> 0000 0000 0000 0000 3 DCISTAT 0286 — — — — SLOT3 SLOT2 SLOT1 SLOT0 — — — — ROV RFUL TUNF TMPTY 0000 0000 0000 0000 3 TSCON 0288 TSE15 TSE14 TSE13 TSE12 TSE11 TSE10 TSE9 TSE8 TSE7 TSE6 TSE5 TSE4 TSE3 TSE2 TSE1 TSE0 0000 0000 0000 0000 F RSCON 028C RSE15 RSE14 RSE13 RSE12 RSE11 RSE10 RSE9 RSE8 RSE7 RSE6 RSE5 RSE4 RSE3 RSE2 RSE1 RSE0 0000 0000 0000 0000 J RXBUF0 0290 Receive Buffer #0 Data Register 0000 0000 0000 0000 X RXBUF1 0292 Receive Buffer #1 Data Register 0000 0000 0000 0000 X RXBUF2 0294 Receive Buffer #2 Data Register 0000 0000 0000 0000 X RXBUF3 0296 Receive Buffer #3 Data Register 0000 0000 0000 0000 G TXBUF0 0298 Transmit Buffer #0 Data Register 0000 0000 0000 0000 TXBUF1 029A Transmit Buffer #1 Data Register 0000 0000 0000 0000 P TXBUF2 029C Transmit Buffer #2 Data Register 0000 0000 0000 0000 X TXBUF3 029E Transmit Buffer #3 Data Register 0000 0000 0000 0000 0 Legend: — = unimplemented, read as ‘0’. Note 1: Refer to the “dsPIC33F Family Reference Manual” for descriptions of register bit fields. 6 / TABLE 4-25: PORTA REGISTER MAP(1) X 0 All File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets 8 / TRISA 02C0 TRISA15 TRISA14 TRISA13 TRISA12 — TRISA10 TRISA9 — TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 F6FF X PORTA 02C2 RA15 RA14 RA13 RA12 — RA10 RA9 — RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx 1 LATA 02C4 LATA15 LATA14 LATA13 LATA12 — LATA10 LATA9 — LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxx 0 ODCA(2) 06C0 ODCA15 ODCA14 — — — — — — — — ODCA5 ODCA4 ODCA3 ODCA2 ODCA1 ODCA0 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. Note 1: The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams. © 2 TABLE 4-26: PORTB REGISTER MAP(1) 0 0 9 M File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All ic Resets ro c TRISB 02C6 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF h ip T PORTB 02C8 RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx ec LATB 02CA LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx h no Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. lo Note 1: The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams. g y In c .

© 2 TABLE 4-27: PORTC REGISTER MAP(1) 0 09 M File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts ic ro TRISC 02CC TRISC15 TRISC14 TRISC13 TRISC12 — — — — — — — TRISC4 TRISC3 TRISC2 TRISC1 — F01E c hip PORTC 02CE RC15 RC14 RC13 RC12 — — — — — — — RC4 RC3 RC2 RC1 — xxxx Te LATC 02D0 LATC15 LATC14 LATC13 LATC12 — — — — — — — LATC4 LATC3 LATC2 LATC1 — xxxx c h Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. n o Note 1: The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams. lo g y In TABLE 4-28: PORTD REGISTER MAP(1) c . All File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets TRISD 02D2 TRISD15 TRISD14 TRISD13 TRISD12 TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 FFFF d PORTD 02D4 RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx s LATD 02D6 LATD15 LATD14 LATD13 LATD12 LATD11 LATD10 LATD9 LATD8 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx P ODCD 06D2 ODCD15 ODCD14 ODCD13 ODCD12 ODCD11 ODCD10 ODCD9 ODCD8 ODCD7 ODCD6 ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 ODCD0 0000 I Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. C Note 1: The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams. 3 TABLE 4-29: PORTE REGISTER MAP(1) 3 F All File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets J X TRISE 02D8 — — — — — — — — TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 00FF PORTE 02DA — — — — — — — — RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx X LATE 02DC — — — — — — — — LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxx X Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. G Note 1: The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams. P TABLE 4-30: PORTF REGISTER MAP(1) X File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0 TRISF 02DE — — TRISF13 TRISF12 — — — TRISF8 TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 31FF 6 PORTF 02E0 — — RF13 RF12 — — — RF8 RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 xxxx / X LATF 02E2 — — LATF13 LATF12 — — — LATF8 LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx DS ODCF 06DE — — ODCF13 ODCF12 — — — ODCF8 ODCF7 ODCF6 ODCF5 ODCF4 ODCF3 ODCF2 ODCF1 ODCF0 0000 0 70 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. 8 2 86 Note 1: The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams. / C X -p a 1 g e 5 0 9

D TABLE 4-31: PORTG REGISTER MAP(1) d S 70286 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts sP C -p TRISG 02E4 TRISG15 TRISG14 TRISG13 TRISG12 — — TRISG9 TRISG8 TRISG7 TRISG6 — — TRISG3 TRISG2 TRISG1 TRISG0 F3CF I a C ge PORTG 02E6 RG15 RG14 RG13 RG12 — — RG9 RG8 RG7 RG6 — — RG3 RG2 RG1 RG0 xxxx 60 LATG 02E8 LATG15 LATG14 LATG13 LATG12 — — LATG9 LATG8 LATG7 LATG6 — — LATG3 LATG2 LATG1 LATG0 xxxx 3 ODCG 06E4 ODCG15 ODCG14 ODCG13 ODCG12 — — ODCG9 ODCG8 ODCG7 ODCG6 — — ODCG3 ODCG2 ODCG1 ODCG0 0000 3 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. F Note 1: The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams. J X TABLE 4-32: SYSTEM CONTROL REGISTER MAP X All File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets X RCON 0740 TRAPR IOPUWR — — — — — VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR xxxx(1) G OSCCON 0742 — COSC<2:0> — NOSC<2:0> CLKLOCK — LOCK — CF — LPOSCEN OSWEN 0300(2) P CLKDIV 0744 ROI DOZE<2:0> DOZEN FRCDIV<2:0> PLLPOST<1:0> — PLLPRE<4:0> 3040 X PLLFBD 0746 — — — — — — — PLLDIV<8:0> 0030 OSCTUN 0748 — — — — — — — — — — TUN<5:0> 0000 0 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 6 Note 1: RCON register Reset values dependent on type of Reset. / 2: OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset. X 0 TABLE 4-33: NVM REGISTER MAP 8 All / File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X Resets NVMCON 0760 WR WREN WRERR — — — — — — ERASE — — NVMOP<3:0> 0000(1) 1 0 NVMKEY 0766 — — — — — — — — NVMKEY<7:0> 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset. © 2 TABLE 4-34: PMD REGISTER MAP 0 0 9 All M File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets ic ro PMD1 0770 T5MD T4MD T3MD T2MD T1MD — — DCIMD I2C1MD U2MD U1MD SPI2MD SPI1MD C2MD C1MD AD1MD 0000 c h ip PMD2 0772 IC8MD IC7MD IC6MD IC5MD IC4MD IC3MD IC2MD IC1MD OC8MD OC7MD OC6MD OC5MD OC4MD OC3MD OC2MD OC1MD 0000 T e PMD3 0774 T9MD T8MD T7MD T6MD — — — — — — — — — — I2C2MD AD2MD 0000 c hn Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. o lo g y In c .

dsPIC33FJXXXGPX06/X08/X10 4.2.7 SOFTWARE STACK 4.2.8 DATA RAM PROTECTION FEATURE In addition to its use as a working register, the W15 The dsPIC33F product family supports Data RAM register in the dsPIC33FJXXXGPX06/X08/X10 devices protection features which enable segments of RAM to is also used as a software Stack Pointer. The Stack be protected when used in conjunction with Boot and Pointer always points to the first available free word Secure Code Segment Security. BSRAM (Secure RAM and grows from lower to higher addresses. It segment for BS) is accessible only from the Boot pre-decrements for stack pops and post-increments for Segment Flash code when enabled. SSRAM (Secure stack pushes, as shown in Figure4-6. For a PC push RAM segment for RAM) is accessible only from the during any CALL instruction, the MSb of the PC is Secure Segment Flash code when enabled. See zero-extended before the push, ensuring that the MSb Table4-1 for an overview of the BSRAM and SSRAM is always clear. SFRs. Note: A PC push during exception processing 4.3 Instruction Addressing Modes concatenates the SRL register to the MSb of the PC prior to the push. The addressing modes in Table4-35 form the basis of the addressing modes optimized to support the specific The Stack Pointer Limit register (SPLIM) associated features of individual instructions. The addressing with the Stack Pointer sets an upper address boundary modes provided in the MAC class of instructions are for the stack. SPLIM is uninitialized at Reset. As is the case for the Stack Pointer, SPLIM<0> is forced to ‘0’ somewhat different from those in the other instruction types. because all stack operations must be word-aligned. Whenever an EA is generated using W15 as a source 4.3.1 FILE REGISTER INSTRUCTIONS or destination pointer, the resulting address is compared with the value in SPLIM. If the contents of Most file register instructions use a 13-bit address field the Stack Pointer (W15) and the SPLIM register are (f) to directly address data present in the first 8192 equal and a push operation is performed, a stack error bytes of data memory (Near Data Space). Most file trap will not occur. The stack error trap will occur on a register instructions employ a working register, W0, subsequent push operation. Thus, for example, if it is which is denoted as WREG in these instructions. The desirable to cause a stack error trap when the stack destination is typically either the same file register or grows beyond address 0x2000 in RAM, initialize the WREG (with the exception of the MUL instruction), SPLIM with the value 0x1FFE. which writes the result to a register or register pair. The MOV instruction allows additional flexibility and can Similarly, a Stack Pointer underflow (stack error) trap is access the entire data space. generated when the Stack Pointer address is found to be less than 0x0800. This prevents the stack from 4.3.2 MCU INSTRUCTIONS interfering with the Special Function Register (SFR) space. The 3-operand MCU instructions are of the form: A write to the SPLIM register should not be immediately Operand 3 = Operand 1 <function> Operand 2 followed by an indirect read operation using W15. where Operand 1 is always a working register (i.e., the addressing mode can only be register direct) which is FIGURE 4-6: CALL STACK FRAME referred to as Wb. Operand 2 can be a W register, fetched from data memory, or a 5-bit literal. The result 0x0000 15 0 location can be either a W register or a data memory location. The following addressing modes are supported by MCU instructions: s d waress • Register Direct Todr • Register Indirect s Ad ower PC<15:0> W15 (before CALL) • Register Indirect Post-Modified Grgh 000000000 PC<22:16> • Register Indirect Pre-Modified ck Hi <Free Word> W15 (after CALL) a • 5-bit or 10-bit Literal St POP : [--W15] Note: Not all instructions support all the PUSH: [W15++] addressing modes given above. Individual instructions may support different subsets of these addressing modes. © 2009 Microchip Technology Inc. DS70286C-page 61

dsPIC33FJXXXGPX06/X08/X10 TABLE 4-35: FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode Description File Register Direct The address of the file register is specified explicitly. Register Direct The contents of a register are accessed directly. Register Indirect The contents of Wn forms the EA. Register Indirect Post-Modified The contents of Wn forms the EA. Wn is post-modified (incremented or decremented) by a constant value. Register Indirect Pre-Modified Wn is pre-modified (incremented or decremented) by a signed constant value to form the EA. Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset The sum of Wn and a literal forms the EA. 4.3.3 MOVE AND ACCUMULATOR The 2-source operand prefetch registers must be INSTRUCTIONS members of the set {W8, W9, W10, W11}. For data reads, W8 and W9 are always directed to the X RAGU Move instructions and the DSP accumulator class of and W10 and W11 will always be directed to the Y instructions provide a greater degree of addressing AGU. The effective addresses generated (before and flexibility than other instructions. In addition to the after modification) must, therefore, be valid addresses Addressing modes supported by most MCU within X data space for W8 and W9 and Y data space instructions, move and accumulator instructions also for W10 and W11. support Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed Note: Register Indirect with Register Offset mode. Addressing mode is only available for W9 (in X space) and W11 (in Y space). Note: For the MOV instructions, the Addressing mode specified in the instruction can differ In summary, the following addressing modes are for the source and destination EA. supported by the MAC class of instructions: However, the 4-bit Wb (Register Offset) • Register Indirect field is shared between both source and • Register Indirect Post-Modified by 2 destination (but typically only used by • Register Indirect Post-Modified by 4 one). • Register Indirect Post-Modified by 6 In summary, the following Addressing modes are • Register Indirect with Register Offset (Indexed) supported by move and accumulator instructions: • Register Direct 4.3.5 OTHER INSTRUCTIONS • Register Indirect Besides the various addressing modes outlined above, • Register Indirect Post-modified some instructions use literal constants of various sizes. • Register Indirect Pre-modified For example, BRA (branch) instructions use 16-bit signed • Register Indirect with Register Offset (Indexed) literals to specify the branch destination directly, whereas the DISI instruction uses a 14-bit unsigned literal field. In • Register Indirect with Literal Offset some instructions, such as ADD Acc, the source of an • 8-bit Literal operand or result is implied by the opcode itself. Certain • 16-bit Literal operations, such as NOP, do not have any operands. Note: Not all instructions support all the Addressing modes given above. Individual 4.4 Modulo Addressing instructions may support different subsets Modulo Addressing mode is a method of providing an of these Addressing modes. automated means to support circular data buffers using 4.3.4 MAC INSTRUCTIONS hardware. The objective is to remove the need for software to perform data address boundary checks The dual source operand DSP instructions (CLR, ED, when executing tightly looped code, as is typical in EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also referred many DSP algorithms. to as MAC instructions, utilize a simplified set of addressing modes to allow the user to effectively Modulo Addressing can operate in either data or program manipulate the data pointers through register indirect space (since the data pointer mechanism is essentially tables. the same for both). One circular buffer can be supported in each of the X (which also provides the pointers into program space) and Y data spaces. Modulo Addressing DS70286C-page 62 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 can operate on any W register pointer. However, it is not The length of a circular buffer is not directly specified. It advisable to use W14 or W15 for Modulo Addressing is determined by the difference between the since these two registers are used as the Stack Frame corresponding start and end addresses. The maximum Pointer and Stack Pointer, respectively. possible length of the circular buffer is 32K words (64Kbytes). In general, any particular circular buffer can only be configured to operate in one direction as there are 4.4.2 W ADDRESS REGISTER certain restrictions on the buffer start address (for incre- SELECTION menting buffers), or end address (for decrementing buffers), based upon the direction of the buffer. The Modulo and Bit-Reversed Addressing Control register, MODCON<15:0>, contains enable flags as well The only exception to the usage restrictions is for as a W register field to specify the W Address registers. buffers which have a power-of-2 length. As these The XWM and YWM fields select which registers will buffers satisfy the start and end address criteria, they operate with Modulo Addressing. If XWM = 15, XRAGU may operate in a bidirectional mode (i.e., address and X WAGU Modulo Addressing is disabled. Similarly, if boundary checks will be performed on both the lower YWM = 15, Y AGU Modulo Addressing is disabled. and upper address boundaries). The X Address Space Pointer W register (XWM), to 4.4.1 START AND END ADDRESS which Modulo Addressing is to be applied, is stored in The Modulo Addressing scheme requires that a starting MODCON<3:0> (see Table4-1). Modulo Addressing is and ending address be specified and loaded into the enabled for X data space when XWM is set to any value 16-bit Modulo Buffer Address registers: XMODSRT, other than ‘15’ and the XMODEN bit is set at XMODEND, YMODSRT and YMODEND (see MODCON<15>. Table4-1). The Y Address Space Pointer W register (YWM) to Note: Y space Modulo Addressing EA which Modulo Addressing is to be applied is stored in calculations assume word sized data (LSb MODCON<7:4>. Modulo Addressing is enabled for Y of every EA is always clear). data space when YWM is set to any value other than ‘15’ and the YMODEN bit is set at MODCON<14>. FIGURE 4-7: MODULO ADDRESSING OPERATION EXAMPLE Byte MOV #0x1100, W0 Address MOV W0, XMODSRT ;set modulo start address MOV #0x1163, W0 MOV W0, MODEND ;set modulo end address MOV #0x8001, W0 0x1100 MOV W0, MODCON ;enable W1, X AGU for modulo MOV #0x0000, W0 ;W0 holds buffer fill value MOV #0x1110, W1 ;point W1 to buffer DO AGAIN, #0x31 ;fill the 50 buffer locations MOV W0, [W1++] ;fill the next location AGAIN: INC W0, W0 ;increment the fill value 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2009 Microchip Technology Inc. DS70286C-page 63

dsPIC33FJXXXGPX06/X08/X10 4.4.3 MODULO ADDRESSING If the length of a bit-reversed buffer is M = 2N bytes, APPLICABILITY the last ‘N’ bits of the data buffer start address must be zeros. Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W XB<14:0> is the Bit-Reversed Address modifier, or register. It is important to realize that the address ‘pivot point’, which is typically a constant. In the case of boundaries check for addresses less than, or greater an FFT computation, its value is equal to half of the FFT than, the upper (for incrementing buffers) and lower (for data buffer size. decrementing buffers) boundary addresses (not just Note: All bit-reversed EA calculations assume equal to). Address changes may, therefore, jump word sized data (LSb of every EA is beyond boundaries and still be adjusted correctly. always clear). The XB value is scaled Note: The modulo corrected effective address is accordingly to generate compatible (byte) written back to the register only when addresses. Pre-Modify or Post-Modify Addressing When enabled, Bit-Reversed Addressing is only mode is used to compute the effective executed for Register Indirect with Pre-Increment or address. When an address offset (e.g., Post-Increment Addressing and word sized data writes. [W7+W2]) is used, Modulo Address It will not function for any other addressing mode or for correction is performed but the contents of byte sized data and normal addresses are generated the register remain unchanged. instead. When Bit-Reversed Addressing is active, the W Address Pointer is always added to the address 4.5 Bit-Reversed Addressing modifier (XB) and the offset associated with the Regis- ter Indirect Addressing mode is ignored. In addition, as Bit-Reversed Addressing mode is intended to simplify word sized data is a requirement, the LSb of the EA is data re-ordering for radix-2 FFT algorithms. It is ignored (and always clear). supported by the X AGU for data writes only. Note: Modulo Addressing and Bit-Reversed The modifier, which may be a constant value or register Addressing should not be enabled contents, is regarded as having its bit order reversed. The together. In the event that the user attempts address source and destination are kept in normal order. to do so, Bit-Reversed Addressing will Thus, the only operand requiring reversal is the modifier. assume priority when active for the X 4.5.1 BIT-REVERSED ADDRESSING WAGU and X WAGU Modulo Addressing will be disabled. However, Modulo IMPLEMENTATION Addressing will continue to function in the X Bit-Reversed Addressing mode is enabled when: RAGU. 1. BWM bits (W register selection) in the If Bit-Reversed Addressing has already been enabled MODCON register are any value other than ‘15’ by setting the BREN (XBREV<15>) bit, then a write to (the stack cannot be accessed using the XBREV register should not be immediately followed Bit-Reversed Addressing). by an indirect read operation using the W register that 2. The BREN bit is set in the XBREV register. has been designated as the bit-reversed pointer. 3. The addressing mode used is Register Indirect with Pre-Increment or Post-Increment. DS70286C-page 64 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 FIGURE 4-8: BIT-REVERSED ADDRESS EXAMPLE Sequential Address b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0 Bit Locations Swapped Left-to-Right Around Center of Binary Value b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0 Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer TABLE 4-36: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address Bit-Reversed Address A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 8 0 0 1 0 2 0 1 0 0 4 0 0 1 1 3 1 1 0 0 12 0 1 0 0 4 0 0 1 0 2 0 1 0 1 5 1 0 1 0 10 0 1 1 0 6 0 1 1 0 6 0 1 1 1 7 1 1 1 0 14 1 0 0 0 8 0 0 0 1 1 1 0 0 1 9 1 0 0 1 9 1 0 1 0 10 0 1 0 1 5 1 0 1 1 11 1 1 0 1 13 1 1 0 0 12 0 0 1 1 3 1 1 0 1 13 1 0 1 1 11 1 1 1 0 14 0 1 1 1 7 1 1 1 1 15 1 1 1 1 15 © 2009 Microchip Technology Inc. DS70286C-page 65

dsPIC33FJXXXGPX06/X08/X10 4.6 Interfacing Program and Data 4.6.1 ADDRESSING PROGRAM SPACE Memory Spaces Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is The dsPIC33FJXXXGPX06/X08/X10 architecture uses needed to create a 23-bit or 24-bit program address a 24-bit wide program space and a 16-bit wide data from 16-bit data registers. The solution depends on the space. The architecture is also a modified Harvard interface method to be used. scheme, meaning that data can also be present in the program space. To use this data successfully, it must For table operations, the 8-bit Table Page register be accessed in a way that preserves the alignment of (TBLPAG) is used to define a 32Kword region within information in both spaces. the program space. This is concatenated with a 16-bit EA to arrive at a full 24-bit program space address. In Aside from normal execution, the this format, the Most Significant bit of TBLPAG is used dsPIC33FJXXXGPX06/X08/X10 architecture provides to determine if the operation occurs in the user memory two methods by which program space can be accessed (TBLPAG<7> = 0) or the configuration memory during operation: (TBLPAG<7> = 1). • Using table instructions to access individual bytes For remapping operations, the 8-bit Program Space or words anywhere in the program space Visibility register (PSVPAG) is used to define a • Remapping a portion of the program space into 16Kword page in the program space. When the Most the data space (Program Space Visibility) Significant bit of the EA is ‘1’, PSVPAG is concatenated Table instructions allow an application to read or write with the lower 15 bits of the EA to form a 23-bit program to small areas of the program memory. This capability space address. Unlike table operations, this limits makes the method ideal for accessing data tables that remapping operations strictly to the user memory area. need to be updated from time to time. It also allows Table4-37 and Figure4-9 show how the program EA is access to all bytes of the program word. The created for table operations and remapping accesses remapping method allows an application to access a from the data EA. Here, P<23:0> refers to a program large block of data on a read-only basis, which is ideal space word, whereas D<15:0> refers to a data space for look ups from a large table of static data. It can only word. access the least significant word of the program word. TABLE 4-37: PROGRAM SPACE ADDRESS CONSTRUCTION Access Program Space Address Access Type Space <23> <22:16> <15> <14:1> <0> Instruction Access User 0 PC<22:1> 0 (Code Execution) 0xx xxxx xxxx xxxx xxxx xxx0 TBLRD/TBLWT User TBLPAG<7:0> Data EA<15:0> (Byte/Word Read/Write) 0xxx xxxx xxxx xxxx xxxx xxxx Configuration TBLPAG<7:0> Data EA<15:0> 1xxx xxxx xxxx xxxx xxxx xxxx Program Space Visibility User 0 PSVPAG<7:0> Data EA<14:0>(1) (Block Remap/Read) 0 xxxx xxxx xxx xxxx xxxx xxxx Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG<0>. DS70286C-page 66 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 FIGURE 4-9: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter(1) 0 Program Counter 0 23 bits EA 1/0 Table Operations(2) 1/0 TBLPAG 8 bits 16 bits 24 bits Select 1 EA 0 Program Space Visibility(1) 0 PSVPAG (Remapping) 8 bits 15 bits 23 bits User/Configuration Byte Select Space Select Note1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space. © 2009 Microchip Technology Inc. DS70286C-page 67

dsPIC33FJXXXGPX06/X08/X10 4.6.2 DATA ACCESS FROM PROGRAM 2. TBLRDH (Table Read High): In Word mode, it MEMORY USING TABLE maps the entire upper word of a program address INSTRUCTIONS (P<23:16>) to a data address. Note that D<15:8>, the ‘phantom byte’, will always be ‘0’. The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any In Byte mode, it maps the upper or lower byte of address within the program space without going the program word to D<7:0> of the data through data space. The TBLRDH and TBLWTH address, as above. Note that the data will instructions are the only method to read or write the always be ‘0’ when the upper ‘phantom’ byte is upper 8bits of a program space word as data. selected (Byte Select = 1). The PC is incremented by two for each successive In a similar fashion, two table instructions, TBLWTH 24-bit program word. This allows program memory and TBLWTL, are used to write individual bytes or addresses to directly map to data space addresses. words to a program space address. The details of Program memory can thus be regarded as two 16-bit their operation are explained in Section5.0 “Flash word wide address spaces, residing side by side, each Program Memory”. with the same address range. TBLRDL and TBLWTL For all table operations, the area of program memory access the space which contains the least significant space to be accessed is determined by the Table Page data word and TBLRDH and TBLWTH access the space register (TBLPAG). TBLPAG covers the entire program which contains the upper data byte. memory space of the device, including user and Two table instructions are provided to move byte or configuration spaces. When TBLPAG<7> = 0, the table word sized (16-bit) data to and from program space. page is located in the user memory space. When Both function as either byte or word operations. TBLPAG<7> = 1, the page is located in configuration space. 1. TBLRDL (Table Read Low): In Word mode, it maps the lower word of the program space location (P<15:0>) to a data address (D<15:0>). In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when Byte Select is ‘1’; the lower byte is selected when it is ‘0’. FIGURE 4-10: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS Program Space TBLPAG 02 23 15 0 0x000000 23 16 8 0 00000000 00000000 0x020000 00000000 0x030000 00000000 ‘Phantom’ Byte TBLRDH.B (Wn<0> = 0) TBLRDL.B (Wn<0> = 1) TBLRDL.B (Wn<0> = 0) TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. 0x800000 Only read operations are shown; write operations are also valid in the user memory area. DS70286C-page 68 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 4.6.3 READING DATA FROM PROGRAM 24-bit program word are used to contain the data. The MEMORY USING PROGRAM SPACE upper 8 bits of any program space location used as VISIBILITY data should be programmed with ‘1111 1111’ or ‘0000 0000’ to force a NOP. This prevents possible The upper 32Kbytes of data space may optionally be issues should the area of code ever be accidentally mapped into any 16Kword page of the program space. executed. This option provides transparent access of stored constant data from the data space without the need to Note: PSV access is temporarily disabled during use special instructions (i.e., TBLRDL/H). table reads/writes. Program space access through the data space occurs For operations that use PSV and are executed outside if the Most Significant bit of the data space EA is ‘1’ and a REPEAT loop, the MOV and MOV.D instructions program space visibility is enabled by setting the PSV require one instruction cycle in addition to the specified bit in the Core Control register (CORCON<2>). The execution time. All other instructions require two location of the program memory space to be mapped instruction cycles in addition to the specified execution into the data space is determined by the Program time. Space Visibility Page register (PSVPAG). This 8-bit For operations that use PSV, which are executed inside register defines any one of 256 possible pages of a REPEAT loop, there will be some instances that 16Kwords in program space. In effect, PSVPAG require two instruction cycles in addition to the functions as the upper 8 bits of the program memory specified execution time of the instruction: address, with the 15 bits of the EA functioning as the lower bits. Note that by incrementing the PC by 2 for • Execution in the first iteration each program memory word, the lower 15 bits of data • Execution in the last iteration space addresses directly map to the lower 15 bits in the • Execution prior to exiting the loop due to an corresponding program space addresses. interrupt Data reads to this area add an additional cycle to the • Execution upon re-entering the loop after an instruction being executed, since two program memory interrupt is serviced fetches are required. Any other iteration of the REPEAT loop will allow the Although each data space address, 8000h and higher, instruction accessing data, using PSV, to execute in a maps directly into a corresponding program memory single cycle. address (see Figure4-11), only the lower 16bits of the FIGURE 4-11: PROGRAM SPACE VISIBILITY OPERATION When CORCON<2> = 1 and EA<15> = 1: Program Space Data Space PSVPAG 23 15 0 02 0x000000 0x0000 Data EA<14:0> 0x010000 0x018000 The data in the page designated by PSV- PAG is mapped into the upper half of the data memory 0x8000 space... PSV Area ...while the lower 15 bits of the EA specify an exact address within 0xFFFF the PSV area. This corresponds exactly to the same lower 15 bits of the actual program space address. 0x800000 © 2009 Microchip Technology Inc. DS70286C-page 69

dsPIC33FJXXXGPX06/X08/X10 NOTES: DS70286C-page 70 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 5.0 FLASH PROGRAM MEMORY program the digital signal controller just before shipping the product. This also allows the most recent firmware Note: This data sheet summarizes the features or a custom firmware to be programmed. of the dsPIC33FJXXXGPX06/X08/X10 RTSP is accomplished using TBLRD (table read) and family of devices. However, it is not TBLWT (table write) instructions. With RTSP, the user intended to be a comprehensive reference can write program memory data either in blocks or source. To complement the information in ‘rows’ of 64 instructions (192 bytes) at a time or a single this data sheet, refer to Section 5. “Flash program memory word, and erase program memory in Programming” (DS70191) in the blocks or ‘pages’ of 512 instructions (1536 bytes) at a “dsPIC33F Family Reference Manual”, time. which is available from the Microchip web site (www.microchip.com). 5.1 Table Instructions and Flash The dsPIC33FJXXXGPX06/X08/X10 devices contain Programming internal Flash program memory for storing and executing application code. The memory is readable, Regardless of the method used, all programming of writable and erasable during normal operation over the Flash memory is done with the table read and table entire VDD range. write instructions. These allow direct read and write access to the program memory space from the data Flash memory can be programmed in two ways: memory while the device is in normal operating mode. 1. In-Circuit Serial Programming™ (ICSP™) The 24-bit target address in the program memory is programming capability formed using bits<7:0> of the TBLPAG register and the 2. Run-Time Self-Programming (RTSP) Effective Address (EA) from a W register specified in the table instruction, as shown in Figure5-1. ICSP allows a dsPIC33FJXXXGPX06/X08/X10 device to be serially programmed while in the end application The TBLRDL and the TBLWTL instructions are used to circuit. This is simply done with two lines for read or write to bits<15:0> of program memory. programming clock and programming data (one of the TBLRDL and TBLWTL can access program memory in alternate programming pin pairs: PGECx/PGEDx), and both Word and Byte modes. three other lines for power (VDD), ground (VSS) and The TBLRDH and TBLWTH instructions are used to read Master Clear (MCLR). This allows customers to manu- or write to bits<23:16> of program memory. TBLRDH facture boards with unprogrammed devices and then and TBLWTH can also access program memory in Word or Byte mode. FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS 24 bits Using 0 Program Counter 0 Program Counter Working Reg EA Using 1/0 TBLPAG Reg Table Instruction 8 bits 16 bits User/Configuration Byte Space Select 24-bit EA Select © 2009 Microchip Technology Inc. DS70286C-page 71

dsPIC33FJXXXGPX06/X08/X10 5.2 RTSP Operation 5.3 Programming Operations The dsPIC33FJXXXGPX06/X08/X10 Flash program A complete programming sequence is necessary for memory array is organized into rows of 64 instructions programming or erasing the internal Flash in RTSP or 192 bytes. RTSP allows the user to erase a page of mode. The processor stalls (waits) until the memory, which consists of eight rows (512 instructions) programming operation is finished. at a time, and to program one row or one word at a The programming time depends on the FRC accuracy time. Table25-12 illustrates typical erase and program- (see Table25-19) and the value of the FRC Oscillator ming times. The 8-row erase pages and single row Tuning register (see Register9-4). Use the following write rows are edge-aligned, from the beginning of pro- formula to calculate the minimum and maximum values gram memory, on boundaries of 1536 bytes and 192 for the Row Write Time, Page Erase Time and Word bytes, respectively. Write Cycle Time parameters (see Table25-12). The program memory implements holding buffers that can contain 64 instructions of programming data. Prior EQUATION 5-1: PROGRAMMING TIME to the actual programming operation, the write data must be loaded into the buffers in sequential order. The ------------------------------------------------------------T-------------------------------------------------------------- instruction words loaded must always be from a group 7.37 MHz×(FRC Accuracy)%×(FRC Tuning)% of 64 boundary. The basic sequence for RTSP programming is to set up For example, if the device is operating at +85°C, the a Table Pointer, then do a series of TBLWT instructions FRC accuracy will be ±2%. If the TUN<5:0> bits (see to load the buffers. Programming is performed by Register9-4) are set to ‘b111111, the Minimum setting the control bits in the NVMCON register. A total Row Write Time is: of 64 TBLWTL and TBLWTH instructions are required 11064 Cycles to load the instructions. TRW =7---.--3---7--- --M-----H----z----×-----(--1-----+-----0---.-0---2----)---×-----(--1-----–----0---.--0---0---3---7---5---)-=1.48ms All of the table write operations are single-word writes (two instruction cycles) because only the buffers are and, the Maximum Row Write Time is: written. A programming cycle is required for 11064 Cycles programming each row. TRW =7----.-3---7--- --M-----H----z----×-----(--1-----–----0---.--0---2---)----×-----(--1----–-----0---.--0--0---3---7----5----)=1.54ms Setting the WR bit (NVMCON<15>) starts the opera- tion, and the WR bit is automatically cleared when the operation is finished. 5.4 Control Registers There are two SFRs used to read and write the program Flash memory: • NVMCON: Flash Memory Control Register • NVMKEY: Non-Volatile Memory Key Register The NVMCON register (Register5-1) controls which blocks are to be erased, which memory type is to be programmed and the start of the programming cycle. NVMKEY (Register5-2) is a write-only register that is used for write protection. To start a programming or erase sequence, the user must consecutively write 55h and AAh to the NVMKEY register. Refer to Section5.3 “Programming Operations” for further details. DS70286C-page 72 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER R/SO-0(1) R/W-0(1) R/W-0(1) U-0 U-0 U-0 U-0 U-0 WR WREN WRERR — — — — — bit 15 bit 8 U-0 R/W-0(1) U-0 U-0 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1) — ERASE — — NVMOP<3:0>(2) bit 7 bit 0 Legend: SO = Settable only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 WR: Write Control bit 1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete 0 = Program or erase operation is complete and inactive bit 14 WREN: Write Enable bit 1 = Enable Flash program/erase operations 0 = Inhibit Flash program/erase operations bit 13 WRERR: Write Sequence Error Flag bit 1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically on any set attempt of the WR bit) 0 = The program or erase operation completed normally bit 12-7 Unimplemented: Read as ‘0’ bit 6 ERASE: Erase/Program Enable bit 1 = Perform the erase operation specified by NVMOP<3:0> on the next WR command 0 = Perform the program operation specified by NVMOP<3:0> on the next WR command bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 NVMOP<3:0>: NVM Operation Select bits(2) If ERASE = 1: 1111 = Memory bulk erase operation 1110 = Reserved 1101 = Erase General Segment 1100 = Erase Secure Segment 1011 = Reserved 0011 = No operation 0010 = Memory page erase operation 0001 = No operation 0000 = Erase a single Configuration register byte If ERASE = 0: 1111 = No operation 1110 = Reserved 1101 = No operation 1100 = No operation 1011 = Reserved 0011 = Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte Note1: These bits can only be reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. © 2009 Microchip Technology Inc. DS70286C-page 73

dsPIC33FJXXXGPX06/X08/X10 REGISTER 5-2: NVMKEY: NON-VOLATILE MEMORY KEY REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY<7:0> bit 7 bit 0 Legend: SO = Settable only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMKEY<7:0>: Key Register (Write Only) bits DS70286C-page 74 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 5.4.1 PROGRAMMING ALGORITHM FOR 4. Write the first 64 instructions from data RAM into FLASH PROGRAM MEMORY the program memory buffers (see Example5-2). 5. Write the program block to Flash memory: The user can program one row of program Flash memory at a time. To do this, it is necessary to erase a) Set the NVMOP bits to ‘0001’ to configure the 8-row erase page that contains the desired row. for row programming. Clear the ERASE bit The general process is: and set the WREN bit. b) Write #0x55 to NVMKEY. 1. Read eight rows of program memory (512instructions) and store in data RAM. c) Write #0xAA to NVMKEY. 2. Update the program data in RAM with the d) Set the WR bit. The programming cycle desired new data. begins and the CPU stalls for the duration of the write cycle. When the write to Flash 3. Erase the block (see Example5-1): memory is done, the WR bit is cleared a) Set the NVMOP bits (NVMCON<3:0>) to automatically. ‘0010’ to configure for block erase. Set the 6. Repeat steps 4 and 5, using the next available ERASE (NVMCON<6>) and WREN 64 instructions from the block in data RAM by (NVMCON<14>) bits. incrementing the value in TBLPAG, until all b) Write the starting address of the page to be 512instructions are written back to Flash memory. erased into the TBLPAG and W registers. For protection against accidental operations, the write c) Write 55h to NVMKEY. initiate sequence for NVMKEY must be used to allow d) Write AAh to NVMKEY. any erase or program operation to proceed. After the e) Set the WR bit (NVMCON<15>). The erase programming command has been executed, the user cycle begins and the CPU stalls for the must wait for the programming time until programming duration of the erase cycle. When the erase is is complete. The two instructions following the start of done, the WR bit is cleared automatically. the programming sequence should be NOPs, as shown in Example5-3. EXAMPLE 5-1: ERASING A PROGRAM MEMORY PAGE ; Set up NVMCON for block erase operation MOV #0x4042, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Init pointer to row to be ERASED MOV #tblpage(PROG_ADDR), W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #tbloffset(PROG_ADDR), W0 ; Initialize in-page EA[15:0] pointer TBLWTL W0, [W0] ; Set base address of erase block DISI #5 ; Block all interrupts with priority <7 ; for next 5 instructions MOV #0x55, W0 MOV W0, NVMKEY ; Write the 55 key MOV #0xAA, W1 ; MOV W1, NVMKEY ; Write the AA key BSET NVMCON, #WR ; Start the erase sequence NOP ; Insert two NOPs after the erase NOP ; command is asserted © 2009 Microchip Technology Inc. DS70286C-page 75

dsPIC33FJXXXGPX06/X08/X10 EXAMPLE 5-2: LOADING THE WRITE BUFFERS ; Set up NVMCON for row programming operations MOV #0x4001, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #0x6000, W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word MOV #LOW_WORD_0, W2 ; MOV #HIGH_BYTE_0, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 1st_program_word MOV #LOW_WORD_1, W2 ; MOV #HIGH_BYTE_1, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 2nd_program_word MOV #LOW_WORD_2, W2 ; MOV #HIGH_BYTE_2, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch • • • ; 63rd_program_word MOV #LOW_WORD_31, W2 ; MOV #HIGH_BYTE_31, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch EXAMPLE 5-3: INITIATING A PROGRAMMING SEQUENCE DISI #5 ; Block all interrupts with priority <7 ; for next 5 instructions MOV #0x55, W0 MOV W0, NVMKEY ; Write the 55 key MOV #0xAA, W1 ; MOV W1, NVMKEY ; Write the AA key BSET NVMCON, #WR ; Start the erase sequence NOP ; Insert two NOPs after the NOP ; erase command is asserted DS70286C-page 76 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 6.0 RESET Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU Note: This data sheet summarizes the features and peripherals are forced to a known Reset state. of the dsPIC33FJXXXGPX06/X08/X10 Most registers are unaffected by a Reset; their status is family of devices. However, it is not unknown on POR and unchanged by all other Resets. intended to be a comprehensive reference Note: Refer to the specific peripheral or CPU source. To complement the information in section of this manual for register Reset this data sheet, refer to Section 8. states. “Reset” (DS70192) in the “dsPIC33F Family Reference Manual”, which is avail- All types of device Reset will set a corresponding status able from the Microchip web site bit in the RCON register to indicate the type of Reset (www.microchip.com). (see Register6-1). A POR will clear all bits, except for The Reset module combines all Reset sources and the POR bit (RCON<0>), that are set. The user can set controls the device Master Reset Signal, SYSRST. The or clear any bit at any time during code execution. The following is a list of device Reset sources: RCON bits only serve as status bits. Setting a particular Reset status bit in software does not cause a device • POR: Power-on Reset Reset to occur. • BOR: Brown-out Reset The RCON register also has other bits associated with • MCLR: Master Clear Pin Reset the Watchdog Timer and device power-saving states. • SWR: RESET Instruction The function of these bits is discussed in other sections • WDT: Watchdog Timer Reset of this manual. • TRAPR: Trap Conflict Reset Note: The status bits in the RCON register • IOPUWR: Illegal Opcode and Uninitialized W should be cleared after they are read so Register Reset that the next RCON register value after a A simplified block diagram of the Reset module is device Reset will be meaningful. shown in Figure6-1. FIGURE 6-1: RESET SYSTEM BLOCK DIAGRAM RESET Instruction Glitch Filter MCLR WDT Module Sleep or Idle BOR Internal Regulator SYSRST VDD VDD Rise POR Detect Trap Conflict Illegal Opcode Uninitialized W Register © 2009 Microchip Technology Inc. DS70286C-page 77

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 6-1: RCON: RESET CONTROL REGISTER(1) R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 TRAPR IOPUWR — — — — — VREGS bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 EXTR SWR SWDTEN(2) WDTO SLEEP IDLE BOR POR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TRAPR: Trap Reset Flag bit 1 = A Trap Conflict Reset has occurred 0 = A Trap Conflict Reset has not occurred bit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit 1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an Address Pointer caused a Reset 0 = An illegal opcode or uninitialized W Reset has not occurred bit 13-9 Unimplemented: Read as ‘0’ bit 8 VREGS: Voltage Regulator Standby During Sleep bit 1 = Voltage regulator is active during Sleep 0 = Voltage regulator goes into Standby mode during Sleep bit 7 EXTR: External Reset (MCLR) Pin bit 1 = A Master Clear (pin) Reset has occurred 0 = A Master Clear (pin) Reset has not occurred bit 6 SWR: Software Reset (Instruction) Flag bit 1 = A RESET instruction has been executed 0 = A RESET instruction has not been executed bit 5 SWDTEN: Software Enable/Disable of WDT bit(2) 1 = WDT is enabled 0 = WDT is disabled bit 4 WDTO: Watchdog Timer Time-out Flag bit 1 = WDT time-out has occurred 0 = WDT time-out has not occurred bit 3 SLEEP: Wake-up from Sleep Flag bit 1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode bit 2 IDLE: Wake-up from Idle Flag bit 1 = Device was in Idle mode 0 = Device was not in Idle mode bit 1 BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred 0 = A Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit 1 = A Power-on Reset has occurred 0 = A Power-on Reset has not occurred Note1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset. 2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. DS70286C-page 78 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 TABLE 6-1: RESET FLAG BIT OPERATION Flag Bit Setting Event Clearing Event TRAPR (RCON<15>) Trap conflict event POR, BOR IOPUWR (RCON<14>) Illegal opcode or uninitialized POR, BOR W register access EXTR (RCON<7>) MCLR Reset POR SWR (RCON<6>) RESET instruction POR, BOR WDTO (RCON<4>) WDT time-out PWRSAV instruction, POR, BOR SLEEP (RCON<3>) PWRSAV #SLEEP instruction POR, BOR IDLE (RCON<2>) PWRSAV #IDLE instruction POR, BOR BOR (RCON<1>) BOR, POR — POR (RCON<0>) POR — Note: All Reset flag bits may be set or cleared by the user software. 6.1 Clock Source Selection at Reset 6.2 Device Reset Times If clock switching is enabled, the system clock source at The Reset times for various types of device Reset are device Reset is chosen, as shown in Table6-2. If clock summarized in Table6-3. The system Reset signal, switching is disabled, the system clock source is always SYSRST, is released after the POR and PWRT delay selected according to the oscillator Configuration bits. times expire. Refer to Section9.0 “Oscillator Configuration” for The time at which the device actually begins to execute further details. code also depends on the system oscillator delays, which include the Oscillator Start-up Timer (OST) and TABLE 6-2: OSCILLATOR SELECTION VS the PLL lock time. The OST and PLL lock times occur TYPE OF RESET (CLOCK in parallel with the applicable SYSRST delay times. SWITCHING ENABLED) The FSCM delay determines the time at which the Reset Type Clock Source Determinant FSCM begins to monitor the system clock source after the SYSRST signal is released. POR Oscillator Configuration bits BOR (FNOSC<2:0>) MCLR COSC Control bits WDTR (OSCCON<14:12>) SWR © 2009 Microchip Technology Inc. DS70286C-page 79

dsPIC33FJXXXGPX06/X08/X10 TABLE 6-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS System Clock FSCM Reset Type Clock Source SYSRST Delay Notes Delay Delay POR EC, FRC, LPRC TPOR + TSTARTUP + TRST — — 1, 2, 3 ECPLL, FRCPLL TPOR + TSTARTUP + TRST TLOCK TFSCM 1, 2, 3, 5, 6 XT, HS, SOSC TPOR + TSTARTUP + TRST TOST TFSCM 1, 2, 3, 4, 6 XTPLL, HSPLL TPOR + TSTARTUP + TRST TOST + TLOCK TFSCM 1, 2, 3, 4, 5, 6 BOR EC, FRC, LPRC TSTARTUP + TRST — — 3 ECPLL, FRCPLL TSTARTUP + TRST TLOCK TFSCM 3, 5, 6 XT, HS, SOSC TSTARTUP + TRST TOST TFSCM 3, 4, 6 XTPLL, HSPLL TSTARTUP + TRST TOST + TLOCK TFSCM 3, 4, 5, 6 MCLR Any Clock TRST — — 3 WDT Any Clock TRST — — 3 Software Any Clock TRST — — 3 Illegal Opcode Any Clock TRST — — 3 Uninitialized W Any Clock TRST — — 3 Trap Conflict Any Clock TRST — — 3 Note 1: TPOR = Power-on Reset delay (10 μs nominal). 2: TSTARTUP = Conditional POR delay of 20μs nominal (if on-chip regulator is enabled) or 64ms nominal Power-up Timer delay (if regulator is disabled). TSTARTUP is also applied to all returns from powered-down states, including waking from Sleep mode, only if the regulator is enabled. 3: TRST = Internal state Reset time (20 μs nominal). 4: TOST = Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the oscillator clock to the system. 5: TLOCK = PLL lock time (20 μs nominal). 6: TFSCM = Fail-Safe Clock Monitor delay (100 μs nominal). 6.2.1 POR AND LONG OSCILLATOR 6.2.2.1 FSCM Delay for Crystal and PLL START-UP TIMES Clock Sources The oscillator start-up circuitry and its associated delay When the system clock source is provided by a crystal timers are not linked to the device Reset delays that oscillator and/or the PLL, a small delay, TFSCM, is auto- occur at power-up. Some crystal circuits (especially matically inserted after the POR and PWRT delay low-frequency crystals) have a relatively long start-up times. The FSCM does not begin to monitor the system time. Therefore, one or more of the following conditions clock source until this delay expires. The FSCM delay is possible after SYSRST is released: time is nominally 500 μs and provides additional time for the oscillator and/or PLL to stabilize. In most cases, • The oscillator circuit has not begun to oscillate. the FSCM delay prevents an oscillator failure trap at a • The Oscillator Start-up Timer has not expired (if a device Reset when the PWRT is disabled. crystal oscillator is used). • The PLL has not achieved a lock (if PLL is used). 6.3 Special Function Register Reset The device will not begin to execute code until a valid States clock source has been released to the system. Therefore, the oscillator and PLL start-up delays must Most of the Special Function Registers (SFRs) associ- be considered when the Reset delay time must be ated with the CPU and peripherals are reset to a known. particular value at a device Reset. The SFRs are grouped by their peripheral or CPU function and their 6.2.2 FAIL-SAFE CLOCK MONITOR Reset values are specified in each section of this manual. (FSCM) AND DEVICE RESETS The Reset value for each SFR does not depend on the If the FSCM is enabled, it begins to monitor the system type of Reset, with the exception of two registers. The clock source when SYSRST is released. If a valid clock Reset value for the Reset Control register, RCON, source is not available at this time, the device depends on the type of device Reset. The Reset value automatically switches to the FRC oscillator and the for the Oscillator Control register, OSCCON, depends user can switch to the desired crystal oscillator in the on the type of Reset and the programmed values of the Trap Service Routine. oscillator Configuration bits in the FOSC Configuration register. DS70286C-page 80 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 7.0 INTERRUPT CONTROLLER 7.1.1 ALTERNATE VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located Note: This data sheet summarizes the features after the IVT, as shown in Figure7-1. Access to the of the dsPIC33FJXXXGPX06/X08/X10 AIVT is provided by the ALTIVT control bit family of devices. However, it is not (INTCON2<15>). If the ALTIVT bit is set, all interrupt intended to be a comprehensive reference and exception processes use the alternate vectors source. To complement the information in instead of the default vectors. The alternate vectors are this data sheet, refer to Section 6. organized in the same manner as the default vectors. “Interrupts” (DS70184) in the “dsPIC33F Family Reference Manual”, which is avail- The AIVT supports debugging by providing a means to able from the Microchip web site switch between an application and a support (www.microchip.com). environment without requiring the interrupt vectors to be reprogrammed. This feature also enables switching The dsPIC33FJXXXGPX06/X08/X10 interrupt between applications for evaluation of different controller reduces the numerous peripheral interrupt software algorithms at run time. If the AIVT is not request signals to a single interrupt request signal to needed, the AIVT should be programmed with the the dsPIC33FJXXXGPX06/X08/X10 CPU. It has the same addresses used in the IVT. following features: • Up to 8 processor exceptions and software traps 7.2 Reset Sequence • 7 user-selectable priority levels A device Reset is not a true exception because the • Interrupt Vector Table (IVT) with up to 118 vectors interrupt controller is not involved in the Reset process. • A unique vector for each interrupt or exception The dsPIC33FJXXXGPX06/X08/X10 device clears its source registers in response to a Reset, which forces the PC • Fixed priority within a specified user priority level to zero. The digital signal controller then begins • Alternate Interrupt Vector Table (AIVT) for debug program execution at location 0x000000. The user support programs a GOTO instruction at the Reset address which redirects program execution to the appropriate • Fixed interrupt entry and return latencies start-up routine. 7.1 Interrupt Vector Table Note: Any unimplemented or unused vector locations in the IVT and AIVT should be The Interrupt Vector Table is shown in Figure7-1. The programmed with the address of a default IVT resides in program memory, starting at location interrupt handler routine that contains a 000004h. The IVT contains 126 vectors consisting of RESET instruction. 8nonmaskable trap vectors plus up to 118 sources of interrupt. In general, each interrupt source has its own vector. Each interrupt vector contains a 24-bit wide address. The value programmed into each interrupt vector location is the starting address of the associated Interrupt Service Routine (ISR). Interrupt vectors are prioritized in terms of their natural priority; this priority is linked to their position in the vector table. All other things being equal, lower addresses have a higher natural priority. For example, the interrupt associated with vector 0 will take priority over interrupts at any other vector address. dsPIC33FJXXXGPX06/X08/X10 devices implement up to 67 unique interrupts and 5 nonmaskable traps. These are summarized in Table7-1 and Table7-2. © 2009 Microchip Technology Inc. DS70286C-page 81

dsPIC33FJXXXGPX06/X08/X10 FIGURE 7-1: dsPIC33FJXXXGPX06/X08/X10 INTERRUPT VECTOR TABLE Reset – GOTO Instruction 0x000000 Reset – GOTO Address 0x000002 Reserved 0x000004 Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector DMA Error Trap Vector Reserved Reserved Interrupt Vector 0 0x000014 Interrupt Vector 1 ~ ~ ~ Interrupt Vector 52 0x00007C Interrupt Vector Table (IVT)(1) Interrupt Vector 53 0x00007E ority Interrupt ~Vector 54 0x000080 Pri ~ der ~ Or Interrupt Vector 116 0x0000FC al Interrupt Vector 117 0x0000FE atur Reserved 0x000100 N Reserved 0x000102 g n Reserved si a Oscillator Fail Trap Vector e cr Address Error Trap Vector e D Stack Error Trap Vector Math Error Trap Vector DMA Error Trap Vector Reserved Reserved Interrupt Vector 0 0x000114 Interrupt Vector 1 ~ ~ ~ Alternate Interrupt Vector Table (AIVT)(1) Interrupt Vector 52 0x00017C Interrupt Vector 53 0x00017E Interrupt Vector 54 0x000180 ~ ~ ~ Interrupt Vector 116 Interrupt Vector 117 0x0001FE Start of Code 0x000200 Note 1: See Table7-1 for the list of implemented interrupt vectors. DS70286C-page 82 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 TABLE 7-1: INTERRUPT VECTORS Interrupt Vector Request (IRQ) IVT Address AIVT Address Interrupt Source Number Number 8 0 0x000014 0x000114 INT0 – External Interrupt 0 9 1 0x000016 0x000116 IC1 – Input Compare 1 10 2 0x000018 0x000118 OC1 – Output Compare 1 11 3 0x00001A 0x00011A T1 – Timer1 12 4 0x00001C 0x00011C DMA0 – DMA Channel 0 13 5 0x00001E 0x00011E IC2 – Input Capture 2 14 6 0x000020 0x000120 OC2 – Output Compare 2 15 7 0x000022 0x000122 T2 – Timer2 16 8 0x000024 0x000124 T3 – Timer3 17 9 0x000026 0x000126 SPI1E – SPI1 Error 18 10 0x000028 0x000128 SPI1 – SPI1 Transfer Done 19 11 0x00002A 0x00012A U1RX – UART1 Receiver 20 12 0x00002C 0x00012C U1TX – UART1 Transmitter 21 13 0x00002E 0x00012E ADC1 – ADC 1 22 14 0x000030 0x000130 DMA1 – DMA Channel 1 23 15 0x000032 0x000132 Reserved 24 16 0x000034 0x000134 SI2C1 – I2C1 Slave Events 25 17 0x000036 0x000136 MI2C1 – I2C1 Master Events 26 18 0x000038 0x000138 Reserved 27 19 0x00003A 0x00013A Change Notification Interrupt 28 20 0x00003C 0x00013C INT1 – External Interrupt 1 29 21 0x00003E 0x00013E ADC2 – ADC 2 30 22 0x000040 0x000140 IC7 – Input Capture 7 31 23 0x000042 0x000142 IC8 – Input Capture 8 32 24 0x000044 0x000144 DMA2 – DMA Channel 2 33 25 0x000046 0x000146 OC3 – Output Compare 3 34 26 0x000048 0x000148 OC4 – Output Compare 4 35 27 0x00004A 0x00014A T4 – Timer4 36 28 0x00004C 0x00014C T5 – Timer5 37 29 0x00004E 0x00014E INT2 – External Interrupt 2 38 30 0x000050 0x000150 U2RX – UART2 Receiver 39 31 0x000052 0x000152 U2TX – UART2 Transmitter 40 32 0x000054 0x000154 SPI2E – SPI2 Error 41 33 0x000056 0x000156 SPI1 – SPI1 Transfer Done 42 34 0x000058 0x000158 C1RX – ECAN1 Receive Data Ready 43 35 0x00005A 0x00015A C1 – ECAN1 Event 44 36 0x00005C 0x00015C DMA3 – DMA Channel 3 45 37 0x00005E 0x00015E IC3 – Input Capture 3 46 38 0x000060 0x000160 IC4 – Input Capture 4 47 39 0x000062 0x000162 IC5 – Input Capture 5 48 40 0x000064 0x000164 IC6 – Input Capture 6 49 41 0x000066 0x000166 OC5 – Output Compare 5 50 42 0x000068 0x000168 OC6 – Output Compare 6 51 43 0x00006A 0x00016A OC7 – Output Compare 7 52 44 0x00006C 0x00016C OC8 – Output Compare 8 53 45 0x00006E 0x00016E Reserved © 2009 Microchip Technology Inc. DS70286C-page 83

dsPIC33FJXXXGPX06/X08/X10 TABLE 7-1: INTERRUPT VECTORS (CONTINUED) Interrupt Vector Request (IRQ) IVT Address AIVT Address Interrupt Source Number Number 54 46 0x000070 0x000170 DMA4 – DMA Channel 4 55 47 0x000072 0x000172 T6 – Timer6 56 48 0x000074 0x000174 T7 – Timer7 57 49 0x000076 0x000176 SI2C2 – I2C2 Slave Events 58 50 0x000078 0x000178 MI2C2 – I2C2 Master Events 59 51 0x00007A 0x00017A T8 – Timer8 60 52 0x00007C 0x00017C T9 – Timer9 61 53 0x00007E 0x00017E INT3 – External Interrupt 3 62 54 0x000080 0x000180 INT4 – External Interrupt 4 63 55 0x000082 0x000182 C2RX – ECAN2 Receive Data Ready 64 56 0x000084 0x000184 C2 – ECAN2 Event 65 57 0x000086 0x000186 Reserved 66 58 0x000088 0x000188 Reserved 67 59 0x00008A 0x00018A DCIE – DCI Error 68 60 0x00008C 0x00018C DCID – DCI Transfer Done 69 61 0x00008E 0x00018E DMA5 – DMA Channel 5 70 62 0x000090 0x000190 Reserved 71 63 0x000092 0x000192 Reserved 72 64 0x000094 0x000194 Reserved 73 65 0x000096 0x000196 U1E – UART1 Error 74 66 0x000098 0x000198 U2E – UART2 Error 75 67 0x00009A 0x00019A Reserved 76 68 0x00009C 0x00019C DMA6 – DMA Channel 6 77 69 0x00009E 0x00019E DMA7 – DMA Channel 7 78 70 0x0000A0 0x0001A0 C1TX – ECAN1 Transmit Data Request 79 71 0x0000A2 0x0001A2 C2TX – ECAN2 Transmit Data Request 80-125 72-117 0x0000A4-0x0000 0x0001A4-0x0001 Reserved FE FE TABLE 7-2: TRAP VECTORS Vector Number IVT Address AIVT Address Trap Source 0 0x000004 0x000104 Reserved 1 0x000006 0x000106 Oscillator Failure 2 0x000008 0x000108 Address Error 3 0x00000A 0x00010A Stack Error 4 0x00000C 0x00010C Math Error 5 0x00000E 0x00010E DMA Error Trap 6 0x000010 0x000110 Reserved 7 0x000012 0x000112 Reserved DS70286C-page 84 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 7.3 Interrupt Control and Status The IPC registers are used to set the interrupt priority Registers level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels. dsPIC33FJXXXGPX06/X08/X10 devices implement a The INTTREG register contains the associated total of 30 registers for the interrupt controller: interrupt vector number and the new CPU interrupt • INTCON1 priority level, which are latched into vector number • INTCON2 (VECNUM<6:0>) and Interrupt level (ILR<3:0>) bit • IFS0 through IFS4 fields in the INTTREG register. The new interrupt priority level is the priority of the pending interrupt. • IEC0 through IEC4 • IPC0 through IPC17 The interrupt sources are assigned to the IFSx, IECx and IPCx registers in the same sequence that they are • INTTREG listed in Table7-1. For example, the INT0 (External Global interrupt control functions are controlled from Interrupt 0) is shown as having vector number 8 and a INTCON1 and INTCON2. INTCON1 contains the natural order priority of 0. Thus, the INT0IF bit is found Interrupt Nesting Disable (NSTDIS) bit as well as the in IFS0<0>, the INT0IE bit in IEC0<0>, and the INT0IP control and status flags for the processor trap sources. bits in the first position of IPC0 (IPC0<2:0>). The INTCON2 register controls the external interrupt Although they are not specifically part of the interrupt request signal behavior and the use of the Alternate control hardware, two of the CPU Control registers Interrupt Vector Table. contain bits that control interrupt functionality. The CPU The IFS registers maintain all of the interrupt request STATUS register, SR, contains the IPL<2:0> bits flags. Each source of interrupt has a Status bit, which is (SR<7:5>). These bits indicate the current CPU set by the respective peripherals or external signal and interrupt priority level. The user can change the current is cleared via software. CPU priority level by writing to the IPL bits. The IEC registers maintain all of the interrupt enable The CORCON register contains the IPL3 bit which, bits. These control bits are used to individually enable together with IPL<2:0>, also indicates the current CPU interrupts from the peripherals or external signals. priority level. IPL3 is a read-only bit so that trap events cannot be masked by the user software. All Interrupt registers are described in Register7-1 through Register7-32, in the following pages. © 2009 Microchip Technology Inc. DS70286C-page 85

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 7-1: SR: CPU STATUS REGISTER(1) R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R -0 R/W-0 OA OB SA SB OAB SAB DA DC bit 15 bit 8 R/W-0(3) R/W-0(3) R/W-0(3) R-0 R/W-0 R/W-0 R/W-0 R/W-0 IPL2(2) IPL1(2) IPL0(2) RA N OV Z C bit 7 bit 0 Legend: C = Clear only bit R = Readable bit U = Unimplemented bit, read as ‘0’ S = Set only bit W = Writable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2) 111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) Note1: For complete register details, see Register 3-1: “SR: CPU STATUS REGISTER”. 2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3>=1. 3: The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15>) = 1. REGISTER 7-2: CORCON: CORE CONTROL REGISTER(1) U-0 U-0 U-0 R/W-0 R/W-0 R-0 R-0 R-0 — — — US EDT DL<2:0> bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0 SATA SATB SATDW ACCSAT IPL3(2) PSV RND IF bit 7 bit 0 Legend: C = Clear only bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set 0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’ bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(2) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less Note1: For complete register details, see Register 3-2: “CORCON: CORE CONTROL REGISTER”. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level. DS70286C-page 86 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled 0 = Interrupt nesting is enabled bit 14 OVAERR: Accumulator A Overflow Trap Flag bit 1 = Trap was caused by overflow of Accumulator A 0 = Trap was not caused by overflow of Accumulator A bit 13 OVBERR: Accumulator B Overflow Trap Flag bit 1 = Trap was caused by overflow of Accumulator B 0 = Trap was not caused by overflow of Accumulator B bit 12 COVAERR: Accumulator A Catastrophic Overflow Trap Flag bit 1 = Trap was caused by catastrophic overflow of Accumulator A 0 = Trap was not caused by catastrophic overflow of Accumulator A bit 11 COVBERR: Accumulator B Catastrophic Overflow Trap Flag bit 1 = Trap was caused by catastrophic overflow of Accumulator B 0 = Trap was not caused by catastrophic overflow of Accumulator B bit 10 OVATE: Accumulator A Overflow Trap Enable bit 1 = Trap overflow of Accumulator A 0 = Trap disabled bit 9 OVBTE: Accumulator B Overflow Trap Enable bit 1 = Trap overflow of Accumulator B 0 = Trap disabled bit 8 COVTE: Catastrophic Overflow Trap Enable bit 1 = Trap on catastrophic overflow of Accumulator A or B enabled 0 = Trap disabled bit 7 SFTACERR: Shift Accumulator Error Status bit 1 = Math error trap was caused by an invalid accumulator shift 0 = Math error trap was not caused by an invalid accumulator shift bit 6 DIV0ERR: Arithmetic Error Status bit 1 = Math error trap was caused by a divide by zero 0 = Math error trap was not caused by a divide by zero bit 5 DMACERR: DMA Controller Error Status bit 1 = DMA controller error trap has occurred 0 = DMA controller error trap has not occurred bit 4 MATHERR: Arithmetic Error Status bit 1 = Math error trap has occurred 0 = Math error trap has not occurred © 2009 Microchip Technology Inc. DS70286C-page 87

dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED) bit 3 ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred bit 2 STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ DS70286C-page 88 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 ALTIVT DISI — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT4EP INT3EP INT2EP INT1EP INT0EP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Use alternate vector table 0 = Use standard (default) vector table bit 14 DISI: DISI Instruction Status bit 1 = DISI instruction is active 0 = DISI instruction is not active bit 13-5 Unimplemented: Read as ‘0’ bit 4 INT4EP: External Interrupt 4 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 3 INT3EP: External Interrupt 3 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2009 Microchip Technology Inc. DS70286C-page 89

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T2IF OC2IF IC2IF DMA01IF T1IF OC1IF IC1IF INT0IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 DMA1IF: DMA Channel 1 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13 AD1IF: ADC1 Conversion Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12 U1TXIF: UART1 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 11 U1RXIF: UART1 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10 SPI1IF: SPI1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 SPI1EIF: SPI1 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8 T3IF: Timer3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7 T2IF: Timer2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6 OC2IF: Output Compare Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 IC2IF: Input Capture Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4 DMA01IF: DMA Channel 0 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70286C-page 90 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2009 Microchip Technology Inc. DS70286C-page 91

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA21IF bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 IC8IF IC7IF AD2IF INT1IF CNIF — MI2C1IF SI2C1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 U2TXIF: UART2 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 14 U2RXIF: UART2 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13 INT2IF: External Interrupt 2 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12 T5IF: Timer5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 11 T4IF: Timer4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10 OC4IF: Output Compare Channel 4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 OC3IF: Output Compare Channel 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8 DMA21IF: DMA Channel 2 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7 IC8IF: Input Capture Channel 8 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6 IC7IF: Input Capture Channel 7 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 AD2IF: ADC2 Conversion Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4 INT1IF: External Interrupt 1 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70286C-page 92 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 (CONTINUED) bit 3 CNIF: Input Change Notification Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 Unimplemented: Read as ‘0’ bit 1 MI2C1IF: I2C1 Master Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2009 Microchip Technology Inc. DS70286C-page 93

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 7-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T6IF DMA4IF — OC8IF OC7IF OC6IF OC5IF IC6IF bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IC5IF IC4IF IC3IF DMA3IF C1IF C1RXIF SPI2IF SPI2EIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 T6IF: Timer6 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 14 DMA4IF: DMA Channel 4 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13 Unimplemented: Read as ‘0’ bit 12 OC8IF: Output Compare Channel 8 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 11 OC7IF: Output Compare Channel 7 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10 OC6IF: Output Compare Channel 6 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 OC5IF: Output Compare Channel 5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8 IC6IF: Input Capture Channel 6 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7 IC5IF: Input Capture Channel 5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6 IC4IF: Input Capture Channel 4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 IC3IF: Input Capture Channel 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4 DMA3IF: DMA Channel 3 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 C1IF: ECAN1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70286C-page 94 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 (CONTINUED) bit 2 C1RXIF: ECAN1 Receive Data Ready Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 SPI2IF: SPI2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SPI2EIF: SPI2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2009 Microchip Technology Inc. DS70286C-page 95

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 7-8: IFS3: INTERRUPT FLAG STATUS REGISTER 3 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 — — DMA5IF DCIIF DCIEIF — — C2IF bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C2RXIF INT4IF INT3IF T9IF T8IF MI2C2IF SI2C2IF T7IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 DMA5IF: DMA Channel 5 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12 DCIIF: DCI Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 11 DCIEIF: DCI Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10-9 Unimplemented: Read as ‘0’ bit 8 C2IF: ECAN2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7 C2RXIF: ECAN2 Receive Data Ready Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6 INT4IF: External Interrupt 4 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 INT3IF: External Interrupt 3 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4 T9IF: Timer9 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 T8IF: Timer8 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 MI2C2IF: I2C2 Master Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 SI2C2IF: I2C2 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 T7IF: Timer7 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70286C-page 96 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 7-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 C2TXIF C1TXIF DMA7IF DMA6IF — U2EIF U1EIF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 C2TXIF: ECAN2 Transmit Data Request Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6 C1TXIF: ECAN1 Transmit Data Request Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 DMA7IF: DMA Channel 7 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4 DMA6IF: DMA Channel 6 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 Unimplemented: Read as ‘0’ bit 2 U2EIF: UART2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 U1EIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. DS70286C-page 97

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 7-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 DMA1IE: DMA Channel 1 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 13 AD1IE: ADC1 Conversion Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 12 U1TXIE: UART1 Transmitter Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 11 U1RXIE: UART1 Receiver Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 10 SPI1IE: SPI1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 9 SPI1EIE: SPI1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 8 T3IE: Timer3 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 7 T2IE: Timer2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 6 OC2IE: Output Compare Channel 2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 5 IC2IE: Input Capture Channel 2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 4 DMA0IE: DMA Channel 0 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 3 T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70286C-page 98 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2009 Microchip Technology Inc. DS70286C-page 99

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 7-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 IC8IE IC7IE AD2IE INT1IE CNIE — MI2C1IE SI2C1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 U2TXIE: UART2 Transmitter Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 14 U2RXIE: UART2 Receiver Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 13 INT2IE: External Interrupt 2 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 12 T5IE: Timer5 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 11 T4IE: Timer4 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 10 OC4IE: Output Compare Channel 4 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 9 OC3IE: Output Compare Channel 3 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 8 DMA2IE: DMA Channel 2 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 7 IC8IE: Input Capture Channel 8 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 6 IC7IE: Input Capture Channel 7 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 5 AD2IE: ADC2 Conversion Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 4 INT1IE: External Interrupt 1 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70286C-page 100 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 (CONTINUED) bit 3 CNIE: Input Change Notification Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 2 Unimplemented: Read as ‘0’ bit 1 MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2009 Microchip Technology Inc. DS70286C-page 101

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 7-12: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T6IE DMA4IE — OC8IE OC7IE OC6IE OC5IE IC6IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IC5IE IC4IE IC3IE DMA3IE C1IE C1RXIE SPI2IE SPI2EIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 T6IE: Timer6 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 14 DMA4IE: DMA Channel 4 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 13 Unimplemented: Read as ‘0’ bit 12 OC8IE: Output Compare Channel 8 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 11 OC7IE: Output Compare Channel 7 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 10 OC6IE: Output Compare Channel 6 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 9 OC5IE: Output Compare Channel 5 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 8 IC6IE: Input Capture Channel 6 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 7 IC5IE: Input Capture Channel 5 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 6 IC4IE: Input Capture Channel 4 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 5 IC3IE: Input Capture Channel 3 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 4 DMA3IE: DMA Channel 3 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 3 C1IE: ECAN1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70286C-page 102 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-12: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 (CONTINUED) bit 2 C1RXIE: ECAN1 Receive Data Ready Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SPI2EIE: SPI2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2009 Microchip Technology Inc. DS70286C-page 103

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 7-13: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 — — DMA5IE DCIIE DCIEIE — — C2IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C2RXIE INT4IE INT3IE T9IE T8IE MI2C2IE SI2C2IE T7IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 DMA5IE: DMA Channel 5 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 12 DCIIE: DCI Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 11 DCIEIE: DCI Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 10-9 Unimplemented: Read as ‘0’ bit 8 C2IE: ECAN2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 7 C2RXIE: ECAN2 Receive Data Ready Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 6 INT4IE: External Interrupt 4 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 5 INT3IE: External Interrupt 3 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 4 T9IE: Timer9 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 3 T8IE: Timer8 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 2 MI2C2IE: I2C2 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 SI2C2IE: I2C2 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 T7IE: Timer7 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70286C-page 104 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 7-14: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 C2TXIE C1TXIE DMA7IE DMA6IE — U2EIE U1EIE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 C2TXIE: ECAN2 Transmit Data Request Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 6 C1TXIE: ECAN1 Transmit Data Request Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 5 DMA7IE: DMA Channel 7 Data Transfer Complete Enable Status bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 4 DMA6IE: DMA Channel 6 Data Transfer Complete Enable Status bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 3 Unimplemented: Read as ‘0’ bit 2 U2EIE: UART2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. DS70286C-page 105

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 7-15: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T1IP<2:0> — OC1IP<2:0> bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC1IP<2:0> — INT0IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS70286C-page 106 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 7-16: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T2IP<2:0> — OC2IP<2:0> bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC2IP<2:0> — DMA0IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP<2:0>: Timer2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 DMA0IP<2:0>: DMA Channel 0 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. DS70286C-page 107

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 7-17: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U1RXIP<2:0> — SPI1IP<2:0> bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPI1EIP<2:0> — T3IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 SPI1IP<2:0>: SPI1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 SPI1EIP<2:0>: SPI1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS70286C-page 108 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 7-18: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — DMA1IP<2:0> bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — AD1IP<2:0> — U1TXIP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 DMA1IP<2:0>: DMA Channel 1 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 AD1IP<2:0>: ADC1 Conversion Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. DS70286C-page 109

dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-19: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — CNIP<2:0> — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — MI2C1IP<2:0> — SI2C1IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP<2:0>: Change Notification Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11-7 Unimplemented: Read as ‘0’ bit 6-4 MI2C1IP<2:0>: I2C1 Master Events Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 SI2C1IP<2:0>: I2C1 Slave Events Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS70286C-page 110 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 7-20: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC8IP<2:0> — IC7IP<2:0> bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — AD2IP<2:0> — INT1IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 IC8IP<2:0>: Input Capture Channel 8 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 IC7IP<2:0>: Input Capture Channel 7 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 AD2IP<2:0>: ADC2 Conversion Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. DS70286C-page 111

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 7-21: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T4IP<2:0> — OC4IP<2:0> bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — OC3IP<2:0> — DMA2IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T4IP<2:0>: Timer4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC4IP<2:0>: Output Compare Channel 4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 OC3IP<2:0>: Output Compare Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 DMA2IP<2:0>: DMA Channel 2 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS70286C-page 112 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 7-22: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U2TXIP<2:0> — U2RXIP<2:0> bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — INT2IP<2:0> — T5IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 U2TXIP<2:0>: UART2 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 U2RXIP<2:0>: UART2 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 INT2IP<2:0>: External Interrupt 2 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 T5IP<2:0>: Timer5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. DS70286C-page 113

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 7-23: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — C1IP<2:0> — C1RXIP<2:0> bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPI2IP<2:0> — SPI2EIP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 C1IP<2:0>: ECAN1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 C1RXIP<2:0>: ECAN1 Receive Data Ready Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 SPI2IP<2:0>: SPI2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 SPI2EIP<2:0>: SPI2 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS70286C-page 114 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 7-24: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC5IP<2:0> — IC4IP<2:0> bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC3IP<2:0> — DMA3IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 IC5IP<2:0>: Input Capture Channel 5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 IC4IP<2:0>: Input Capture Channel 4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC3IP<2:0>: Input Capture Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 DMA3IP<2:0>: DMA Channel 3 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. DS70286C-page 115

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 7-25: IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — OC7IP<2:0> — OC6IP<2:0> bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — OC5IP<2:0> — IC6IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 OC7IP<2:0>: Output Compare Channel 7 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC6IP<2:0>: Output Compare Channel 6 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 OC5IP<2:0>: Output Compare Channel 5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 IC6IP<2:0>: Input Capture Channel 6 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS70286C-page 116 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 7-26: IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T6IP<2:0> — DMA4IP<2:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — OC8IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T6IP<2:0>: Timer6 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 DMA4IP<2:0>: DMA Channel 4 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 OC8IP<2:0>: Output Compare Channel 8 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. DS70286C-page 117

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 7-27: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T8IP<2:0> — MI2C2IP<2:0> bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SI2C2IP<2:0> — T7IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T8IP<2:0>: Timer8 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 MI2C2IP<2:0>: I2C2 Master Events Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 SI2C2IP<2:0>: I2C2 Slave Events Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 T7IP<2:0>: Timer7 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS70286C-page 118 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 7-28: IPC13: INTERRUPT PRIORITY CONTROL REGISTER 13 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — C2RXIP<2:0> — INT4IP<2:0> bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — INT3IP<2:0> — T9IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 C2RXIP<2:0>: ECAN2 Receive Data Ready Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 INT4IP<2:0>: External Interrupt 4 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 INT3IP<2:0>: External Interrupt 3 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 T9IP<2:0>: Timer9 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. DS70286C-page 119

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 7-29: IPC14: INTERRUPT PRIORITY CONTROL REGISTER 14 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — DCIEIP<2:0> — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — C2IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 DCIEIP<2:0>: DCI Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11-3 Unimplemented: Read as ‘0’ bit 2-0 C2IP<2:0>: ECAN2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS70286C-page 120 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-30: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — DMA5IP<2:0> — DCIIP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 DMA5IP<2:0>: DMA Channel 5 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 DCIIP<2:0>: DCI Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. DS70286C-page 121

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 7-31: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — U2EIP<2:0> bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — U1EIP<2:0> — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 U2EIP<2:0>: UART2 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 U1EIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS70286C-page 122 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-32: IPC17: INTERRUPT PRIORITY CONTROL REGISTER 17 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — C2TXIP<2:0> — C1TXIP<2:0> bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — DMA7IP<2:0> — DMA6IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 C2TXIP<2:0>: ECAN2 Transmit Data Request Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 C1TXIP<2:0>: ECAN1 Transmit Data Request Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 DMA7IP<2:0>: DMA Channel 7 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 DMA6IP<2:0>: DMA Channel 6 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. DS70286C-page 123

dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-33: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — ILR<3:0> bit 15 bit 8 U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 — VECNUM<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 ILR<3:0>: New CPU Interrupt Priority Level bits 1111 = CPU Interrupt Priority Level is 15 • • • 0001 = CPU Interrupt Priority Level is 1 0000 = CPU Interrupt Priority Level is 0 bit 7 Unimplemented: Read as ‘0’ bit 6-0 VECNUM<6:0>: Vector Number of Pending Interrupt bits 0111111 = Interrupt Vector pending is number 135 • • • 0000001 = Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8 DS70286C-page 124 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 7.4 Interrupt Setup Procedures 7.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, 7.4.1 INITIALIZATION except that the appropriate trap status flag in the To configure an interrupt source: INTCON1 register must be cleared to avoid re-entry into the TSR. 1. Set the NSTDIS bit (INTCON1<15>) if nested interrupts are not desired. 7.4.4 INTERRUPT DISABLE 2. Select the user-assigned priority level for the interrupt source by writing the control bits in the All user interrupts can be disabled using the following appropriate IPCx register. The priority level will procedure: depend on the specific application and type of 1. Push the current SR value onto the software interrupt source. If multiple priority levels are not stack using the PUSH instruction. desired, the IPCx register control bits for all 2. Force the CPU to priority level 7 by inclusive enabled interrupt sources may be programmed ORing the value OEh with SRL. to the same non-zero value. To enable user interrupts, the POP instruction may be Note: At a device Reset, the IPCx registers are used to restore the previous SR value. initialized, such that all user interrupt Note that only user interrupts with a priority level of 7 or sources are assigned to priority level 4. less can be disabled. Trap sources (level 8-level 15) 3. Clear the interrupt flag status bit associated with cannot be disabled. the peripheral in the associated IFSx register. The DISI instruction provides a convenient way to 4. Enable the interrupt source by setting the disable interrupts of priority levels 1-6 for a fixed period interrupt enable control bit associated with the of time. Level 7 interrupt sources are not disabled by source in the appropriate IECx register. the DISI instruction. 7.4.2 INTERRUPT SERVICE ROUTINE The method that is used to declare an ISR and initialize the IVT with the correct vector address will depend on the programming language (i.e., C or assembler) and the language development toolsuite that is used to develop the application. In general, the user must clear the interrupt flag in the appropriate IFSx register for the source of interrupt that the ISR handles. Otherwise, the ISR will be re-entered immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. © 2009 Microchip Technology Inc. DS70286C-page 125

dsPIC33FJXXXGPX06/X08/X10 NOTES: DS70286C-page 126 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 8.0 DIRECT MEMORY ACCESS The DMA controller features eight identical data (DMA) transfer channels. Each channel has its own set of control and status Note: This data sheet summarizes the features registers. Each DMA channel can be configured to of the dsPIC33FJXXXGPX06/X08/X10 copy data either from buffers stored in dual port DMA family of devices. However, it is not RAM to peripheral SFRs, or from peripheral SFRs to intended to be a comprehensive reference buffers in DMA RAM. source. To complement the information in this data sheet, refer to Section 22. The DMA controller supports the following features: “Direct Memory Access (DMA)” • Word or byte sized data transfers. (DS70182) in the “dsPIC33F Family • Transfers from peripheral to DMA RAM or DMA Reference Manual”, which is available RAM to peripheral. from the Microchip web site • Indirect Addressing of DMA RAM locations with or (www.microchip.com). without automatic post-increment. Direct Memory Access (DMA) is a very efficient • Peripheral Indirect Addressing – In some mechanism of copying data between peripheral SFRs peripherals, the DMA RAM read/write addresses (e.g., UART Receive register, Input Capture 1 buffer), may be partially derived from the peripheral. and buffers or variables stored in RAM, with minimal • One-Shot Block Transfers – Terminating DMA CPU intervention. The DMA controller can transfer after one block transfer. automatically copy entire blocks of data without • Continuous Block Transfers – Reloading DMA requiring the user software to read or write the RAM buffer start address after every block peripheral Special Function Registers (SFRs) every transfer is complete. time a peripheral interrupt occurs. The DMA controller uses a dedicated bus for data transfers and therefore, • Ping-Pong Mode – Switching between two DMA does not steal cycles from the code execution flow of RAM start addresses between successive block the CPU. To exploit the DMA capability, the transfers, thereby filling two buffers alternately. corresponding user buffers or variables must be • Automatic or manual initiation of block transfers located in DMA RAM. • Each channel can select from 20 possible The dsPIC33FJXXXGPX06/X08/X10 peripherals that sources of data sources or destinations. can utilize DMA are listed in Table8-1 along with their For each DMA channel, a DMA interrupt request is associated Interrupt Request (IRQ) numbers. generated when a block transfer is complete. Alternatively, an interrupt can be generated when half of TABLE 8-1: PERIPHERALS WITH DMA the block has been filled. SUPPORT Peripheral IRQ Number INT0 0 Input Capture 1 1 Input Capture 2 5 Output Compare 1 2 Output Compare 2 6 Timer2 7 Timer3 8 SPI1 10 SPI2 33 UART1 Reception 11 UART1 Transmission 12 UART2 Reception 30 UART2 Transmission 31 ADC1 13 ADC2 21 DCI 60 ECAN1 Reception 34 ECAN1 Transmission 70 ECAN2 Reception 55 ECAN2 Transmission 71 © 2009 Microchip Technology Inc. DS70286C-page 127

dsPIC33FJXXXGPX06/X08/X10 FIGURE 8-1: TOP LEVEL SYSTEM ARCHITECTURE USING A DEDICATED TRANSACTION BUS Peripheral Indirect Address DMA Controller DMA SRAM DMA RAM MAntrol ChDaMnAnels PerRipehaedrayl 3 Do C PORT1 PORT2 CPU DMA SRAM X-Bus DMA DS Bus CPU Peripheral DS Bus CPU DMA CPU DMA Non-DMA DMA DMA CPU Ready Ready Ready Peripheral Peripheral 1 Peripheral 2 Note: CPU and DMA address buses are not shown for clarity. 8.1 DMAC Registers Each DMAC Channel x (x = 0, 1, 2, 3, 4, 5, 6 or 7) contains the following registers: • A 16-bit DMA Channel Control register (DMAxCON) • A 16-bit DMA Channel IRQ Select register (DMAxREQ) • A 16-bit DMA RAM Primary Start Address Offset register (DMAxSTA) • A 16-bit DMA RAM Secondary Start Address Offset register (DMAxSTB) • A 16-bit DMA Peripheral Address register (DMAxPAD) • A 10-bit DMA Transfer Count register (DMAxCNT) An additional pair of status registers, DMACS0 and DMACS1, are common to all DMAC channels. DS70286C-page 128 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 8-1: DMAxCON: DMA CHANNEL x CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 CHEN SIZE DIR HALF NULLW — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 — — AMODE<1:0> — — MODE<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CHEN: Channel Enable bit 1 = Channel enabled 0 = Channel disabled bit 14 SIZE: Data Transfer Size bit 1 = Byte 0 = Word bit 13 DIR: Transfer Direction bit (source/destination bus select) 1 = Read from DMA RAM address, write to peripheral address 0 = Read from peripheral address, write to DMA RAM address bit 12 HALF: Early Block Transfer Complete Interrupt Select bit 1 = Initiate block transfer complete interrupt when half of the data has been moved 0 = Initiate block transfer complete interrupt when all of the data has been moved bit 11 NULLW: Null Data Peripheral Write Mode Select bit 1 = Null data write to peripheral in addition to DMA RAM write (DIR bit must also be clear) 0 = Normal operation bit 10-6 Unimplemented: Read as ‘0’ bit 5-4 AMODE<1:0>: DMA Channel Operating Mode Select bits 11 = Reserved 10 = Peripheral Indirect Addressing mode 01 = Register Indirect without Post-Increment mode 00 = Register Indirect with Post-Increment mode bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 MODE<1:0>: DMA Channel Operating Mode Select bits 11 = One-Shot, Ping-Pong modes enabled (one block transfer from/to each DMA RAM buffer) 10 = Continuous, Ping-Pong modes enabled 01 = One-Shot, Ping-Pong modes disabled 00 = Continuous, Ping-Pong modes disabled © 2009 Microchip Technology Inc. DS70286C-page 129

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 8-2: DMAxREQ: DMA CHANNEL x IRQ SELECT REGISTER R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 FORCE(1) — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — IRQSEL6(2) IRQSEL5(2) IRQSEL4(2) IRQSEL3(2) IRQSEL2(2) IRQSEL1(2) IRQSEL0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FORCE: Force DMA Transfer bit(1) 1 = Force a single DMA transfer (Manual mode) 0 = Automatic DMA transfer initiation by DMA request bit 14-7 Unimplemented: Read as ‘0’ bit 6-0 IRQSEL<6:0>: DMA Peripheral IRQ Number Select bits(2) 0000000-1111111 = DMAIRQ0-DMAIRQ127 selected to be Channel DMAREQ Note1: The FORCE bit cannot be cleared by the user. The FORCE bit is cleared by hardware when the forced DMA transfer is complete. 2: Please see Table8-1 for a complete listing of IRQ numbers for all interrupt sources. DS70286C-page 130 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 8-3: DMAxSTA: DMA CHANNEL x RAM START ADDRESS OFFSET REGISTER A R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STA<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STA<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 STA<15:0>: Primary DMA RAM Start Address bits (source or destination) REGISTER 8-4: DMAxSTB: DMA CHANNEL x RAM START ADDRESS OFFSET REGISTER B R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STB<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STB<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 STB<15:0>: Secondary DMA RAM Start Address bits (source or destination) © 2009 Microchip Technology Inc. DS70286C-page 131

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 8-5: DMAxPAD: DMA CHANNEL x PERIPHERAL ADDRESS REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PAD<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PAD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PAD<15:0>: Peripheral Address Register bits Note1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the DMA channel and should be avoided. REGISTER 8-6: DMAxCNT: DMA CHANNEL x TRANSFER COUNT REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — CNT<9:8>(2) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CNT<7:0>(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 CNT<9:0>: DMA Transfer Count Register bits(2) Note1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the DMA channel and should be avoided. 2: Number of DMA transfers = CNT<9:0> + 1. DS70286C-page 132 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 8-7: DMACS0: DMA CONTROLLER STATUS REGISTER 0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 PWCOL7 PWCOL6 PWCOL5 PWCOL4 PWCOL3 PWCOL2 PWCOL1 PWCOL0 bit 15 bit 8 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 XWCOL7 XWCOL6 XWCOL5 XWCOL4 XWCOL3 XWCOL2 XWCOL1 XWCOL0 bit 7 bit 0 Legend: C = Clear only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PWCOL7: Channel 7 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 14 PWCOL6: Channel 6 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 13 PWCOL5: Channel 5 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 12 PWCOL4: Channel 4 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 11 PWCOL3: Channel 3 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 10 PWCOL2: Channel 2 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 9 PWCOL1: Channel 1 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 8 PWCOL0: Channel 0 Peripheral Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 7 XWCOL7: Channel 7 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 6 XWCOL6: Channel 6 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 5 XWCOL5: Channel 5 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 4 XWCOL4: Channel 4 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected © 2009 Microchip Technology Inc. DS70286C-page 133

dsPIC33FJXXXGPX06/X08/X10 REGISTER 8-7: DMACS0: DMA CONTROLLER STATUS REGISTER 0 (CONTINUED) bit 3 XWCOL3: Channel 3 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 2 XWCOL2: Channel 2 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 1 XWCOL1: Channel 1 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 0 XWCOL0: Channel 0 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected DS70286C-page 134 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 8-8: DMACS1: DMA CONTROLLER STATUS REGISTER 1 U-0 U-0 U-0 U-0 R-1 R-1 R-1 R-1 — — — — LSTCH<3:0> bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 LSTCH<3:0>: Last DMA Channel Active bits 1111 = No DMA transfer has occurred since system Reset 1110-1000 = Reserved 0111 = Last data transfer was by DMA Channel 7 0110 = Last data transfer was by DMA Channel 6 0101 = Last data transfer was by DMA Channel 5 0100 = Last data transfer was by DMA Channel 4 0011 = Last data transfer was by DMA Channel 3 0010 = Last data transfer was by DMA Channel 2 0001 = Last data transfer was by DMA Channel 1 0000 = Last data transfer was by DMA Channel 0 bit 7 PPST7: Channel 7 Ping-Pong Mode Status Flag bit 1 = DMA7STB register selected 0 = DMA7STA register selected bit 6 PPST6: Channel 6 Ping-Pong Mode Status Flag bit 1 = DMA6STB register selected 0 = DMA6STA register selected bit 5 PPST5: Channel 5 Ping-Pong Mode Status Flag bit 1 = DMA5STB register selected 0 = DMA5STA register selected bit 4 PPST4: Channel 4 Ping-Pong Mode Status Flag bit 1 = DMA4STB register selected 0 = DMA4STA register selected bit 3 PPST3: Channel 3 Ping-Pong Mode Status Flag bit 1 = DMA3STB register selected 0 = DMA3STA register selected bit 2 PPST2: Channel 2 Ping-Pong Mode Status Flag bit 1 = DMA2STB register selected 0 = DMA2STA register selected bit 1 PPST1: Channel 1 Ping-Pong Mode Status Flag bit 1 = DMA1STB register selected 0 = DMA1STA register selected bit 0 PPST0: Channel 0 Ping-Pong Mode Status Flag bit 1 = DMA0STB register selected 0 = DMA0STA register selected © 2009 Microchip Technology Inc. DS70286C-page 135

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 8-9: DSADR: MOST RECENT DMA RAM ADDRESS R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DSADR<15:8> bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DSADR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 DSADR<15:0>: Most Recent DMA RAM Address Accessed by DMA Controller bits DS70286C-page 136 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 9.0 OSCILLATOR • An on-chip PLL to scale the internal operating CONFIGURATION frequency to the required system clock frequency • The internal FRC oscillator can also be used with Note: This data sheet summarizes the features the PLL, thereby allowing full-speed operation of the dsPIC33FJXXXGPX06/X08/X10 without any external clock generation hardware family of devices. However, it is not • Clock switching between various clock sources intended to be a comprehensive reference • Programmable clock postscaler for system power source. To complement the information in savings this data sheet, refer to Section 7. • A Fail-Safe Clock Monitor (FSCM) that detects “Oscillator” (DS70186) in the “dsPIC33F clock failure and takes fail-safe measures Family Reference Manual”, which is • A Clock Control register (OSCCON) available from the Microchip web site (www.microchip.com). • Nonvolatile Configuration bits for main oscillator selection. The dsPIC33FJXXXGPX06/X08/X10 oscillator system A simplified diagram of the oscillator system is shown provides: in Figure9-1. • Various external and internal oscillator options as clock sources FIGURE 9-1: dsPIC33FJXXXGPX06/X08/X10 OSCILLATOR SYSTEM DIAGRAM dsPIC33F Primary Oscillator OSC1 XT, HS, EC DOZE<2:0> S2 R(2) S3 XTPLL, HSPLL, S1 PLL(1) ECPLL, FRCPLL S1/S3 ZE FCY O OSC2 D POSCMD<1:0> FP ÷ 2 OsFcRillCator CDIV FRCDIVN S7 FOSC R F FRCDIV<2:0> TUN<5:0> FRCDIV16 S6 ÷ 16 FRC S0 LPRC LPRC S5 Oscillator Secondary Oscillator SOSC SOSCO S4 LPOSCEN SOSCI Clock Fail Clock Switch Reset S7 NOSC<2:0> FNOSC<2:0> WDT, PWRT, FSCM Timer 1 Note 1: See Figure9-2 for PLL details. 2: If the Oscillator is used with XT or HS modes, an extended parallel resistor with the value of 1 MΩ must be connected. © 2009 Microchip Technology Inc. DS70286C-page 137

dsPIC33FJXXXGPX06/X08/X10 9.1 CPU Clocking System Oscillator Mode Select Configuration bits, POSCMD<1:0> (FOSC<1:0>), select the oscillator There are seven system clock options provided by the source that is used at a Power-on Reset. The FRC dsPIC33FJXXXGPX06/X08/X10: primary oscillator is the default (unprogrammed) • FRC Oscillator selection. • FRC Oscillator with PLL The Configuration bits allow users to choose between • Primary (XT, HS or EC) Oscillator twelve different clock modes, shown in Table9-1. • Primary Oscillator with PLL The output of the oscillator (or the output of the PLL if • Secondary (LP) Oscillator a PLL mode has been selected) FOSC is divided by 2 to • LPRC Oscillator generate the device instruction clock (FCY) and the peripheral clock time base (FP). FCY defines the • FRC Oscillator with postscaler operating speed of the device, and speeds up to 40 9.1.1 SYSTEM CLOCK SOURCES MHz are supported by the dsPIC33FJXXXGPX06/X08/X10 architecture. The FRC (Fast RC) internal oscillator runs at a nominal frequency of 7.37 MHz. The user software can tune the Instruction execution speed or device operating FRC frequency. User software can optionally specify a frequency, FCY, is given by: factor (ranging from 1:2 to 1:256) by which the FRC EQUATION 9-1: DEVICE OPERATING clock frequency is divided. This factor is selected using FREQUENCY the FRCDIV<2:0> (CLKDIV<10:8>) bits. The primary oscillator can use one of the following as FOSC FCY = ------------- its clock source: 2 1. XT (Crystal): Crystals and ceramic resonators in the range of 3 MHz to 10 MHz. The crystal is 9.1.3 PLL CONFIGURATION connected to the OSC1 and OSC2 pins. The primary oscillator and internal FRC oscillator can 2. HS (High-Speed Crystal): Crystals in the range optionally use an on-chip PLL to obtain higher speeds of 10 MHz to 40 MHz. The crystal is connected of operation. The PLL provides a significant amount of to the OSC1 and OSC2 pins. flexibility in selecting the device operating speed. A 3. EC (External Clock): External clock signal is block diagram of the PLL is shown in Figure9-2. directly applied to the OSC1 pin. The output of the primary oscillator or FRC, denoted as The secondary (LP) oscillator is designed for low power ‘FIN’, is divided down by a prescale factor (N1) of 2, 3, and uses a 32.768 kHz crystal or ceramic resonator. ... or 33 before being provided to the PLL’s Voltage The LP oscillator uses the SOSCI and SOSCO pins. Controlled Oscillator (VCO). The input to the VCO must be selected to be in the range of 0.8 MHz to 8 MHz. The LPRC (Low-Power RC) internal oscillator runs at a Since the minimum prescale factor is 2, this implies that nominal frequency of 32.768 kHz. It is also used as a reference clock by the Watchdog Timer (WDT) and FIN must be chosen to be in the range of 1.6 MHz to 16 MHz. The prescale factor ‘N1’ is selected using the Fail-Safe Clock Monitor (FSCM). PLLPRE<4:0> bits (CLKDIV<4:0>). The clock signals generated by the FRC and primary The PLL Feedback Divisor, selected using the oscillators can be optionally applied to an on-chip PLLDIV<8:0> bits (PLLFBD<8:0>), provides a factor ‘M’, Phase Locked Loop (PLL) to provide a wide range of by which the input to the VCO is multiplied. This factor output frequencies for device operation. PLL must be selected such that the resulting VCO output configuration is described in Section9.1.3 “PLL frequency is in the range of 100 MHz to 200 MHz. Configuration”. The VCO output is further divided by a postscale factor The FRC frequency depends on the FRC accuracy ‘N2’. This factor is selected using the PLLPOST<1:0> (see Table25-19) and the value of the FRC Oscillator bits (CLKDIV<7:6>). ‘N2’ can be either 2, 4 or 8, and Tuning register (see Register9-4). must be selected such that the PLL output frequency 9.1.2 SYSTEM CLOCK SELECTION (FOSC) is in the range of 12.5 MHz to 80 MHz, which generates device operating speeds of 6.25-40 MIPS. The oscillator source that is used at a device Power-on Reset event is selected using Configuration bit settings. For a primary oscillator or FRC oscillator, output ‘FIN’, The oscillator Configuration bit settings are located in the the PLL output ‘FOSC’ is given by: Configuration registers in the program memory. (Refer to Section22.1 “Configuration Bits” for further details.) EQUATION 9-2: FOSC CALCULATION The Initial Oscillator Selection Configuration bits, FNOSC<2:0> (FOSCSEL<2:0>), and the Primary FOSC = FIN⋅⎝⎛N-----1---M-⋅---N-----2--⎠⎞ DS70286C-page 138 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 For example, suppose a 10 MHz crystal is being used, EQUATION 9-3: XT WITH PLL MODE with “XT with PLL” being the selected oscillator mode. EXAMPLE If PLLPRE<4:0> = 0, then N1 = 2. This yields a VCO irnapnugte o of f 100.8/2- 8= M 5H Mz.H Ifz ,P wLLhDicIhV <is8 :w0i>th =in 0 txh1eE a, cthceenp table FCY = F----O--2--S---C-- = 12---⎝⎛1---0---0---0----02---0-⋅-0--2-0-----⋅---3---2--⎠⎞ = 40 MIPS M = 32. This yields a VCO output of 5 x 32 = 160 MHz, which is within the 100-200 MHz range needed. If PLLPOST<1:0> = 0, then N2 = 2. This provides a Fosc of 160/2 = 80 MHz. The resultant device operating speed is 80/2 = 40 MIPS. FIGURE 9-2: dsPIC33FJXXXGPX06/X08/X10 PLL BLOCK DIAGRAM FVCO 0.8-8.0 MHz 12.5-80 MHz Here(1) 100H-2e0re0( 1M)Hz Here(1) Source (Crystal, External Clock or Internal RC) PLLPRE X VCO PLLPOST FOSC PLLDIV N1 N2 Divide by Divide by 2-33 M 2, 4, 8 Divide by 2-513 Note1: This frequency range must be satisfied at all times. TABLE 9-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION Oscillator Mode Oscillator Source POSCMD<1:0> FNOSC<2:0> Note Fast RC Oscillator with Divide-by-N Internal xx 111 1, 2 (FRCDIVN) Fast RC Oscillator with Divide-by-16 Internal xx 110 1 (FRCDIV16) Low-Power RC Oscillator (LPRC) Internal xx 101 1 Secondary (Timer1) Oscillator (SOSC) Secondary xx 100 1 Primary Oscillator (HS) with PLL Primary 10 011 — (HSPLL) Primary Oscillator (XT) with PLL Primary 01 011 — (XTPLL) Primary Oscillator (EC) with PLL Primary 00 011 1 (ECPLL) Primary Oscillator (HS) Primary 10 010 — Primary Oscillator (XT) Primary 01 010 — Primary Oscillator (EC) Primary 00 010 1 Fast RC Oscillator with PLL (FRCPLL) Internal xx 001 1 Fast RC Oscillator (FRC) Internal xx 000 1 Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit. 2: This is the default oscillator mode for an unprogrammed (erased) device. © 2009 Microchip Technology Inc. DS70286C-page 139

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER(1) U-0 R-0 R-0 R-0 U-0 R/W-y R/W-y R/W-y — COSC<2:0> — NOSC<2:0>(2) bit 15 bit 8 R/W-0 U-0 R-0 U-0 R/C-0 U-0 R/W-0 R/W-0 CLKLOCK — LOCK — CF — LPOSCEN OSWEN bit 7 bit 0 Legend: y = Value set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 COSC<2:0>: Current Oscillator Selection bits (read-only) 000 = Fast RC oscillator (FRC) 001 = Fast RC oscillator (FRC) with PLL 010 = Primary oscillator (XT, HS, EC) 011 = Primary oscillator (XT, HS, EC) with PLL 100 = Secondary oscillator (SOSC) 101 = Low-Power RC oscillator (LPRC) 110 = Fast RC oscillator (FRC) with Divide-by-16 111 = Fast RC oscillator (FRC) with Divide-by-n bit 11 Unimplemented: Read as ‘0’ bit 10-8 NOSC<2:0>: New Oscillator Selection bits(2) 000 = Fast RC oscillator (FRC) 001 = Fast RC oscillator (FRC) with PLL 010 = Primary oscillator (XT, HS, EC) 011 = Primary oscillator (XT, HS, EC) with PLL 100 = Secondary oscillator (SOSC) 101 = Low-Power RC oscillator (LPRC) 110 = Fast RC oscillator (FRC) with Divide-by-16 111 = Fast RC oscillator (FRC) with Divide-by-n bit 7 CLKLOCK: Clock Lock Enable bit 1 = If (FCKSM0=1), then clock and PLL configurations are locked If (FCKSM0=0), then clock and PLL configurations may be modified 0 = Clock and PLL selections are not locked, configurations may be modified bit 6 Unimplemented: Read as ‘0’ bit 5 LOCK: PLL Lock Status bit (read-only) 1 = Indicates that PLL is in lock, or PLL start-up timer is satisfied 0 = Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled bit 4 Unimplemented: Read as ‘0’ bit 3 CF: Clock Fail Detect bit (read/clear by application) 1 = FSCM has detected clock failure 0 = FSCM has not detected clock failure bit 2 Unimplemented: Read as ‘0’ Note1: Writes to this register require an unlock sequence. Refer to Section 7. “Oscillator” (DS70186) in the “dsPIC33F Family Reference Manual” (available from the Microchip website) for details. 2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. DS70286C-page 140 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER(1) (CONTINUED) bit 1 LPOSCEN: Secondary (LP) Oscillator Enable bit 1 = Enable secondary oscillator 0 = Disable secondary oscillator bit 0 OSWEN: Oscillator Switch Enable bit 1 = Request oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete Note1: Writes to this register require an unlock sequence. Refer to Section 7. “Oscillator” (DS70186) in the “dsPIC33F Family Reference Manual” (available from the Microchip website) for details. 2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. © 2009 Microchip Technology Inc. DS70286C-page 141

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 9-2: CLKDIV: CLOCK DIVISOR REGISTER R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 ROI DOZE<2:0> DOZEN(1) FRCDIV<2:0> bit 15 bit 8 R/W-0 R/W-1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PLLPOST<1:0> — PLLPRE<4:0> bit 7 bit 0 Legend: y = Value set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROI: Recover on Interrupt bit 1 = Interrupts will clear the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1 0 = Interrupts have no effect on the DOZEN bit bit 14-12 DOZE<2:0>: Processor Clock Reduction Select bits 000 = FCY/1 001 = FCY/2 010 = FCY/4 011 = FCY/8 (default) 100 = FCY/16 101 = FCY/32 110 = FCY/64 111 = FCY/128 bit 11 DOZEN: DOZE Mode Enable bit(1) 1 = DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks 0 = Processor clock/peripheral clock ratio forced to 1:1 bit 10-8 FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits 000 = FRC divide by 1 (default) 001 = FRC divide by 2 010 = FRC divide by 4 011 = FRC divide by 8 100 = FRC divide by 16 101 = FRC divide by 32 110 = FRC divide by 64 111 = FRC divide by 256 bit 7-6 PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as ‘N2’, PLL postscaler) 00 = Output/2 01 = Output/4 (default) 10 = Reserved 11 = Output/8 bit 5 Unimplemented: Read as ‘0’ bit 4-0 PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as ‘N1’, PLL prescaler) 00000 = Input/2 (default) 00001 = Input/3 • • • 11111 = Input/33 Note1: This bit is cleared when the ROI bit is set and an interrupt occurs. DS70286C-page 142 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 9-3: PLLFBD: PLL FEEDBACK DIVISOR REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0(1) — — — — — — — PLLDIV<8> bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 PLLDIV<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8-0 PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier) 000000000 = 2 000000001 = 3 000000010 = 4 • • • 000110000 = 50 (default) • • • 111111111 = 513 © 2009 Microchip Technology Inc. DS70286C-page 143

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 9-4: OSCTUN: FRC OSCILLATOR TUNING REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — TUN<5:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits(1) 011111 = Center frequency + 11.625% (8.23 MHz) 011110 = Center frequency + 11.25% (8.20 MHz) • • • 000001 = Center frequency + 0.375% (7.40 MHz) 000000 = Center frequency (7.37 MHz nominal) 111111 = Center frequency - 0.375% (7.345 MHz) • • • 100001 = Center frequency - 11.625% (6.52 MHz) 100000 = Center frequency - 12% (6.49 MHz) Note1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither characterized nor tested. DS70286C-page 144 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 9.2 Clock Switching Operation 2. If a valid clock switch has been initiated, the LOCK (OSCCON<5>) and the CF Applications are free to switch between any of the four (OSCCON<3>) status bits are cleared. clock sources (Primary, LP, FRC and LPRC) under 3. The new oscillator is turned on by the hardware software control at any time. To limit the possible side if it is not currently running. If a crystal oscillator effects that could result from this flexibility, must be turned on, the hardware waits until the dsPIC33FJXXXGPX06/X08/X10 devices have a Oscillator Start-up Timer (OST) expires. If the safeguard lock built into the switch process. new source is using the PLL, the hardware waits Note: Primary Oscillator mode has three different until a PLL lock is detected (LOCK = 1). submodes (XT, HS and EC) which are 4. The hardware waits for 10 clock cycles from the determined by the POSCMD<1:0> new clock source and then performs the clock Configuration bits. While an application switch. can switch to and from Primary Oscillator 5. The hardware clears the OSWEN bit to indicate a mode in software, it cannot switch successful clock transition. In addition, the NOSC between the different primary submodes bit values are transferred to the COSC status bits. without reprogramming the device. 6. The old clock source is turned off at this time, 9.2.1 ENABLING CLOCK SWITCHING with the exception of LPRC (if WDT or FSCM are enabled) or LP (if LPOSCEN remains set). To enable clock switching, the FCKSM1 Configuration bit in the Configuration register must be programmed to Note1: The processor continues to execute code ‘0’. (Refer to Section22.1 “Configuration Bits” for throughout the clock switching sequence. further details.) If the FCKSM1 Configuration bit is Timing sensitive code should not be unprogrammed (‘1’), the clock switching function and executed during this time. Fail-Safe Clock Monitor function are disabled. This is 2: Direct clock switches between any primary the default setting. oscillator mode with PLL and FRCPLL The NOSC control bits (OSCCON<10:8>) do not mode are not permitted. This applies to control the clock selection when clock switching is clock switches in either direction. In these disabled. However, the COSC bits (OSCCON<14:12>) instances, the application must switch to reflect the clock source selected by the FNOSC FRC mode as a transition clock source Configuration bits. between the two PLL modes. 3: Refer to Section 7. “Oscillator” The OSWEN control bit (OSCCON<0>) has no effect (DS70186) in the “dsPIC33F Family when clock switching is disabled. It is held at ‘0’ at all Reference Manual” for details. times. 9.2.2 OSCILLATOR SWITCHING SEQUENCE 9.3 Fail-Safe Clock Monitor (FSCM) At a minimum, performing a clock switch requires this The Fail-Safe Clock Monitor (FSCM) allows the device basic sequence: to continue to operate even in the event of an oscillator 1. If desired, read the COSC bits failure. The FSCM function is enabled by programming. (OSCCON<14:12>) to determine the current If the FSCM function is enabled, the LPRC internal oscillator source. oscillator runs at all times (except during Sleep mode) 2. Perform the unlock sequence to allow a write to and is not subject to control by the Watchdog Timer. the OSCCON register high byte. In the event of an oscillator failure, the FSCM 3. Write the appropriate value to the NOSC control generates a clock failure trap event and switches the bits (OSCCON<10:8>) for the new oscillator system clock over to the FRC oscillator. Then the source. application program can either attempt to restart the 4. Perform the unlock sequence to allow a write to oscillator or execute a controlled shutdown. The trap the OSCCON register low byte. can be treated as a warm Reset by simply loading the 5. Set the OSWEN bit to initiate the oscillator Reset address into the oscillator fail trap vector. switch. If the PLL multiplier is used to scale the system clock, Once the basic sequence is completed, the system the internal FRC is also multiplied by the same factor clock hardware responds automatically as follows: on clock failure. Essentially, the device switches to FRC with PLL on a clock failure. 1. The clock switching hardware compares the COSC status bits with the new value of the NOSC control bits. If they are the same, then the clock switch is a redundant operation. In this case, the OSWEN bit is cleared automatically and the clock switch is aborted. © 2009 Microchip Technology Inc. DS70286C-page 145

dsPIC33FJXXXGPX06/X08/X10 NOTES: DS70286C-page 146 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 10.0 POWER-SAVING FEATURES 10.2 Instruction-Based Power-Saving Modes Note: This data sheet summarizes the features of the dsPIC33FJXXXGPX06/X08/X10 dsPIC33FJXXXGPX06/X08/X10 devices have two family of devices. However, it is not special power-saving modes that are entered through intended to be a comprehensive reference the execution of a special PWRSAV instruction. Sleep source. To complement the information in mode stops clock operation and halts all code this data sheet, refer to Section 9. execution. Idle mode halts the CPU and code “Watchdog Timer and Power-Saving execution, but allows peripheral modules to continue Modes” (DS70196) in the “dsPIC33F operation. The assembly syntax of the PWRSAV Family Reference Manual”, which is avail- instruction is shown in Example10-1. able from the Microchip web site Note: SLEEP_MODE and IDLE_MODE are (www.microchip.com). constants defined in the assembler The dsPIC33FJXXXGPX06/X08/X10 devices provide include file for the selected device. the ability to manage power consumption by selectively Sleep and Idle modes can be exited as a result of an managing clocking to the CPU and the peripherals. In enabled interrupt, WDT time-out or a device Reset. When general, a lower clock frequency and a reduction in the the device exits these modes, it is said to “wake-up”. number of circuits being clocked constitutes lower consumed power. dsPIC33FJXXXGPX06/X08/X10 10.2.1 SLEEP MODE devices can manage power consumption in four Sleep mode has these features: different ways: • The system clock source is shut down. If an • Clock frequency on-chip oscillator is used, it is turned off. • Instruction-based Sleep and Idle modes • The device current consumption is reduced to a • Software-controlled Doze mode minimum, provided that no I/O pin is sourcing • Selective peripheral control in software current. Combinations of these methods can be used to • The Fail-Safe Clock Monitor does not operate selectively tailor an application’s power consumption during Sleep mode since the system clock source while still maintaining critical application features, such is disabled. as timing-sensitive communications. • The LPRC clock continues to run in Sleep mode if the WDT is enabled. 10.1 Clock Frequency and Clock • The WDT, if enabled, is automatically cleared Switching prior to entering Sleep mode. • Some device features or peripherals may continue dsPIC33FJXXXGPX06/X08/X10 devices allow a wide to operate in Sleep mode. This includes items such range of clock frequencies to be selected under as the input change notification on the I/O ports, or application control. If the system clock configuration is peripherals that use an external clock input. Any not locked, users can choose low-power or peripheral that requires the system clock source for high-precision oscillators by simply changing the its operation is disabled in Sleep mode. NOSC bits (OSCCON<10:8>). The process of changing a system clock during operation, as well as The device will wake-up from Sleep mode on any of limitations to the process, are discussed in more detail these events: in Section9.0 “Oscillator Configuration”. • Any interrupt source that is individually enabled. • Any form of device Reset. • A WDT time-out. On wake-up from Sleep, the processor restarts with the same clock source that was active when Sleep mode was entered. EXAMPLE 10-1: PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode © 2009 Microchip Technology Inc. DS70286C-page 147

dsPIC33FJXXXGPX06/X08/X10 10.2.2 IDLE MODE Doze mode is enabled by setting the DOZEN bit (CLK- DIV<11>). The ratio between peripheral and core clock Idle mode has these features: speed is determined by the DOZE<2:0> bits (CLK- • The CPU stops executing instructions. DIV<14:12>). There are eight possible configurations, • The WDT is automatically cleared. from 1:1 to 1:128, with 1:1 being the default setting. • The system clock source remains active. By It is also possible to use Doze mode to selectively default, all peripheral modules continue to operate reduce power consumption in event-driven normally from the system clock source, but can applications. This allows clock-sensitive functions, also be selectively disabled (see Section10.4 such as synchronous communications, to continue “Peripheral Module Disable”). without interruption while the CPU idles, waiting for • If the WDT or FSCM is enabled, the LPRC also something to invoke an interrupt routine. Enabling the remains active. automatic return to full-speed CPU operation on interrupts is enabled by setting the ROI bit (CLK- The device will wake from Idle mode on any of these DIV<15>). By default, interrupt events have no effect events: on Doze mode operation. • Any interrupt that is individually enabled. For example, suppose the device is operating at • Any device Reset. 20MIPS and the CAN module has been configured for • A WDT time-out. 500 kbps based on this device operating speed. If the On wake-up from Idle, the clock is reapplied to the CPU device is now placed in Doze mode with a clock and instruction execution begins immediately, starting frequency ratio of 1:4, the CAN module continues to with the instruction following the PWRSAV instruction, or communicate at the required bit rate of 500 kbps, but the first instruction in the ISR. the CPU now starts executing instructions at a frequency of 5 MIPS. 10.2.3 INTERRUPTS COINCIDENT WITH POWER SAVE INSTRUCTIONS 10.4 Peripheral Module Disable Any interrupt that coincides with the execution of a The Peripheral Module Disable (PMD) registers PWRSAV instruction is held off until entry into Sleep or provide a method to disable a peripheral module by Idle mode has completed. The device then wakes up stopping all clock sources supplied to that module. from Sleep or Idle mode. When a peripheral is disabled via the appropriate PMD control bit, the peripheral is in a minimum power 10.3 Doze Mode consumption state. The control and status registers associated with the peripheral are also disabled, so Generally, changing clock speed and invoking one of the writes to those registers will have no effect and read power-saving modes are the preferred strategies for values will be invalid. reducing power consumption. There may be circumstances, however, where this is not practical. For A peripheral module is only enabled if both the example, it may be necessary for an application to associated bit in the PMD register is cleared and the maintain uninterrupted synchronous communication, peripheral is supported by the specific dsPIC® DSC even while it is doing nothing else. Reducing system variant. If the peripheral is present in the device, it is clock speed may introduce communication errors, while enabled in the PMD register by default. using a power-saving mode may stop communications Note: If a PMD bit is set, the corresponding completely. module is disabled after a delay of 1 Doze mode is a simple and effective alternative method instruction cycle. Similarly, if a PMD bit is to reduce power consumption while the device is still cleared, the corresponding module is executing code. In this mode, the system clock enabled after a delay of 1 instruction cycle continues to operate from the same source and at the (assuming the module control registers same speed. Peripheral modules continue to be are already configured to enable module clocked at the same speed, while the CPU clock speed operation). is reduced. Synchronization between the two clock domains is maintained, allowing the peripherals to access the SFRs while the CPU executes code at a slower rate. DS70286C-page 148 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 T5MD T4MD T3MD T2MD T1MD — — DCIMD bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 I2C1MD U2MD U1MD SPI2MD SPI1MD C2MD C1MD AD1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 T5MD: Timer5 Module Disable bit 1 = Timer5 module is disabled 0 = Timer5 module is enabled bit 14 T4MD: Timer4 Module Disable bit 1 = Timer4 module is disabled 0 = Timer4 module is enabled bit 13 T3MD: Timer3 Module Disable bit 1 = Timer3 module is disabled 0 = Timer3 module is enabled bit 12 T2MD: Timer2 Module Disable bit 1 = Timer2 module is disabled 0 = Timer2 module is enabled bit 11 T1MD: Timer1 Module Disable bit 1 = Timer1 module is disabled 0 = Timer1 module is enabled bit 10-9 Unimplemented: Read as ‘0’ bit 8 DCIMD: DCI Module Disable bit 1 = DCI module is disabled 0 = DCI module is enabled bit 7 I2C1MD: I2C1 Module Disable bit 1 = I2C1 module is disabled 0 = I2C1 module is enabled bit 6 U2MD: UART2 Module Disable bit 1 = UART2 module is disabled 0 = UART2 module is enabled bit 5 U1MD: UART1 Module Disable bit 1 = UART1 module is disabled 0 = UART1 module is enabled bit 4 SPI2MD: SPI2 Module Disable bit 1 = SPI2 module is disabled 0 = SPI2 module is enabled bit 3 SPI1MD: SPI1 Module Disable bit 1 = SPI1 module is disabled 0 = SPI1 module is enabled bit 2 C2MD: ECAN2 Module Disable bit 1 = ECAN2 module is disabled 0 = ECAN2 module is enabled © 2009 Microchip Technology Inc. DS70286C-page 149

dsPIC33FJXXXGPX06/X08/X10 REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 (CONTINUED) bit 1 C1MD: ECAN2 Module Disable bit 1 = ECAN1 module is disabled 0 = ECAN1 module is enabled bit 0 AD1MD: ADC1 Module Disable bit 1 = ADC1 module is disabled 0 = ADC1 module is enabled DS70286C-page 150 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 REGISTER 10-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IC8MD IC7MD IC6MD IC5MD IC4MD IC3MD IC2MD IC1MD bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OC8MD OC7MD OC6MD OC5MD OC4MD OC3MD OC2MD OC1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IC8MD: Input Capture 8 Module Disable bit 1 = Input Capture 8 module is disabled 0 = Input Capture 8 module is enabled bit 14 IC7MD: Input Capture 7 Module Disable bit 1 = Input Capture 7 module is disabled 0 = Input Capture 7 module is enabled bit 13 IC6MD: Input Capture 6 Module Disable bit 1 = Input Capture 6 module is disabled 0 = Input Capture 6 module is enabled bit 12 IC5MD: Input Capture 5 Module Disable bit 1 = Input Capture 5 module is disabled 0 = Input Capture 5 module is enabled bit 11 IC4MD: Input Capture 4 Module Disable bit 1 = Input Capture 4 module is disabled 0 = Input Capture 4 module is enabled bit 10 IC3MD: Input Capture 3 Module Disable bit 1 = Input Capture 3 module is disabled 0 = Input Capture 3 module is enabled bit 9 IC2MD: Input Capture 2 Module Disable bit 1 = Input Capture 2 module is disabled 0 = Input Capture 2 module is enabled bit 8 IC1MD: Input Capture 1 Module Disable bit 1 = Input Capture 1 module is disabled 0 = Input Capture 1 module is enabled bit 7 OC8MD: Output Compare 8 Module Disable bit 1 = Output Compare 8 module is disabled 0 = Output Compare 8 module is enabled bit 6 OC7MD: Output Compare 4 Module Disable bit 1 = Output Compare 7 module is disabled 0 = Output Compare 7 module is enabled bit 5 OC6MD: Output Compare 6 Module Disable bit 1 = Output Compare 6 module is disabled 0 = Output Compare 6 module is enabled bit 4 OC5MD: Output Compare 5 Module Disable bit 1 = Output Compare 5 module is disabled 0 = Output Compare 5 module is enabled © 2009 Microchip Technology Inc. DS70286C-page 151

dsPIC33FJXXXGPX06/X08/X10 REGISTER 10-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2 (CONTINUED) bit 3 OC4MD: Output Compare 4 Module Disable bit 1 = Output Compare 4 module is disabled 0 = Output Compare 4 module is enabled bit 2 OC3MD: Output Compare 3 Module Disable bit 1 = Output Compare 3 module is disabled 0 = Output Compare 3 module is enabled bit 1 OC2MD: Output Compare 2 Module Disable bit 1 = Output Compare 2 module is disabled 0 = Output Compare 2 module is enabled bit 0 OC1MD: Output Compare 1 Module Disable bit 1 = Output Compare 1 module is disabled 0 = Output Compare 1 module is enabled DS70286C-page 152 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 REGISTER 10-3: PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 T9MD T8MD T7MD T6MD — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — I2C2MD AD2MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 T9MD: Timer9 Module Disable bit 1 = Timer9 module is disabled 0 = Timer9 module is enabled bit 14 T8MD: Timer8 Module Disable bit 1 = Timer8 module is disabled 0 = Timer8 module is enabled bit 13 T7MD: Timer7 Module Disable bit 1 = Timer7 module is disabled 0 = Timer7 module is enabled bit 12 T6MD: Timer6 Module Disable bit 1 = Timer6 module is disabled 0 = Timer6 module is enabled bit 11-2 Unimplemented: Read as ‘0’ bit 1 I2C2MD: I2C2 Module Disable bit 1 = I2C2 module is disabled 0 = I2C2 module is enabled bit 0 AD2MD: AD2 Module Disable bit 1 = AD2 module is disabled 0 = AD2 module is enabled © 2009 Microchip Technology Inc. DS70286C-page 153

dsPIC33FJXXXGPX06/X08/X10 NOTES: DS70286C-page 154 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 11.0 I/O PORTS When a peripheral is enabled and actively driving an associated pin, the use of the pin as a general purpose Note: This data sheet summarizes the features output pin is disabled. The I/O pin may be read, but the of the dsPIC33FJXXXGPX06/X08/X10 output driver for the parallel port bit will be disabled. If family of devices. However, it is not a peripheral is enabled, but the peripheral is not intended to be a comprehensive reference actively driving a pin, that pin may be driven by a port. source. To complement the information in All port pins have three registers directly associated this data sheet, refer to Section 10. “I/O with their operation as digital I/O. The data direction Ports” (DS70193) in the “dsPIC33F register (TRISx) determines whether the pin is an input Family Reference Manual”, which is avail- or an output. If the data direction bit is a ‘1’, then the pin able from the Microchip web site is an input. All port pins are defined as inputs after a (www.microchip.com). Reset. Reads from the latch (LATx), read the latch. All of the device pins (except VDD, VSS, MCLR and Writes to the latch, write the latch. Reads from the port OSC1/CLKIN) are shared between the peripherals and (PORTx), read the port pins, while writes to the port the parallel I/O ports. All I/O input ports feature Schmitt pins, write the latch. Trigger inputs for improved noise immunity. Any bit and its associated data and control registers that are not valid for a particular device will be 11.1 Parallel I/O (PIO) Ports disabled. That means the corresponding LATx and A parallel I/O port that shares a pin with a peripheral is, TRISx registers and the port pins will read as zeros. in general, subservient to the peripheral. The When a pin is shared with another peripheral or peripheral’s output buffer data and control signals are function that is defined as an input only, it is provided to a pair of multiplexers. The multiplexers nevertheless regarded as a dedicated port because select whether the peripheral or the associated port there is no other competing source of outputs. An has ownership of the output data and control signals of example is the INT4 pin. the I/O pin. The logic also prevents “loop through”, in which a port’s digital output can drive the input of a Note: The voltage on a digital input pin can be peripheral that shares the same pin. Figure11-1 illus- between -0.3V to 5.6V. trates how ports are shared with other peripherals and the associated I/O pin to which they are connected. FIGURE 11-1: BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE Peripheral Module Output Multiplexers Peripheral Input Data Peripheral Module Enable I/O Peripheral Output Enable 1 Output Enable Peripheral Output Data 0 PIO Module 1 Output Data Read TRIS 0 Data Bus D Q I/O Pin WR TRIS CK TRIS Latch D Q WR LAT + WR PORT CK Data Latch Read LAT Input Data Read Port © 2009 Microchip Technology Inc. DS70286C-page 155

dsPIC33FJXXXGPX06/X08/X10 11.2 Open-Drain Configuration 11.4 I/O Port Write/Read Timing In addition to the PORT, LAT and TRIS registers for One instruction cycle is required between a port data control, some port pins can also be individually direction change or port write operation and a read configured for either digital or open-drain output. This is operation of the same port. Typically, this instruction controlled by the Open-Drain Control register, ODCx, would be a NOP. associated with each port. Setting any of the bits configures the corresponding pin to act as an 11.5 Input Change Notification open-drain output. The input change notification function of the I/O ports The open-drain feature allows the generation of allows the dsPIC33FJXXXGPX06/X08/X10 devices to outputs higher than VDD (e.g., 5V) on any desired generate interrupt requests to the processor in digital only pins by using external pull-up resistors. The response to a change-of-state on selected input pins. maximum open-drain voltage allowed is the same as This feature is capable of detecting input the maximum VIH specification. change-of-states even in Sleep mode, when the clocks See “Pin Diagrams” for the available pins and their are disabled. Depending on the device pin count, there functionality. are up to 24 external signals (CN0 through CN23) that can be selected (enabled) for generating an interrupt 11.3 Configuring Analog Port Pins request on a change-of-state. There are four control registers associated with the CN The use of the ADxPCFGH, ADxPCFGL and TRIS module. The CNEN1 and CNEN2 registers contain the registers control the operation of the ADC port pins. CN interrupt enable (CNxIE) control bits for each of the The port pins that are desired as analog inputs must CN input pins. Setting any of these bits enables a CN have their corresponding TRIS bit set (input). If the interrupt for the corresponding pins. TRIS bit is cleared (output), the digital output level (VOH or VOL) is converted. Each CN pin also has a weak pull-up connected to it. The pull-ups act as a current source that is connected Clearing any bit in the ADxPCFGH or ADxPCFGL to the pin and eliminate the need for external resistors register configures the corresponding bit to be an when push button or keypad devices are connected. analog pin. This is also the Reset state of any I/O pin The pull-ups are enabled separately using the CNPU1 that has an analog (ANx) function associated with it. and CNPU2 registers, which contain the weak pull-up Note: In devices with two ADC modules, if the enable (CNxPUE) bits for each of the CN pins. Setting corresponding PCFG bit in either any of the control bits enables the weak pull-ups for the AD1PCFGH(L) and AD2PCFGH(L) is corresponding pins. cleared, the pin is configured as an analog Note: Pull-ups on change notification pins input. should always be disabled whenever the When reading the PORT register, all pins configured as port pin is configured as a digital output. analog input channels will read as cleared (a low level). Pins configured as digital inputs will not convert an analog input. Analog levels on any pin that is defined as a digital input (including the ANx pins) can cause the input buffer to consume current that exceeds the device specifications. Note: The voltage on an analog input pin can be between -0.3V to (VDD + 0.3 V). EXAMPLE 11-1: PORT WRITE/READ EXAMPLE MOV 0xFF00, W0 ; Configure PORTB<15:8> as inputs MOV W0, TRISBB ; and PORTB<7:0> as outputs NOP ; Delay 1 cycle btss PORTB, #13 ; Next Instruction DS70286C-page 156 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 12.0 TIMER1 Timer1 also supports these features: • Timer gate operation Note: This data sheet summarizes the features • Selectable prescaler settings of the dsPIC33FJXXXGPX06/X08/X10 family of devices. However, it is not • Timer operation during CPU Idle and Sleep intended to be a comprehensive reference modes source. To complement the information in • Interrupt on 16-bit Period register match or falling this data sheet, refer to Section 11. edge of external gate signal “Timers” (DS70205) in the “dsPIC33F Figure12-1 presents a block diagram of the 16-bit Family Reference Manual”, which is timer module. available from the Microchip web site To configure Timer1 for operation: (www.microchip.com). 1. Set the TON bit (= 1) in the T1CON register. The Timer1 module is a 16-bit timer, which can serve 2. Select the timer prescaler ratio using the as the time counter for the real-time clock, or operate TCKPS<1:0> bits in the T1CON register. as a free-running interval timer/counter. Timer1 can operate in three modes: 3. Set the Clock and Gating modes using the TCS and TGATE bits in the T1CON register. • 16-bit Timer 4. Set or clear the TSYNC bit in T1CON to select • 16-bit Synchronous Counter synchronous or asynchronous operation. • 16-bit Asynchronous Counter 5. Load the timer period value into the PR1 register. 6. If interrupts are required, set the interrupt enable bit, T1IE. Use the priority bits, T1IP<2:0>, to set the interrupt priority. FIGURE 12-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM TCKPS<1:0> TON 2 SOSCO/ 1x T1CK Gate Prescaler SOSCEN Sync 01 1, 8, 64, 256 SOSCI TCY 00 TGATE TGATE TCS 1 Q D Set T1IF 0 Q CK 0 Reset TMR1 1 Sync Comparator TSYNC Equal PR1 © 2009 Microchip Technology Inc. DS70286C-page 157

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 — TGATE TCKPS<1:0> — TSYNC TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timer1 Gated Time Accumulation Enable bit When T1CS = 1: This bit is ignored. When T1CS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled bit 5-4 TCKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 Unimplemented: Read as ‘0’ bit 2 TSYNC: Timer1 External Clock Input Synchronization Select bit When TCS = 1: 1 = Synchronize external clock input 0 = Do not synchronize external clock input When TCS = 0: This bit is ignored. bit 1 TCS: Timer1 Clock Source Select bit 1 = External clock from pin T1CK (on the rising edge) 0 = Internal clock (FCY) bit 0 Unimplemented: Read as ‘0’ DS70286C-page 158 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 13.0 TIMER2/3, TIMER4/5, TIMER6/7 AND TIMER8/9 Note: For 32-bit operation, T3CON, T5CON, T7CON and T9CON control bits are Note: This data sheet summarizes the features ignored. Only T2CON, T4CON, T6CON of the dsPIC33FJXXXGPX06/X08/X10 and T8CON control bits are used for setup family of devices. However, it is not and control. Timer2, Timer4, Timer6 and intended to be a comprehensive reference Timer8 clock and gate inputs are utilized source. To complement the information in for the 32-bit timer modules, but an this data sheet, refer to Section 11. interrupt is generated with the Timer3, “Timers” (DS70205) in the “dsPIC33F Timer5, Ttimer7 and Timer9 interrupt Family Reference Manual”, which is flags. available from the Microchip web site To configure Timer2/3, Timer4/5, Timer6/7 or Timer8/9 (www.microchip.com). for 32-bit operation: The Timer2/3, Timer4/5, Timer6/7 and Timer8/9 1. Set the corresponding T32 control bit. modules are 32-bit timers, which can also be 2. Select the prescaler ratio for Timer2, Timer4, configured as four independent 16-bit timers with Timer6 or Timer8 using the TCKPS<1:0> bits. selectable operating modes. 3. Set the Clock and Gating modes using the As a 32-bit timer, Timer2/3, Timer4/5, Timer6/7 and corresponding TCS and TGATE bits. Timer8/9 operate in three modes: 4. Load the timer period value. PR3, PR5, PR7 or • Two Independent 16-bit Timers (e.g., Timer2 and PR9 contains the most significant word of the Timer3) with all 16-bit operating modes (except value, while PR2, PR4, PR6 or PR8 contains the Asynchronous Counter mode) least significant word. • Single 32-bit Timer 5. If interrupts are required, set the interrupt enable • Single 32-bit Synchronous Counter bit, T3IE, T5IE, T7IE or T9IE. Use the priority They also support these features: bits, T3IP<2:0>, T5IP<2:0>, T7IP<2:0> or T9IP<2:0>, to set the interrupt priority. While • Timer Gate Operation Timer2, Timer4, Timer6 or Timer8 control the • Selectable Prescaler Settings timer, the interrupt appears as a Timer3, Timer5, • Timer Operation during Idle and Sleep modes Timer7 or Timer9 interrupt. • Interrupt on a 32-bit Period Register Match 6. Set the corresponding TON bit. • Time Base for Input Capture and Output Compare The timer value at any point is stored in the register Modules (Timer2 and Timer3 only) pair, TMR3:TMR2, TMR5:TMR4, TMR7:TMR6 or • ADC1 Event Trigger (Timer2/3 only) TMR9:TMR8. TMR3, TMR5, TMR7 or TMR9 always • ADC2 Event Trigger (Timer4/5 only) contains the most significant word of the count, while TMR2, TMR4, TMR6 or TMR8 contains the least Individually, all eight of the 16-bit timers can function as significant word. synchronous timers or counters. They also offer the features listed above, except for the event trigger; this To configure any of the timers for individual 16-bit is implemented only with Timer2/3. The operating operation: modes and enabled features are determined by setting 1. Clear the T32 bit corresponding to that timer. the appropriate bit(s) in the T2CON, T3CON, T4CON, 2. Select the timer prescaler ratio using the T5CON, T6CON, T7CON, T8CON and T9CON TCKPS<1:0> bits. registers. T2CON, T4CON, T6CON and T8CON are 3. Set the Clock and Gating modes using the TCS shown in generic form in Register13-1. T3CON, and TGATE bits. T5CON, T7CON and T9CON are shown in Register13-2. 4. Load the timer period value into the PRx register. For 32-bit timer/counter operation, Timer2, Timer4, 5. If interrupts are required, set the interrupt enable Timer6 or Timer8 is the least significant word; Timer3, bit, TxIE. Use the priority bits, TxIP<2:0>, to set Timer5, Timer7 or Timer9 is the most significant word the interrupt priority. of the 32-bit timers. 6. Set the TON bit. A block diagram for a 32-bit timer pair (Timer4/5) example is shown in Figure13-1 and a timer (Timer4) operating in 16-bit mode example is shown in Figure13-2. Note: Only Timer2 and Timer3 can trigger a DMA data transfer. © 2009 Microchip Technology Inc. DS70286C-page 159

dsPIC33FJXXXGPX06/X08/X10 FIGURE 13-1: TIMER2/3 (32-BIT) BLOCK DIAGRAM(1) TCKPS<1:0> TON 2 T2CK 1x Gate Prescaler Sync 01 1, 8, 64, 256 TCY 00 TGATE TGATE TCS 1 Q D Set T3IF Q CK 0 PR3 PR2 ADC Event Trigger(2) Equal Comparator MSb LSb TMR3 TMR2 Sync Reset 16 Read TMR2 Write TMR2 16 16 TMR3HLD 16 Data Bus<15:0> Note 1: The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register. 2: The ADC event trigger is available only on Timer2/3. DS70286C-page 160 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 FIGURE 13-2: TIMER2 (16-BIT) BLOCK DIAGRAM TCKPS<1:0> TON 2 T2CK 1x Gate Prescaler Sync 01 1, 8, 64, 256 00 TGATE TCY TCS 1 Q D TGATE Set T2IF Q CK 0 Reset TMR2 Sync Comparator Equal PR2 © 2009 Microchip Technology Inc. DS70286C-page 161

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 13-1: TxCON (T2CON, T4CON, T6CON OR T8CON) CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 — TGATE TCKPS<1:0> T32 — TCS(1) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timerx On bit When T32 = 1: 1 = Starts 32-bit Timerx/y 0 = Stops 32-bit Timerx/y When T32 = 0: 1 = Starts 16-bit Timerx 0 = Stops 16-bit Timerx bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timerx Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled bit 5-4 TCKPS<1:0>: Timerx Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 T32: 32-bit Timer Mode Select bit 1 = Timerx and Timery form a single 32-bit timer 0 = Timerx and Timery act as two 16-bit timers bit 2 Unimplemented: Read as ‘0’ bit 1 TCS: Timerx Clock Source Select bit(1) 1 = External clock from pin TxCK (on the rising edge) 0 = Internal clock (FCY) bit 0 Unimplemented: Read as ‘0’ Note1: The TxCK pin is not available on all timers. Refer to the “Pin Diagrams” section for the available pins. DS70286C-page 162 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 13-2: TyCON (T3CON, T5CON, T7CON OR T9CON) CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON(1) — TSIDL(2) — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 — TGATE(1) TCKPS<1:0>(1) — — TCS(1,3) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timery On bit(1) 1 = Starts 16-bit Timery 0 = Stops 16-bit Timery bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Stop in Idle Mode bit(2) 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timery Gated Time Accumulation Enable bit(1) When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled bit 5-4 TCKPS<1:0>: Timer3 Input Clock Prescale Select bits(1) 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3-2 Unimplemented: Read as ‘0’ bit 1 TCS: Timery Clock Source Select bit(1,3) 1 = External clock from pin TyCK (on the rising edge) 0 = Internal clock (FCY) bit 0 Unimplemented: Read as ‘0’ Note1: When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timery operation; all timer functions are set through T2CON. 2: When 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (TxCON<3>), the TSIDL bit must be cleared to operate the 32-bit timer in Idle mode. 3: The TyCK pin is not available on all timers. Refer to the “Pin Diagrams” section for the available pins. © 2009 Microchip Technology Inc. DS70286C-page 163

dsPIC33FJXXXGPX06/X08/X10 NOTES: DS70286C-page 164 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 14.0 INPUT CAPTURE 2. Capture timer value on every edge (rising and falling) Note: This data sheet summarizes the features 3. Prescaler Capture Event modes of the dsPIC33FJXXXGPX06/X08/X10 -Capture timer value on every 4th rising edge family of devices. However, it is not of input at ICx pin intended to be a comprehensive reference -Capture timer value on every 16th rising source. To complement the information in edge of input at ICx pin this data sheet, refer to Section 12. “Input Capture” (DS70198) in the Each input capture channel can select between one of “dsPIC33F Family Reference Manual”, two 16-bit timers (Timer2 or Timer3) for the time base. which is available from the Microchip web The selected timer can use either an internal or site (www.microchip.com). external clock. The input capture module is useful in applications Other operational features include: requiring frequency (period) and pulse measurement. • Device wake-up from capture pin during CPU The dsPIC33FJXXXGPX06/X08/X10 devices support Sleep and Idle modes up to eight input capture channels. • Interrupt on input capture event The input capture module captures the 16-bit value of • 4-word FIFO buffer for capture values the selected Time Base register when an event occurs - Interrupt optionally generated after 1, 2, 3 or at the ICx pin. The events that cause a capture event 4 buffer locations are filled are listed below in three categories: • Input capture can also be used to provide 1. Simple Capture Event modes additional sources of external interrupts -Capture timer value on every falling edge of Note: Only IC1 and IC2 can trigger a DMA data input at ICx pin transfer. If DMA data transfers are -Capture timer value on every rising edge of required, the FIFO buffer size must be set input at ICx pin to 1 (ICI<1:0> = 00). FIGURE 14-1: INPUT CAPTURE BLOCK DIAGRAM From 16-bit Timers TMRy TMRz 16 16 ICTMR 1 0 (ICxCON<7>) Prescaler Edge Detection Logic FIFO Counter and R/W (1, 4, 16) Clock Synchronizer Logic ICx Pin ICM<2:0> (ICxCON<2:0>) 3 Mode Select O F ICOV, ICBNE (ICxCON<4:3>) FI ICxBUF ICxI<1:0> Interrupt ICxCON Logic System Bus Set Flag ICxIF (in IFSn Register) Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel. © 2009 Microchip Technology Inc. DS70286C-page 165

dsPIC33FJXXXGPX06/X08/X10 14.1 Input Capture Registers REGISTER 14-1: ICxCON: INPUT CAPTURE x CONTROL REGISTER U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — ICSIDL — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-0, HC R-0, HC R/W-0 R/W-0 R/W-0 ICTMR(1) ICI<1:0> ICOV ICBNE ICM<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 ICSIDL: Input Capture Module Stop in Idle Control bit 1 = Input capture module will halt in CPU Idle mode 0 = Input capture module will continue to operate in CPU Idle mode bit 12-8 Unimplemented: Read as ‘0’ bit 7 ICTMR: Input Capture Timer Select bits(1) 1 = TMR2 contents are captured on capture event 0 = TMR3 contents are captured on capture event bit 6-5 ICI<1:0>: Select Number of Captures per Interrupt bits 11 = Interrupt on every fourth capture event 10 = Interrupt on every third capture event 01 = Interrupt on every second capture event 00 = Interrupt on every capture event bit 4 ICOV: Input Capture Overflow Status Flag bit (read-only) 1 = Input capture overflow occurred 0 = No input capture overflow occurred bit 3 ICBNE: Input Capture Buffer Empty Status bit (read-only) 1 = Input capture buffer is not empty, at least one more capture value can be read 0 = Input capture buffer is empty bit 2-0 ICM<2:0>: Input Capture Mode Select bits 111 = Input capture functions as interrupt pin only when device is in Sleep or Idle mode (Rising edge detect only, all other control bits are not applicable.) 110 = Unused (module disabled) 101 = Capture mode, every 16th rising edge 100 = Capture mode, every 4th rising edge 011 = Capture mode, every rising edge 010 = Capture mode, every falling edge 001 = Capture mode, every edge (rising and falling) (ICI<1:0> bits do not control interrupt generation for this mode.) 000 = Input capture module turned off Note1: Timer selections may vary. Refer to the device data sheet for details. DS70286C-page 166 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 15.0 OUTPUT COMPARE The state of the output pin changes when the timer value matches the Compare register value. The output Note: This data sheet summarizes the features compare module generates either a single output of the dsPIC33FJXXXGPX06/X08/X10 pulse, or a sequence of output pulses, by changing the families of devices. It is not intended to be state of the output pin on the compare match events. a comprehensive reference source. To The output compare module can also generate complement the information in this data interrupts on compare match events. sheet, refer to Section 13. “Output The output compare module has multiple operating Compare” (DS70209) in the “dsPIC33F modes: Family Reference Manual”,, which is avail- able on the Microchip web site • Active-Low One-Shot mode (www.microchip.com). • Active-High One-Shot mode • Toggle mode The output compare module can select either Timer2 or • Delayed One-Shot mode Timer3 for its time base. The module compares the • Continuous Pulse mode value of the timer with the value of one or two Compare • PWM mode without Fault Protection registers depending on the operating mode selected. • PWM mode with Fault Protection FIGURE 15-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM Set Flag bit OCxIF(1) OCxRS(1) OCxR(1) Output S Q OCx(1) Logic R Output Enable 3 OCM<2:0> Mode Select OCFA Comparator or OCFB(2) 0 1 OCTSEL 0 1 16 16 TMR2 TMR3 TMR2 TMR3 Rollover Rollover Note 1: An ‘x’ in a signal, register or bit name denotes the number of the output compare channels. 2: The OCFA pin controls OC1 through OC4. The OCFB pin controls OC5 through OC8. © 2009 Microchip Technology Inc. DS70286C-page 167

dsPIC33FJXXXGPX06/X08/X10 15.1 Output Compare Modes application must disable the associated timer when writing to the Output Compare Control registers to Configure the Output Compare modes by setting the avoid malfunctions. appropriate Output Compare Mode (OCM<2:0>) bits in the Output Compare Control (OCxCON<2:0>) register. Note: See Section 13. “Output Compare” Table15-1 lists the different bit settings for the Output (DS70209) in the “dsPIC33F Family Ref- Compare modes. Figure15-2 illustrates the output erence Manual” for OCxR and OCxRS compare operation for various modes. The user register restrictions. TABLE 15-1: OUTPUT COMPARE MODES OCM<2:0> Mode OCx Pin Initial State OCx Interrupt Generation 000 Module Disabled Controlled by GPIO register — 001 Active-Low One-Shot 0 OCx rising edge 010 Active-High One-Shot 1 OCx falling edge 011 Toggle Current output is maintained OCx rising and falling edge 100 Delayed One-Shot 0 OCx falling edge 101 Continuous Pulse 0 OCx falling edge 110 PWM without Fault Protection ‘0’, if OCxR is zero No interrupt ‘1’, if OCxR is non-zero 111 PWM with Fault Protection ‘0’, if OCxR is zero OCFA falling edge for OC1 to OC4 ‘1’, if OCxR is non-zero FIGURE 15-2: OUTPUT COMPARE OPERATION Output Compare Timer is Reset on Mode Enabled Period Match OCxRS TMRy OCxR Active-Low One-Shot (OCM = 001) Active-High One-Shot (OCM = 010) Toggle (OCM = 011) Delayed One-Shot (OCM = 100) Continuous Pulse (OCM = 101) PWM (OCM = 110 or 111) DS70286C-page 168 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 REGISTER 15-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER (x = 1, 2) U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — OCSIDL — — — — — bit 15 bit 8 U-0 U-0 U-0 R-0, HC R/W-0 R/W-0 R/W-0 R/W-0 — — — OCFLT OCTSEL OCM<2:0> bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 OCSIDL: Stop Output Compare in Idle Mode Control bit 1 = Output Compare x halts in CPU Idle mode 0 = Output Compare x continues to operate in CPU Idle mode bit 12-5 Unimplemented: Read as ‘0’ bit 4 OCFLT: PWM Fault Condition Status bit 1 = PWM Fault condition has occurred (cleared in hardware only) 0 = No PWM Fault condition has occurred (this bit is only used when OCM<2:0> = 111) bit 3 OCTSEL: Output Compare Timer Select bit 1 = Timer3 is the clock source for Compare x 0 = Timer2 is the clock source for Compare x bit 2-0 OCM<2:0>: Output Compare Mode Select bits 111 = PWM mode on OCx, Fault pin enabled 110 = PWM mode on OCx, Fault pin disabled 101 = Initialize OCx pin low, generate continuous output pulses on OCx pin 100 = Initialize OCx pin low, generate single output pulse on OCx pin 011 = Compare event toggles OCx pin 010 = Initialize OCx pin high, compare event forces OCx pin low 001 = Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled © 2009 Microchip Technology Inc. DS70286C-page 169

dsPIC33FJXXXGPX06/X08/X10 NOTES: DS70286C-page 170 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 16.0 SERIAL PERIPHERAL Each SPI module consists of a 16-bit shift register, INTERFACE (SPI) SPIxSR (where x = 1 or 2), used for shifting data in and out, and a buffer register, SPIxBUF. A control register, Note: This data sheet summarizes the features SPIxCON, configures the module. Additionally, a status of the dsPIC33FJXXXGPX06/X08/X10 register, SPIxSTAT, indicates various status conditions. family of devices. However, it is not The serial interface consists of 4 pins: SDIx (serial data intended to be a comprehensive reference input), SDOx (serial data output), SCKx (shift clock input source. To complement the information in or output), and SSx (active-low slave select). this data sheet, refer to Section 18. In Master mode operation, SCK is a clock output but in “Serial Peripheral Interface (SPI)” Slave mode, it is a clock input. (DS70206) in the “dsPIC33F Family Reference Manual”, which is available from the Microchip web site (www.microchip.com). The Serial Peripheral Interface (SPI) module is a synchronous serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, ADC, etc. The SPI module is compatible with SPI and SIOP from Motorola®. Note: In this section, the SPI modules are referred to together as SPIx, or separately as SPI1 and SPI2. Special Function Registers will follow a similar notation. For example, SPIxCON refers to the control register for the SPI1 or SPI2 module. FIGURE 16-1: SPI MODULE BLOCK DIAGRAM SCKx 1:1 to 1:8 1:1/4/16/64 Secondary Primary FCY Prescaler Prescaler SSx Sync Control Select Control Clock Edge SPIxCON1<1:0> Shift Control SPIxCON1<4:2> SDOx Enable SDIx bit 0 Master Clock SPIxSR Transfer Transfer SPIxRXB SPIxTXB SPIxBUF Read SPIxBUF Write SPIxBUF 16 Internal Data Bus © 2009 Microchip Technology Inc. DS70286C-page 171

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 16-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 SPIEN — SPISIDL — — — — — bit 15 bit 8 U-0 R/C-0 U-0 U-0 U-0 U-0 R-0 R-0 — SPIROV — — — — SPITBF SPIRBF bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 SPIEN: SPIx Enable bit 1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins 0 = Disables module bit 14 Unimplemented: Read as ‘0’ bit 13 SPISIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 SPIROV: Receive Overflow Flag bit 1 = A new byte/word is completely received and discarded. The user software has not read the previous data in the SPIxBUF register 0 = No overflow has occurred bit 5-2 Unimplemented: Read as ‘0’ bit 1 SPITBF: SPIx Transmit Buffer Full Status bit 1 = Transmit not yet started, SPIxTXB is full 0 = Transmit started, SPIxTXB is empty Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB. Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR. bit 0 SPIRBF: SPIx Receive Buffer Full Status bit 1 = Receive complete, SPIxRXB is full 0 = Receive is not complete, SPIxRXB is empty Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB. DS70286C-page 172 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DISSCK DISSDO MODE16 SMP CKE(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSEN(3) CKP MSTEN SPRE<2:0>(2) PPRE<1:0>(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 DISSCK: Disable SCKx pin bit (SPI Master modes only) 1 = Internal SPI clock is disabled, pin functions as I/O 0 = Internal SPI clock is enabled bit 11 DISSDO: Disable SDOx pin bit 1 = SDOx pin is not used by module; pin functions as I/O 0 = SDOx pin is controlled by the module bit 10 MODE16: Word/Byte Communication Select bit 1 = Communication is word-wide (16 bits) 0 = Communication is byte-wide (8 bits) bit 9 SMP: SPIx Data Input Sample Phase bit Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time Slave mode: SMP must be cleared when SPIx is used in Slave mode. bit 8 CKE: SPIx Clock Edge Select bit(1) 1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6) 0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6) bit 7 SSEN: Slave Select Enable bit (Slave mode)(3) 1 = SSx pin used for Slave mode 0 = SSx pin not used by module. Pin controlled by port function bit 6 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level; active state is a low level 0 = Idle state for clock is a low level; active state is a high level bit 5 MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode Note1: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). 2: Do not set both Primary and Secondary prescalers to a value of 1:1. 3: This bit must be cleared when FRMEN = 1. © 2009 Microchip Technology Inc. DS70286C-page 173

dsPIC33FJXXXGPX06/X08/X10 REGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED) bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode)(2) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 • • • 000 = Secondary prescale 8:1 bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode)(2) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 Note1: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). 2: Do not set both Primary and Secondary prescalers to a value of 1:1. 3: This bit must be cleared when FRMEN = 1. DS70286C-page 174 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 16-3: SPIxCON2: SPIx CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 FRMEN SPIFSD FRMPOL — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — FRMDLY — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FRMEN: Framed SPIx Support bit 1 = Framed SPIx support enabled (SSx pin used as frame sync pulse input/output) 0 = Framed SPIx support disabled bit 14 SPIFSD: Frame Sync Pulse Direction Control bit 1 = Frame sync pulse input (slave) 0 = Frame sync pulse output (master) bit 13 FRMPOL: Frame Sync Pulse Polarity bit 1 = Frame sync pulse is active-high 0 = Frame sync pulse is active-low bit 12-2 Unimplemented: Read as ‘0’ bit 1 FRMDLY: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 Unimplemented: This bit must not be set to ‘1’ by the user application © 2009 Microchip Technology Inc. DS70286C-page 175

dsPIC33FJXXXGPX06/X08/X10 NOTES: DS70286C-page 176 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 17.0 INTER-INTEGRATED 17.2 I2C Registers CIRCUIT™ (I2C™) I2CxCON and I2CxSTAT are control and status registers, respectively. The I2CxCON register is Note: This data sheet summarizes the features readable and writable. The lower six bits of I2CxSTAT of the dsPIC33FJXXXGPX06/X08/X10 are read-only. The remaining bits of the I2CSTAT are family of devices. However, it is not read/write. intended to be a comprehensive reference source. To complement the information in I2CxRSR is the shift register used for shifting data, this data sheet, refer to Section 19. whereas I2CxRCV is the buffer register to which data “Inter-Integrated Circuit™ (I2C™)” bytes are written, or from which data bytes are read. (DS70195) in the “dsPIC33F Family I2CxRCV is the receive buffer. I2CxTRN is the transmit Reference Manual”, which is available register to which bytes are written during a transmit from the Microchip web site operation. (www.microchip.com). The I2CxADD register holds the slave address. A The Inter-Integrated Circuit (I2C) module provides status bit, ADD10, indicates 10-bit Address mode. The I2CxBRG acts as the Baud Rate Generator (BRG) complete hardware support for both Slave and Multi-Master modes of the I2C serial communication reload value. standard, with a 16-bit interface. In receive operations, I2CxRSR and I2CxRCV together form a double-buffered receiver. When I2CxRSR The dsPIC33FJXXXGPX06/X08/X10 devices have up to two I2C interface modules, denoted as I2C1 and receives a complete byte, it is transferred to I2CxRCV I2C2. Each I2C module has a 2-pin interface: the SCLx and an interrupt pulse is generated. pin is clock and the SDAx pin is data. Each I2C module ‘x’ (x = 1 or 2) offers the following key features: • I2C interface supporting both master and slave operation. • I2C Slave mode supports 7 and 10-bit address. • I2C Master mode supports 7 and 10-bit address. • I2C Port allows bidirectional transfers between master and slaves. • Serial clock synchronization for I2C port can be used as a handshake mechanism to suspend and resume serial transfer (SCLREL control). • I2C supports multi-master operation; detects bus collision and will arbitrate accordingly. 17.1 Operating Modes The hardware fully implements all the master and slave functions of the I2C Standard and Fast mode specifications, as well as 7 and 10-bit addressing. The I2C module can operate either as a slave or a master on an I2C bus. The following types of I2C operation are supported: • I2C slave operation with 7-bit address • I2C slave operation with 10-bit address • I2C master operation with 7 or 10-bit address For details about the communication sequence in each of these modes, please refer to the “dsPIC33F Family Reference Manual”. © 2009 Microchip Technology Inc. DS70286C-page 177

dsPIC33FJXXXGPX06/X08/X10 FIGURE 17-1: I2C™ BLOCK DIAGRAM (X = 1 OR 2) Internal Data Bus I2CxRCV Read Shift SCLx Clock I2CxRSR LSb SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation I2CxSTAT c gi Read o CDoelltiseicotn ntrol L Write o C I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSb Read ShiftClock Reload Control Write BRG Down Counter I2CxBRG Read TCY/2 DS70286C-page 178 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-1 HC R/W-0 R/W-0 R/W-0 R/W-0 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 HC R/W-0 HC R/W-0 HC R/W-0 HC R/W-0 HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HS = Set in hardware HC = Cleared in hardware -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 I2CEN: I2Cx Enable bit 1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins 0 = Disables the I2Cx module. All I2C pins are controlled by port functions bit 14 Unimplemented: Read as ‘0’ bit 13 I2CSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters an Idle mode 0 = Continue module operation in Idle mode bit 12 SCLREL: SCLx Release Control bit (when operating as I2C slave) 1 = Release SCLx clock 0 = Hold SCLx clock low (clock stretch) If STREN = 1: Bit is R/W (i.e., software may write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear at beginning of slave transmission. Hardware clear at end of slave reception. If STREN = 0: Bit is R/S (i.e., software may only write ‘1’ to release clock). Hardware clear at beginning of slave transmission. bit 11 IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit 1 = IPMI mode is enabled; all addresses Acknowledged 0 = IPMI mode disabled bit 10 A10M: 10-bit Slave Address bit 1 = I2CxADD is a 10-bit slave address 0 = I2CxADD is a 7-bit slave address bit 9 DISSLW: Disable Slew Rate Control bit 1 = Slew rate control disabled 0 = Slew rate control enabled bit 8 SMEN: SMBus Input Levels bit 1 = Enable I/O pin thresholds compliant with SMBus specification 0 = Disable SMBus input thresholds bit 7 GCEN: General Call Enable bit (when operating as I2C slave) 1 = Enable interrupt when a general call address is received in the I2CxRSR (module is enabled for reception) 0 = General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave) Used in conjunction with SCLREL bit. 1 = Enable software or receive clock stretching 0 = Disable software or receive clock stretching © 2009 Microchip Technology Inc. DS70286C-page 179

dsPIC33FJXXXGPX06/X08/X10 REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive) Value that will be transmitted when the software initiates an Acknowledge sequence. 1 = Send NACK during Acknowledge 0 = Send ACK during Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (when operating as I2C master, applicable during master receive) 1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit. Hardware clear at end of master Acknowledge sequence 0 = Acknowledge sequence not in progress bit 3 RCEN: Receive Enable bit (when operating as I2C master) 1 = Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte 0 = Receive sequence not in progress bit 2 PEN: Stop Condition Enable bit (when operating as I2C master) 1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence 0 = Stop condition not in progress bit 1 RSEN: Repeated Start Condition Enable bit (when operating as I2C master) 1 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of master Repeated Start sequence 0 = Repeated Start condition not in progress bit 0 SEN: Start Condition Enable bit (when operating as I2C master) 1 = Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence 0 = Start condition not in progress DS70286C-page 180 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER R-0 HSC R-0 HSC U-0 U-0 U-0 R/C-0 HS R-0 HSC R-0 HSC ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 bit 15 bit 8 R/C-0 HS R/C-0 HS R-0 HSC R/C-0 HSC R/C-0 HSC R-0 HSC R-0 HSC R-0 HSC IWCOL I2COV D_A P S R_W RBF TBF bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ C = Clear only bit R = Readable bit W = Writable bit HS = Set in hardware HSC = Hardware set/cleared -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ACKSTAT: Acknowledge Status bit (when operating as I2C master, applicable to master transmit operation) 1 = NACK received from slave 0 = ACK received from slave Hardware set or clear at end of slave Acknowledge. bit 14 TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation) 1 = Master transmit is in progress (8 bits + ACK) 0 = Master transmit is not in progress Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge. bit 13-11 Unimplemented: Read as ‘0’ bit 10 BCL: Master Bus Collision Detect bit 1 = A bus collision has been detected during a master operation 0 = No collision Hardware set at detection of bus collision. bit 9 GCSTAT: General Call Status bit 1 = General call address was received 0 = General call address was not received Hardware set when address matches general call address. Hardware clear at Stop detection. bit 8 ADD10: 10-Bit Address Status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection. bit 7 IWCOL: Write Collision Detect bit 1 = An attempt to write the I2CxTRN register failed because the I2C module is busy 0 = No collision Hardware set at occurrence of write to I2CxTRN while busy (cleared by software). bit 6 I2COV: Receive Overflow Flag bit 1 = A byte was received while the I2CxRCV register is still holding the previous byte 0 = No overflow Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software). bit 5 D_A: Data/Address bit (when operating as I2C slave) 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was device address Hardware clear at device address match. Hardware set by reception of slave byte. bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. © 2009 Microchip Technology Inc. DS70286C-page 181

dsPIC33FJXXXGPX06/X08/X10 REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. bit 2 R_W: Read/Write Information bit (when operating as I2C slave) 1 = Read - indicates data transfer is output from slave 0 = Write - indicates data transfer is input to slave Hardware set or clear after reception of I2C device address byte. bit 1 RBF: Receive Buffer Full Status bit 1 = Receive complete, I2CxRCV is full 0 = Receive not complete, I2CxRCV is empty Hardware set when I2CxRCV is written with received byte. Hardware clear when software reads I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. DS70286C-page 182 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 17-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — AMSK9 AMSK8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AMSK7 AMSK6 AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 AMSKx: Mask for Address bit x Select bit 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position © 2009 Microchip Technology Inc. DS70286C-page 183

dsPIC33FJXXXGPX06/X08/X10 NOTES: DS70286C-page 184 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 18.0 UNIVERSAL ASYNCHRONOUS • Hardware Flow Control Option with UxCTS and RECEIVER TRANSMITTER UxRTS pins • Fully Integrated Baud Rate Generator with 16-bit (UART) Prescaler Note: This data sheet summarizes the features • Baud rates ranging from 1 Mbps to 15 bps at 16x of the dsPIC33FJXXXGPX06/X08/X10 mode at 40 MIPS family of devices. However, it is not • Baud rates ranging from 4 Mbps to 61 bps at 4x mode intended to be a comprehensive reference at 40 MIPS source. To complement the information in • 4-deep First-In-First-Out (FIFO) Transmit Data this data sheet, refer to Section 17. Buffer “UART” (DS70188) in the “dsPIC33F • 4-Deep FIFO Receive Data Buffer Family Reference Manual”, which is • Parity, Framing and Buffer Overrun Error Detection available from the Microchip web site (www.microchip.com). • Support for 9-bit mode with Address Detect (9th bit = 1) The Universal Asynchronous Receiver Transmitter • Transmit and Receive Interrupts (UART) module is one of the serial I/O modules • A Separate Interrupt for all UART Error Conditions available in the dsPIC33FJXXXGPX06/X08/X10 • Loopback mode for Diagnostic Support device family. The UART is a full-duplex asynchronous system that can communicate with peripheral devices, • Support for Sync and Break Characters such as personal computers, LIN, RS-232 and RS-485 • Supports Automatic Baud Rate Detection interfaces. The module also supports a hardware flow • IrDA® Encoder and Decoder Logic control option with the UxCTS and UxRTS pins and • 16x Baud Clock Output for IrDA® Support also includes an IrDA® encoder and decoder. A simplified block diagram of the UART is shown in The primary features of the UART module are: Figure18-1. The UART module consists of the key • Full-Duplex, 8 or 9-bit Data Transmission through important hardware elements: the UxTX and UxRX pins • Baud Rate Generator • Even, Odd or No Parity Options (for 8-bit data) • Asynchronous Transmitter • One or Two Stop bits • Asynchronous Receiver FIGURE 18-1: UART SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator IrDA® BCLK Hardware Flow Control UxRTS UxCTS UART Receiver UxRX UART Transmitter UxTX Note1: Both UART1 and UART2 can trigger a DMA data transfer. If U1TX, U1RX, U2TX or U2RX is selected as a DMA IRQ source, a DMA transfer occurs when the U1TXIF, U1RXIF, U2TXIF or U2RXIF bit gets set as a result of a UART1 or UART2 transmission or reception. 2: If DMA transfers are required, the UART TX/RX FIFO buffer must be set to a size of 1 byte/word (i.e., UTXISEL<1:0> = 00 and URXISEL<1:0> = 00). © 2009 Microchip Technology Inc. DS70286C-page 185

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 18-1: UxMODE: UARTx MODE REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 UARTEN(1) — USIDL IREN(2) RTSMD — UEN<1:0> bit 15 bit 8 R/W-0 HC R/W-0 R/W-0 HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL bit 7 bit 0 Legend: HC = Hardware cleared R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 UARTEN: UARTx Enable bit(1) 1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0> 0 = UARTx is disabled; all UARTx pins are controlled by port latches; UARTx power consumption minimal bit 14 Unimplemented: Read as ‘0’ bit 13 USIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12 IREN: IrDA® Encoder and Decoder Enable bit(2) 1 = IrDA® encoder and decoder enabled 0 = IrDA® encoder and decoder disabled bit 11 RTSMD: Mode Selection for UxRTS Pin bit 1 = UxRTS pin in Simplex mode 0 = UxRTS pin in Flow Control mode bit 10 Unimplemented: Read as ‘0’ bit 9-8 UEN<1:0>: UARTx Enable bits 11 = UxTX, UxRX and BCLK pins are enabled and used; UxCTS pin controlled by port latches 10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used 01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by port latches 00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLK pins controlled by port latches bit 7 WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit 1 = UARTx will continue to sample the UxRX pin; interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = No wake-up enabled bit 6 LPBACK: UARTx Loopback Mode Select bit 1 = Enable Loopback mode 0 = Loopback mode is disabled bit 5 ABAUD: Auto-Baud Enable bit 1 = Enable baud rate measurement on the next character - requires reception of a Sync field (55h) before other data; cleared in hardware upon completion 0 = Baud rate measurement disabled or completed Note1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F Family Reference Manual” for information on enabling the UART module for receive or transmit operation. 2: This feature is only available for the 16x BRG mode (BRGH=0). DS70286C-page 186 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 REGISTER 18-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 4 URXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’ 0 = UxRX Idle state is ‘1’ bit 3 BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode) 0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit Note1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F Family Reference Manual” for information on enabling the UART module for receive or transmit operation. 2: This feature is only available for the 16x BRG mode (BRGH=0). © 2009 Microchip Technology Inc. DS70286C-page 187

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 R/W-0 HC R/W-0 R-0 R-1 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN(1) UTXBF TRMT bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/C-0 R-0 URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 Legend: HC = Hardware cleared R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15,13 UTXISEL<1:0>: Transmission Interrupt Mode Selection bits 11 = Reserved; do not use 10 = Interrupt when a character is transferred to the Transmit Shift Register, and as a result, the transmit buffer becomes empty 01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations are completed 00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least one character open in the transmit buffer) bit 14 UTXINV: Transmit Polarity Inversion bit If IREN = 0: 1 = UxTX Idle state is ‘0’ 0 = UxTX Idle state is ‘1’ If IREN = 1: 1 = IrDA® encoded UxTX Idle state is ‘1’ 0 = IrDA® encoded UxTX Idle state is ‘0’ bit 12 Unimplemented: Read as ‘0’ bit 11 UTXBRK: Transmit Break bit 1 = Send Sync Break on next transmission - Start bit, followed by twelve ‘0’ bits, followed by Stop bit; cleared by hardware upon completion 0 = Sync Break transmission disabled or completed bit 10 UTXEN: Transmit Enable bit(1) 1 = Transmit enabled, UxTX pin controlled by UARTx 0 = Transmit disabled, any pending transmission is aborted and buffer is reset. UxTX pin controlled by port bit 9 UTXBF: Transmit Buffer Full Status bit (read-only) 1 = Transmit buffer is full 0 = Transmit buffer is not full, at least one more character can be written bit 8 TRMT: Transmit Shift Register Empty bit (read-only) 1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit Shift Register is not empty, a transmission is in progress or queued bit 7-6 URXISEL<1:0>: Receive Interrupt Mode Selection bits 11 = Interrupt is set on UxRSR transfer making the receive buffer full (i.e., has 4 data characters) 10 = Interrupt is set on UxRSR transfer making the receive buffer 3/4 full (i.e., has 3 data characters) 0x = Interrupt is set when any character is received and transferred from the UxRSR to the receive buffer. Receive buffer has one or more characters Note1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F Family Reference Manual” for information on enabling the UART module for transmit operation. DS70286C-page 188 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 5 ADDEN: Address Character Detect bit (bit 8 of received data=1) 1 = Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect 0 = Address Detect mode disabled bit 4 RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Receiver is active bit 3 PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character (character at the top of the receive FIFO) 0 = Parity error has not been detected bit 2 FERR: Framing Error Status bit (read-only) 1 = Framing error has been detected for the current character (character at the top of the receive FIFO) 0 = Framing error has not been detected bit 1 OERR: Receive Buffer Overrun Error Status bit (read/clear only) 1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed. Clearing a previously set OERR bit (1→0 transition) will reset the receiver buffer and the UxRSR to the empty state bit 0 URXDA: Receive Buffer Data Available bit (read-only) 1 = Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F Family Reference Manual” for information on enabling the UART module for transmit operation. © 2009 Microchip Technology Inc. DS70286C-page 189

dsPIC33FJXXXGPX06/X08/X10 NOTES: DS70286C-page 190 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 19.0 ENHANCED CAN (ECAN™) • Programmable link to input capture module (IC2 MODULE for both CAN1 and CAN2) for time-stamping and network synchronization Note: This data sheet summarizes the features • Low-power Sleep and Idle mode of the dsPIC33FJXXXGPX06/X08/X10 The CAN bus module consists of a protocol engine and family of devices. However, it is not message buffering/control. The CAN protocol engine intended to be a comprehensive reference handles all functions for receiving and transmitting source. To complement the information in messages on the CAN bus. Messages are transmitted this data sheet, refer to Section 21. by first loading the appropriate data registers. Status “Enhanced Controller Area Network and errors can be checked by reading the appropriate (ECAN™)” (DS70185) in the “dsPIC33F registers. Any message detected on the CAN bus is Family Reference Manual”, which is checked for errors and then matched against filters to available from the Microchip web site see if it should be received and stored in one of the (www.microchip.com). receive registers. 19.2 Frame Types 19.1 Overview The CAN module transmits various types of frames The Enhanced Controller Area Network (ECAN) mod- which include data messages, or remote transmission ule is a serial interface, useful for communicating with requests initiated by the user, as other frames that are other CAN modules or microcontroller devices. This automatically generated for control purposes. The interface/protocol was designed to allow communica- following frame types are supported: tions within noisy environments. The dsPIC33FJXXXGPX06/X08/X10 devices contain up to • Standard Data Frame: two ECAN modules. A standard data frame is generated by a node when the node wishes to transmit data. It includes The CAN module is a communication controller imple- an 11-bit Standard Identifier (SID), but not an menting the CAN 2.0 A/B protocol, as defined in the 18-bit Extended Identifier (EID). BOSCH specification. The module will support CAN1.2, CAN 2.0A, CAN 2.0B Passive and CAN 2.0B Active • Extended Data Frame: versions of the protocol. The module implementation is An extended data frame is similar to a standard a full CAN system. The CAN specification is not covered data frame, but includes an extended identifier as within this data sheet. The reader may refer to the well. BOSCH CAN specification for further details. • Remote Frame: The module features are as follows: It is possible for a destination node to request the • Implementation of the CAN protocol, CAN1.2, data from the source. For this purpose, the CAN2.0A and CAN2.0B destination node sends a remote frame with an • Standard and extended data frames identifier that matches the identifier of the required • 0-8 bytes data length data frame. The appropriate data source node will • Programmable bit rate up to 1 Mbit/sec then send a data frame as a response to this remote request. • Automatic response to remote transmission requests • Error Frame: • Up to 8 transmit buffers with application specified An error frame is generated by any node that prioritization and abort capability (each buffer may detects a bus error. An error frame consists of two contain up to 8 bytes of data) fields: an error flag field and an error delimiter • Up to 32 receive buffers (each buffer may contain field. up to 8 bytes of data) • Overload Frame: • Up to 16 full (standard/extended identifier) An overload frame can be generated by a node as acceptance filters a result of two conditions. First, the node detects • 3 full acceptance filter masks a dominant bit during interframe space which is an • DeviceNet™ addressing support illegal condition. Second, due to internal condi- • Programmable wake-up functionality with tions, the node is not yet able to start reception of integrated low-pass filter the next message. A node may generate a maxi- • Programmable Loopback mode supports self-test mum of 2 sequential overload frames to delay the operation start of the next message. • Signaling via interrupt capabilities for all CAN • Interframe Space: receiver and transmitter error states Interframe space separates a proceeding frame • Programmable clock source (of whatever type) from a following data or remote frame. © 2009 Microchip Technology Inc. DS70286C-page 191

dsPIC33FJXXXGPX06/X08/X10 FIGURE 19-1: ECAN™ MODULE BLOCK DIAGRAM RXF15 Filter RXF14 Filter RXF13 Filter RXF12 Filter RXF11 Filter DMA Controller RXF10 Filter RXF9 Filter RXF8 Filter TRB7 TX/RX Buffer Control Register RXF7 Filter TRB6 TX/RX Buffer Control Register RXF6 Filter TRB5 TX/RX Buffer Control Register RXF5 Filter TRB4 TX/RX Buffer Control Register RXF4 Filter TRB3 TX/RX Buffer Control Register RXF3 Filter TRB2 TX/RX Buffer Control Register RXF2 Filter RXM2 Mask TRB1 TX/RX Buffer Control Register RXF1 Filter RXM1 Mask TRB0 TX/RX Buffer Control Register RXF0 Filter RXM0 Mask Transmit Byte Message Assembly Sequencer Buffer Control CPU Configuration Bus Logic CAN Protocol Engine Interrupts CiTX(1) CiRX(1) Note 1: i = 1 or 2 refers to a particular ECAN™ module (ECAN1 or ECAN2). DS70286C-page 192 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 19.3 Modes of Operation Note: Typically, if the CAN module is allowed to transmit in a particular mode of operation The CAN module can operate in one of several operation and a transmission is requested modes selected by the user. These modes include: immediately after the CAN module has • Initialization Mode been placed in that mode of operation, the • Disable Mode module waits for 11 consecutive recessive • Normal Operation Mode bits on the bus before starting • Listen Only Mode transmission. If the user switches to • Listen All Messages Mode Disable mode within this 11-bit period, then • Loopback Mode this transmission is aborted and the corre- sponding TXABT bit is set and TXREQ bit Modes are requested by setting the REQOP<2:0> bits is cleared. (CiCTRL1<10:8>). Entry into a mode is Acknowledged by monitoring the OPMODE<2:0> bits 19.3.3 NORMAL OPERATION MODE (CiCTRL1<7:5>). The module will not change the mode Normal Operation mode is selected when and the OPMODE bits until a change in mode is REQOP<2:0>=000. In this mode, the module is acceptable, generally during bus Idle time, which is activated and the I/O pins will assume the CAN bus defined as at least 11 consecutive recessive bits. functions. The module will transmit and receive CAN 19.3.1 INITIALIZATION MODE bus messages via the CiTX and CiRX pins. In the Initialization mode, the module will not transmit or 19.3.4 LISTEN ONLY MODE receive. The error counters are cleared and the If the Listen Only mode is activated, the module on the interrupt flags remain unchanged. The programmer will CAN bus is passive. The transmitter buffers revert to have access to Configuration registers that are access the port I/O function. The receive pins remain inputs. restricted in other modes. The module will protect the For the receiver, no error flags or Acknowledge signals user from accidentally violating the CAN protocol are sent. The error counters are deactivated in this through programming errors. All registers which control state. The Listen Only mode can be used for detecting the configuration of the module can not be modified the baud rate on the CAN bus. To use this, it is while the module is on-line. The CAN module will not necessary that there are at least two further nodes that be allowed to enter the Configuration mode while a communicate with each other. transmission is taking place. The Configuration mode serves as a lock to protect the following registers: 19.3.5 LISTEN ALL MESSAGES MODE • All Module Control Registers The module can be set to ignore all errors and receive • Baud Rate and Interrupt Configuration Registers any message. The Listen All Messages mode is • Bus Timing Registers activated by setting REQOP<2:0> = ‘111’. In this • Identifier Acceptance Filter Registers mode, the data which is in the message assembly buf- • Identifier Acceptance Mask Registers fer, until the time an error occurred, is copied in the receive buffer and can be read via the CPU interface. 19.3.2 DISABLE MODE 19.3.6 LOOPBACK MODE In Disable mode, the module will not transmit or receive. The module has the ability to set the WAKIF bit If the Loopback mode is activated, the module will due to bus activity, however, any pending interrupts will connect the internal transmit signal to the internal remain and the error counters will retain their value. receive signal at the module boundary. The transmit If the REQOP<2:0> bits (CiCTRL1<10:8>) = 001, the and receive pins revert to their port I/O function. module will enter the Module Disable mode. If the module is active, the module will wait for 11 recessive bits on the CAN bus, detect that condition as an Idle bus, then accept the module disable command. When the OPMODE<2:0> bits (CiCTRL1<7:5>)=001, that indicates whether the module successfully went into Module Disable mode. The I/O pins will revert to normal I/O function when the module is in the Module Disable mode. The module can be programmed to apply a low-pass filter function to the CiRX input line while the module or the CPU is in Sleep mode. The WAKFIL bit (CiCFG2<14>) enables or disables the filter. © 2009 Microchip Technology Inc. DS70286C-page 193

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 19-1: CiCTRL1: ECAN™ CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 r-0 R/W-1 R/W-0 R/W-0 — — CSIDL ABAT — REQOP<2:0> bit 15 bit 8 R-1 R-0 R-0 U-0 R/W-0 U-0 U-0 R/W-0 OPMODE<2:0> — CANCAP — — WIN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared r = Bit is Reserved bit 15-14 Unimplemented: Read as ‘0’ bit 13 CSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12 ABAT: Abort All Pending Transmissions bit Signal all transmit buffers to abort transmission. Module will clear this bit when all transmissions are aborted bit 11 Reserved: Do not use bit 10-8 REQOP<2:0>: Request Operation Mode bits 000 = Set Normal Operation mode 001 = Set Disable mode 010 = Set Loopback mode 011 = Set Listen Only Mode 100 = Set Configuration mode 101 = Reserved - do not use 110 = Reserved - do not use 111 = Set Listen All Messages mode bit 7-5 OPMODE<2:0>: Operation Mode bits 000 = Module is in Normal Operation mode 001 = Module is in Disable mode 010 = Module is in Loopback mode 011 = Module is in Listen Only mode 100 = Module is in Configuration mode 101 = Reserved 110 = Reserved 111 = Module is in Listen All Messages mode bit 4 Unimplemented: Read as ‘0’ bit 3 CANCAP: CAN Message Receive Timer Capture Event Enable bit 1 = Enable input capture based on CAN message receive 0 = Disable CAN capture bit 2-1 Unimplemented: Read as ‘0’ bit 0 WIN: SFR Map Window Select bit 1 = Use filter window 0 = Use buffer window DS70286C-page 194 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 19-2: CiCTRL2: ECAN™ CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0 — — — DNCNT<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 DNCNT<4:0>: DeviceNet™ Filter Bit Number bits 10010-11111 = Invalid selection 10001 = Compare up to data byte 3, bit 6 with EID<17> • • • 00001 = Compare up to data byte 1, bit 7 with EID<0> 00000 = Do not compare data bytes © 2009 Microchip Technology Inc. DS70286C-page 195

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 19-3: CiVEC: ECAN™ INTERRUPT CODE REGISTER U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0 — — — FILHIT<4:0> bit 15 bit 8 U-0 R-1 R-0 R-0 R-0 R-0 R-0 R-0 — ICODE<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 FILHIT<4:0>: Filter Hit Number bits 10000-11111 = Reserved 01111 = Filter 15 • • • 00001 = Filter 1 00000 = Filter 0 bit 7 Unimplemented: Read as ‘0’ bit 6-0 ICODE<6:0>: Interrupt Flag Code bits 1000101-1111111 = Reserved 1000100 = FIFO almost full interrupt 1000011 = Receiver overflow interrupt 1000010 = Wake-up interrupt 1000001 = Error interrupt 1000000 = No interrupt 0010000-0111111 = Reserved 0001111 = RB15 buffer Interrupt • • • 0001001 = RB9 buffer interrupt 0001000 = RB8 buffer interrupt 0000111 = TRB7 buffer interrupt 0000110 = TRB6 buffer interrupt 0000101 = TRB5 buffer interrupt 0000100 = TRB4 buffer interrupt 0000011 = TRB3 buffer interrupt 0000010 = TRB2 buffer interrupt 0000001 = TRB1 buffer interrupt 0000000 = TRB0 Buffer interrupt DS70286C-page 196 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 19-4: CiFCTRL: ECAN™ FIFO CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 DMABS<2:0> — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — FSA<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 DMABS<2:0>: DMA Buffer Size bits 111 = Reserved 110 = 32 buffers in DMA RAM 101 = 24 buffers in DMA RAM 100 = 16 buffers in DMA RAM 011 = 12 buffers in DMA RAM 010 = 8 buffers in DMA RAM 001 = 6 buffers in DMA RAM 000 = 4 buffers in DMA RAM bit 12-5 Unimplemented: Read as ‘0’ bit 4-0 FSA<4:0>: FIFO Area Starts with Buffer bits 11111 = RB31 buffer 11110 = RB30 buffer • • • 00001 = TRB1 buffer 00000 = TRB0 buffer © 2009 Microchip Technology Inc. DS70286C-page 197

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 19-5: CiFIFO: ECAN™ FIFO STATUS REGISTER U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 — — FBP<5:0> bit 15 bit 8 U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 — — FNRB<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 FBP<5:0>: FIFO Write Buffer Pointer bits 011111 = RB31 buffer 011110 = RB30 buffer • • • 000001 = TRB1 buffer 000000 = TRB0 buffer bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 FNRB<5:0>: FIFO Next Read Buffer Pointer bits 011111 = RB31 buffer 011110 = RB30 buffer • • • 000001 = TRB1 buffer 000000 = TRB0 buffer DS70286C-page 198 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 19-6: CiINTF: ECAN™ INTERRUPT FLAG REGISTER U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 — — TXBO TXBP RXBP TXWAR RXWAR EWARN bit 15 bit 8 R/C-0 R/C-0 R/C-0 U-0 R/C-0 R/C-0 R/C-0 R/C-0 IVRIF WAKIF ERRIF — FIFOIF RBOVIF RBIF TBIF bit 7 bit 0 Legend: C = Clear only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 TXBO: Transmitter in Error State Bus Off bit bit 12 TXBP: Transmitter in Error State Bus Passive bit bit 11 RXBP: Receiver in Error State Bus Passive bit bit 10 TXWAR: Transmitter in Error State Warning bit bit 9 RXWAR: Receiver in Error State Warning bit bit 8 EWARN: Transmitter or Receiver in Error State Warning bit bit 7 IVRIF: Invalid Message Received Interrupt Flag bit bit 6 WAKIF: Bus Wake-up Activity Interrupt Flag bit bit 5 ERRIF: Error Interrupt Flag bit (multiple sources in CiINTF<13:8> register) bit 4 Unimplemented: Read as ‘0’ bit 3 FIFOIF: FIFO Almost Full Interrupt Flag bit bit 2 RBOVIF: RX Buffer Overflow Interrupt Flag bit bit 1 RBIF: RX Buffer Interrupt Flag bit bit 0 TBIF: TX Buffer Interrupt Flag bit © 2009 Microchip Technology Inc. DS70286C-page 199

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 19-7: CiINTE: ECAN™ INTERRUPT ENABLE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 IVRIE WAKIE ERRIE — FIFOIE RBOVIE RBIE TBIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 IVRIE: Invalid Message Received Interrupt Enable bit bit 6 WAKIE: Bus Wake-up Activity Interrupt Flag bit bit 5 ERRIE: Error Interrupt Enable bit bit 4 Unimplemented: Read as ‘0’ bit 3 FIFOIE: FIFO Almost Full Interrupt Enable bit bit 2 RBOVIE: RX Buffer Overflow Interrupt Enable bit bit 1 RBIE: RX Buffer Interrupt Enable bit bit 0 TBIE: TX Buffer Interrupt Enable bit DS70286C-page 200 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 19-8: CiEC: ECAN™ TRANSMIT/RECEIVE ERROR COUNT REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 TERRCNT<7:0> bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 RERRCNT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 TERRCNT<7:0>: Transmit Error Count bits bit 7-0 RERRCNT<7:0>: Receive Error Count bits © 2009 Microchip Technology Inc. DS70286C-page 201

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 19-9: CiCFG1: ECAN™ BAUD RATE CONFIGURATION REGISTER 1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SJW<1:0> BRP<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-6 SJW<1:0>: Synchronization Jump Width bits 11 = Length is 4 x TQ 10 = Length is 3 x TQ 01 = Length is 2 x TQ 00 = Length is 1 x TQ bit 5-0 BRP<5:0>: Baud Rate Prescaler bits 11 1111 = TQ = 2 x 64 x 1/FCAN • • • 00 0010 = TQ = 2 x 3 x 1/FCAN 00 0001 = TQ = 2 x 2 x 1/FCAN 00 0000 = TQ = 2 x 1 x 1/FCAN DS70286C-page 202 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 19-10: CiCFG2: ECAN™ BAUD RATE CONFIGURATION REGISTER 2 U-0 R/W-x U-0 U-0 U-0 R/W-x R/W-x R/W-x — WAKFIL — — — SEG2PH<2:0> bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 WAKFIL: Select CAN bus Line Filter for Wake-up bit 1 = Use CAN bus line filter for wake-up 0 = CAN bus line filter is not used for wake-up bit 13-11 Unimplemented: Read as ‘0’ bit 10-8 SEG2PH<2:0>: Phase Buffer Segment 2 bits 111 = Length is 8 x TQ 000 = Length is 1 x TQ bit 7 SEG2PHTS: Phase Segment 2 Time Select bit 1 = Freely programmable 0 = Maximum of SEG1PH bits or Information Processing Time (IPT), whichever is greater bit 6 SAM: Sample of the CAN bus Line bit 1 = Bus line is sampled three times at the sample point 0 = Bus line is sampled once at the sample point bit 5-3 SEG1PH<2:0>: Phase Buffer Segment 1 bits 111 = Length is 8 x TQ 000 = Length is 1 x TQ bit 2-0 PRSEG<2:0>: Propagation Time Segment bits 111 = Length is 8 x TQ 000 = Length is 1 x TQ © 2009 Microchip Technology Inc. DS70286C-page 203

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 19-11: CiFEN1: ECAN™ ACCEPTANCE FILTER ENABLE REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLTEN15 FLTEN14 FLTEN13 FLTEN12 FLTEN11 FLTEN10 FLTEN9 FLTEN8 bit 15 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLTEN7 FLTEN6 FLTEN5 FLTEN4 FLTEN3 FLTEN2 FLTEN1 FLTEN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 FLTENn: Enable Filter n to Accept Messages bits 1 = Enable Filter n 0 = Disable Filter n REGISTER 19-12: CiBUFPNT1: ECAN™ FILTER 0-3 BUFFER POINTER REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F3BP<3:0> F2BP<3:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F1BP<3:0> F0BP<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 F3BP<3:0>: RX Buffer Written when Filter 3 Hits bits bit 11-8 F2BP<3:0>: RX Buffer Written when Filter 2 Hits bits bit 7-4 F1BP<3:0>: RX Buffer Written when Filter 1 Hits bits bit 3-0 F0BP<3:0>: RX Buffer Written when Filter 0 Hits bits 1111 = Filter hits received in RX FIFO buffer 1110 = Filter hits received in RX Buffer 14 • • • 0001 = Filter hits received in RX Buffer 1 0000 = Filter hits received in RX Buffer 0 DS70286C-page 204 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 19-13: CiBUFPNT2: ECAN™ FILTER 4-7 BUFFER POINTER REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F7BP<3:0> F6BP<3:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F5BP<3:0> F4BP<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 F7BP<3:0>: RX Buffer Written when Filter 7 Hits bits bit 11-8 F6BP<3:0>: RX Buffer Written when Filter 6 Hits bits bit 7-4 F5BP<3:0>: RX Buffer Written when Filter 5 Hits bits bit 3-0 F4BP<3:0>: RX Buffer Written when Filter 4 Hits bits REGISTER 19-14: CiBUFPNT3: ECAN™ FILTER 8-11 BUFFER POINTER REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F11BP<3:0> F10BP<3:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F9BP<3:0> F8BP<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 F11BP<3:0>: RX Buffer Written when Filter 11 Hits bits bit 11-8 F10BP<3:0>: RX Buffer Written when Filter 10 Hits bits bit 7-4 F9BP<3:0>: RX Buffer Written when Filter 9 Hits bits bit 3-0 F8BP<3:0>: RX Buffer Written when Filter 8 Hits bits © 2009 Microchip Technology Inc. DS70286C-page 205

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 19-15: CiBUFPNT4: ECAN™ FILTER 12-15 BUFFER POINTER REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F15BP<3:0> F14BP<3:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F13BP<3:0> F12BP<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 F15BP<3:0>: RX Buffer Written when Filter 15 Hits bits bit 11-8 F14BP<3:0>: RX Buffer Written when Filter 14 Hits bits bit 7-4 F13BP<3:0>: RX Buffer Written when Filter 13 Hits bits bit 3-0 F12BP<3:0>: RX Buffer Written when Filter 12 Hits bits DS70286C-page 206 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 19-16: CiRXFnSID: ECAN™ ACCEPTANCE FILTER n STANDARD IDENTIFIER (n = 0, 1, ..., 15) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 15 bit 8 R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x SID2 SID1 SID0 — EXIDE — EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 SID<10:0>: Standard Identifier bits 1 = Message address bit SIDx must be ‘1’ to match filter 0 = Message address bit SIDx must be ‘0’ to match filter bit 4 Unimplemented: Read as ‘0’ bit 3 EXIDE: Extended Identifier Enable bit If MIDE = 1 then: 1 = Match only messages with extended identifier addresses 0 = Match only messages with standard identifier addresses If MIDE = 0 then: Ignore EXIDE bit. bit 2 Unimplemented: Read as ‘0’ bit 1-0 EID<17:16>: Extended Identifier bits 1 = Message address bit EIDx must be ‘1’ to match filter 0 = Message address bit EIDx must be ‘0’ to match filter REGISTER 19-17: CiRXFnEID: ECAN™ ACCEPTANCE FILTER n EXTENDED IDENTIFIER (n = 0, 1, ..., 15) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 EID<15:0>: Extended Identifier bits 1 = Message address bit EIDx must be ‘1’ to match filter 0 = Message address bit EIDx must be ‘0’ to match filter © 2009 Microchip Technology Inc. DS70286C-page 207

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 19-18: CiFMSKSEL1: ECAN™ FILTER 7-0 MASK SELECTION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F7MSK<1:0> F6MSK<1:0> F5MSK<1:0> F4MSK<1:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F3MSK<1:0> F2MSK<1:0> F1MSK<1:0> F0MSK<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 F7MSK<1:0>: Mask Source for Filter 7 bit bit 13-12 F6MSK<1:0>: Mask Source for Filter 6 bit bit 11-10 F5MSK<1:0>: Mask Source for Filter 5 bit bit 9-8 F4MSK<1:0>: Mask Source for Filter 4 bit bit 7-6 F3MSK<1:0>: Mask Source for Filter 3 bit bit 5-4 F2MSK<1:0>: Mask Source for Filter 2 bit bit 3-2 F1MSK<1:0>: Mask Source for Filter 1 bit bit 1-0 F0MSK<1:0>: Mask Source for Filter 0 bit 11 = Reserved 10 = Acceptance Mask 2 registers contain mask 01 = Acceptance Mask 1 registers contain mask 00 = Acceptance Mask 0 registers contain mask DS70286C-page 208 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 19-19: CiFMSKSEL2: ECAN™ FILTER 15-8 MASK SELECTION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F15MSK<1:0> F14MSK<1:0> F13MSK<1:0> F12MSK<1:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F11MSK<1:0> F10MSK<1:0> F9MSK<1:0> F8MSK<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 F15MSK<1:0>: Mask Source for Filter 15 bit 11 = Reserved 10 = Acceptance Mask 2 registers contain mask 01 = Acceptance Mask 1 registers contain mask 00 = Acceptance Mask 0 registers contain mask bit 13-12 F14MSK<1:0>: Mask Source for Filter 14 bit (same values as bit 15-14) bit 11-10 F13MSK<1:0>: Mask Source for Filter 13 bit (same values as bit 15-14) bit 9-8 F12MSK<1:0>: Mask Source for Filter 12 bit (same values as bit 15-14) bit 7-6 F11MSK<1:0>: Mask Source for Filter 11 bit (same values as bit 15-14) bit 5-4 F10MSK<1:0>: Mask Source for Filter 10 bit (same values as bit 15-14) bit 3-2 F9MSK<1:0>: Mask Source for Filter 9 bit (same values as bit 15-14) bit 1-0 F8MSK<1:0>: Mask Source for Filter 8 bit (same values as bit 15-14) © 2009 Microchip Technology Inc. DS70286C-page 209

dsPIC33FJXXXGPX06/X08/X10 REGISTER 19-20: CiRXMnSID: ECAN™ ACCEPTANCE FILTER MASK n STANDARD IDENTIFIER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 15 bit 8 R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x SID2 SID1 SID0 — MIDE — EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 SID<10:0>: Standard Identifier bits 1 = Include bit SIDx in filter comparison 0 = Bit SIDx is don’t care in filter comparison bit 4 Unimplemented: Read as ‘0’ bit 3 MIDE: Identifier Receive Mode bit 1 = Match only message types (standard or extended address) that correspond to EXIDE bit in filter 0 = Match either standard or extended address message if filters match (i.e., if (Filter SID) = (Message SID) or if (Filter SID/EID) = (Message SID/EID)) bit 2 Unimplemented: Read as ‘0’ bit 1-0 EID<17:16>: Extended Identifier bits 1 = Include bit EIDx in filter comparison 0 = Bit EIDx is don’t care in filter comparison REGISTER 19-21: CiRXMnEID: ECAN™ ACCEPTANCE FILTER MASK n EXTENDED IDENTIFIER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 EID<15:0>: Extended Identifier bits 1 = Include bit EIDx in filter comparison 0 = Bit EIDx is don’t care in filter comparison DS70286C-page 210 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 19-22: CiRXFUL1: ECAN™ RECEIVE BUFFER FULL REGISTER 1 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9 RXFUL8 bit 15 bit 8 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXFUL7 RXFUL6 RXFUL5 RXFUL4 RXFUL3 RXFUL2 RXFUL1 RXFUL0 bit 7 bit 0 Legend: C = Clear only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 RXFUL<15:0>: Receive Buffer n Full bits 1 = Buffer is full (set by module) 0 = Buffer is empty (clear by application software) REGISTER 19-23: CiRXFUL2: ECAN™ RECEIVE BUFFER FULL REGISTER 2 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 bit 15 bit 8 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16 bit 7 bit 0 Legend: C = Clear only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 RXFUL<31:16>: Receive Buffer n Full bits 1 = Buffer is full (set by module) 0 = Buffer is empty (clear by application software) © 2009 Microchip Technology Inc. DS70286C-page 211

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 19-24: CiRXOVF1: ECAN™ RECEIVE BUFFER OVERFLOW REGISTER 1 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 RXOVF8 bit 15 bit 8 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 bit 7 bit 0 Legend: C = Clear only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 RXOVF<15:0>: Receive Buffer n Overflow bits 1 = Module pointed a write to a full buffer (set by module) 0 = Overflow is cleared (clear by application software) REGISTER 19-25: CiRXOVF2: ECAN™ RECEIVE BUFFER OVERFLOW REGISTER 2 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 bit 15 bit 8 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 bit 7 bit 0 Legend: C = Clear only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 RXOVF<31:16>: Receive Buffer n Overflow bits 1 = Module pointed a write to a full buffer (set by module) 0 = Overflow is cleared (clear by application software) DS70286C-page 212 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 19-26: CiTRmnCON: ECAN™ TX/RX BUFFER m CONTROL REGISTER (m = 0,2,4,6; n = 1,3,5,7) R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 TXENn TXABTn TXLARBn TXERRn TXREQn RTRENn TXnPRI<1:0> bit 15 bit 8 R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 TXENm TXABTm(1) TXLARBm(1) TXERRm(1) TXREQm RTRENm TXmPRI<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 See Definition for Bits 7-0, Controls Buffer n bit 7 TXENm: TX/RX Buffer Selection bit 1 = Buffer TRBn is a transmit buffer 0 = Buffer TRBn is a receive buffer bit 6 TXABTm: Message Aborted bit(1) 1 = Message was aborted 0 = Message completed transmission successfully bit 5 TXLARBm: Message Lost Arbitration bit(1) 1 = Message lost arbitration while being sent 0 = Message did not lose arbitration while being sent bit 4 TXERRm: Error Detected During Transmission bit(1) 1 = A bus error occurred while the message was being sent 0 = A bus error did not occur while the message was being sent bit 3 TXREQm: Message Send Request bit Setting this bit to ‘1’ requests sending a message. The bit will automatically clear when the message is successfully sent. Clearing the bit to ‘0’ while set will request a message abort. bit 2 RTRENm: Auto-Remote Transmit Enable bit 1 = When a remote transmit is received, TXREQ will be set 0 = When a remote transmit is received, TXREQ will be unaffected bit 1-0 TXmPRI<1:0>: Message Transmission Priority bits 11 = Highest message priority 10 = High intermediate message priority 01 = Low intermediate message priority 00 = Lowest message priority Note1: This bit is cleared when TXREQ is set. © 2009 Microchip Technology Inc. DS70286C-page 213

dsPIC33FJXXXGPX06/X08/X10 Note: The buffers, SID, EID, DLC, Data Field and Receive Status registers are located in DMA RAM. REGISTER 19-27: CiTRBnSID: ECAN™ BUFFER n STANDARD IDENTIFIER (n = 0, 1, ..., 31) U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — SID10 SID9 SID8 SID7 SID6 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID5 SID4 SID3 SID2 SID1 SID0 SRR IDE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-2 SID<10:0>: Standard Identifier bits bit 1 SRR: Substitute Remote Request bit 1 = Message will request remote transmission 0 = Normal message bit 0 IDE: Extended Identifier bit 1 = Message will transmit extended identifier 0 = Message will transmit standard identifier REGISTER 19-28: CiTRBnEID: ECAN™ BUFFER n EXTENDED IDENTIFIER (n = 0, 1, ..., 31) U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x — — — — EID17 EID16 EID15 EID14 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-0 EID<17:6>: Extended Identifier bits DS70286C-page 214 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 19-29: CiTRBnDLC: ECAN™ BUFFER n DATA LENGTH CONTROL (n = 0, 1, ..., 31) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID5 EID4 EID3 EID2 EID1 EID0 RTR RB1 bit 15 bit 8 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — RB0 DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 EID<5:0>: Extended Identifier bits bit 9 RTR: Remote Transmission Request bit 1 = Message will request remote transmission 0 = Normal message bit 8 RB1: Reserved Bit 1 User must set this bit to ‘0’ per CAN protocol. bit 7-5 Unimplemented: Read as ‘0’ bit 4 RB0: Reserved Bit 0 User must set this bit to ‘0’ per CAN protocol. bit 3-0 DLC<3:0>: Data Length Code bits REGISTER 19-30: CiTRBnDm: ECAN™ BUFFER n DATA FIELD BYTE m (n = 0, 1, ..., 31; m = 0, 1, ..., 7)(1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x TRBnDm7 TRBnDm6 TRBnDm5 TRBnDm4 TRBnDm3 TRBnDm2 TRBnDm1 TRBnDm0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 TRBnDm<7:0>: Data Field Buffer ‘n’ Byte ‘m’ bits Note1: The Most Significant Byte contains byte (m + 1) of the buffer. © 2009 Microchip Technology Inc. DS70286C-page 215

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 19-31: CiTRBnSTAT: ECAN™ RECEIVE BUFFER n STATUS (n = 0, 1, ..., 31) U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 FILHIT<4:0>: Filter Hit Code bits (only written by module for receive buffers, unused for transmit buffers) Encodes number of filter that resulted in writing this buffer. bit 7-0 Unimplemented: Read as ‘0’ DS70286C-page 216 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 20.0 DATA CONVERTER allows other devices to place data on the serial bus INTERFACE (DCI) MODULE during transmission periods not used by the DCI module. Note: This data sheet summarizes the features 20.2.3 CSDI PIN of the dsPIC33FJXXXGPX06/X08/X10 family of devices. However, it is not The Serial Data Input (CSDI) pin is configured as an intended to be a comprehensive reference input only pin when the module is enabled. source. To complement the information in this data sheet, refer to Section 20. “Data 20.2.3.1 COFS Pin Converter Interface (DCI)” (DS70288) in The Codec Frame Synchronization (COFS) pin is used the “dsPIC33F Family Reference Manual”, to synchronize data transfers that occur on the CSDO which is available from the Microchip web and CSDI pins. The COFS pin may be configured as an site (www.microchip.com). input or an output. The data direction for the COFS pin is determined by the COFSD control bit in the 20.1 Module Introduction DCICON1 register. The dsPIC33FJXXXGPX06/X08/X10 Data Converter The DCI module accesses the shadow registers while Interface (DCI) module allows simple interfacing of the CPU is in the process of accessing the memory devices, such as audio coder/decoders (Codecs), ADC mapped buffer registers. and D/A converters. The following interfaces are sup- 20.2.4 BUFFER DATA ALIGNMENT ported: Data values are always stored left justified in the • Framed Synchronous Serial Transfer (Single or buffers since most Codec data is represented as a Multi-Channel) • Inter-IC Sound (I2S) Interface signed 2’s complement fractional number. If the received word length is less than 16 bits, the unused • AC-Link Compliant mode Least Significant bits in the Receive Buffer registers are The DCI module provides the following general set to ‘0’ by the module. If the transmitted word length features: is less than 16bits, the unused LSbs in the Transmit Buffer register are ignored by the module. The word • Programmable word size up to 16 bits length setup is described in subsequent sections of this • Supports up to 16 time slots, for a maximum document. frame size of 256 bits • Data buffering for up to 4 samples without CPU 20.2.5 TRANSMIT/RECEIVE SHIFT overhead REGISTER The DCI module has a 16-bit shift register for shifting 20.2 Module I/O Pins serial data in and out of the module. Data is shifted There are four I/O pins associated with the module. in/out of the shift register, MSb first, since audio PCM When enabled, the module controls the data direction data is transmitted in signed 2’s complement format. of each of the four pins. 20.2.6 DCI BUFFER CONTROL 20.2.1 CSCK PIN The DCI module contains a buffer control unit for The CSCK pin provides the serial clock for the DCI transferring data between the shadow buffer memory module. The CSCK pin may be configured as an input and the Serial Shift register. The buffer control unit is a or output using the CSCKD control bit in the DCICON1 simple 2-bit address counter that points to word loca- SFR. When configured as an output, the serial clock is tions in the shadow buffer memory. For the receive provided by the dsPIC33FJXXXGPX06/X08/X10. memory space (high address portion of DCI buffer When configured as an input, the serial clock must be memory), the address counter is concatenated with a provided by an external device. ‘0’ in the MSb location to form a 3-bit address. For the transmit memory space (high portion of DCI buffer 20.2.2 CSDO PIN memory), the address counter is concatenated with a ‘1’ in the MSb location. The Serial Data Output (CSDO) pin is configured as an output only pin when the module is enabled. The Note: The DCI buffer control unit always CSDO pin drives the serial bus whenever data is to be accesses the same relative location in the transmitted. The CSDO pin is tri-stated, or driven to ‘0’, transmit and receive buffers, so only one during CSCK periods when data is not transmitted address counter is provided. depending on the state of the CSDOM control bit. This © 2009 Microchip Technology Inc. DS70286C-page 217

dsPIC33FJXXXGPX06/X08/X10 FIGURE 20-1: DCI MODULE BLOCK DIAGRAM BCG Control bits SCKD Sample Rate FOSC/4 CSCK Generator FSD Word Size Selection bits Frame Frame Length Selection bits Synchronization COFS DCI Mode Selection bits Generator s u B a at D bit Receive Buffer 6- Registers w/Shadow 1 DCI Buffer Control Unit 15 0 Transmit Buffer DCI Shift Register CSDI Registers w/Shadow CSDO DS70286C-page 218 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 20-1: DCICON1: DCI CONTROL REGISTER 1 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 DCIEN — DCISIDL — DLOOP CSCKD CSCKE COFSD bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 UNFM CSDOM DJST — — — COFSM<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 DCIEN: DCI Module Enable bit 1 = Module is enabled 0 = Module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 DCISIDL: DCI Stop in Idle Control bit 1 = Module will halt in CPU Idle mode 0 = Module will continue to operate in CPU Idle mode bit 12 Unimplemented: Read as ‘0’ bit 11 DLOOP: Digital Loopback Mode Control bit 1 = Digital Loopback mode is enabled. CSDI and CSDO pins internally connected 0 = Digital Loopback mode is disabled bit 10 CSCKD: Sample Clock Direction Control bit 1 = CSCK pin is an input when DCI module is enabled 0 = CSCK pin is an output when DCI module is enabled bit 9 CSCKE: Sample Clock Edge Control bit 1 = Data changes on serial clock falling edge, sampled on serial clock rising edge 0 = Data changes on serial clock rising edge, sampled on serial clock falling edge bit 8 COFSD: Frame Synchronization Direction Control bit 1 = COFS pin is an input when DCI module is enabled 0 = COFS pin is an output when DCI module is enabled bit 7 UNFM: Underflow Mode bit 1 = Transmit last value written to the transmit registers on a transmit underflow 0 = Transmit ‘0’s on a transmit underflow bit 6 CSDOM: Serial Data Output Mode bit 1 = CSDO pin will be tri-stated during disabled transmit time slots 0 = CSDO pin drives ‘0’s during disabled transmit time slots bit 5 DJST: DCI Data Justification Control bit 1 = Data transmission/reception is begun during the same serial clock cycle as the frame synchronization pulse 0 = Data transmission/reception is begun one serial clock cycle after frame synchronization pulse bit 4-2 Unimplemented: Read as ‘0’ bit 1-0 COFSM<1:0>: Frame Sync Mode bits 11 = 20-bit AC-Link mode 10 = 16-bit AC-Link mode 01 = I2S Frame Sync mode 00 = Multi-Channel Frame Sync mode © 2009 Microchip Technology Inc. DS70286C-page 219

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 20-2: DCICON2: DCI CONTROL REGISTER 2 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 R/W-0 — — — — BLEN<1:0> — COFSG3 bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 COFSG<2:0> — WS<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-10 BLEN<1:0>: Buffer Length Control bits 11 = Four data words will be buffered between interrupts 10 = Three data words will be buffered between interrupts 01 = Two data words will be buffered between interrupts 00 = One data word will be buffered between interrupts bit 9 Unimplemented: Read as ‘0’ bit 8-5 COFSG<3:0>: Frame Sync Generator Control bits 1111 = Data frame has 16 words • • • 0010 = Data frame has 3 words 0001 = Data frame has 2 words 0000 = Data frame has 1 word bit 4 Unimplemented: Read as ‘0’ bit 3-0 WS<3:0>: DCI Data Word Size bits 1111 = Data word size is 16 bits • • • 0100 = Data word size is 5 bits 0011 = Data word size is 4 bits 0010 = Invalid Selection. Do not use. Unexpected results may occur 0001 = Invalid Selection. Do not use. Unexpected results may occur 0000 = Invalid Selection. Do not use. Unexpected results may occur DS70286C-page 220 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 20-3: DCICON3: DCI CONTROL REGISTER 3 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — BCG<11:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BCG<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-0 BCG<11:0>: DCI Bit Clock Generator Control bits © 2009 Microchip Technology Inc. DS70286C-page 221

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 20-4: DCISTAT: DCI STATUS REGISTER U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — SLOT<3:0> bit 15 bit 8 U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — ROV RFUL TUNF TMPTY bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 SLOT<3:0>: DCI Slot Status bits 1111 = Slot #15 is currently active • • • 0010 = Slot #2 is currently active 0001 = Slot #1 is currently active 0000 = Slot #0 is currently active bit 7-4 Unimplemented: Read as ‘0’ bit 3 ROV: Receive Overflow Status bit 1 = A receive overflow has occurred for at least one receive register 0 = A receive overflow has not occurred bit 2 RFUL: Receive Buffer Full Status bit 1 = New data is available in the receive registers 0 = The receive registers have old data bit 1 TUNF: Transmit Buffer Underflow Status bit 1 = A transmit underflow has occurred for at least one transmit register 0 = A transmit underflow has not occurred bit 0 TMPTY: Transmit Buffer Empty Status bit 1 = The transmit registers are empty 0 = The transmit registers are not empty DS70286C-page 222 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 20-5: RSCON: DCI RECEIVE SLOT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RSE15 RSE14 RSE13 RSE12 RSE11 RSE10 RSE9 RSE8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RSE7 RSE6 RSE5 RSE4 RSE3 RSE2 RSE1 RSE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 RSE<15:0>: Receive Slot Enable bits 1 = CSDI data is received during the individual time slot n 0 = CSDI data is ignored during the individual time slot n REGISTER 20-6: TSCON: DCI TRANSMIT SLOT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TSE15 TSE14 TSE13 TSE12 TSE11 TSE10 TSE9 TSE8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TSE7 TSE6 TSE5 TSE4 TSE3 TSE2 TSE1 TSE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 TSE<15:0>: Transmit Slot Enable Control bits 1 = Transmit buffer contents are sent during the individual time slot n 0 = CSDO pin is tri-stated or driven to logic ‘0’, during the individual time slot, depending on the state of the CSDOM bit © 2009 Microchip Technology Inc. DS70286C-page 223

dsPIC33FJXXXGPX06/X08/X10 NOTES: DS70286C-page 224 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 21.0 10-BIT/12-BIT analog input pins. The actual number of analog input ANALOG-TO-DIGITAL pins and external voltage reference input configuration will depend on the specific device. Refer to the device CONVERTER (ADC) data sheet for further details. Note: This data sheet summarizes the features A block diagram of the ADC is shown in Figure21-1. of the dsPIC33FJXXXGPX06/X08/X10 family of devices. However, it is not 21.2 ADC Initialization intended to be a comprehensive reference The following configuration steps should be performed. source. To complement the information in this data sheet, refer to Section 16. 1. Configure the ADC module: “Analog-to-Digital Converter (ADC)” a) Select port pins as analog inputs (DS70183) in the “dsPIC33F Family (ADxPCFGH<15:0> or ADxPCFGL<15:0>) Reference Manual”, which is available b) Select voltage reference source to match from the Microchip web site expected range on analog inputs (www.microchip.com). (ADxCON2<15:13>) The dsPIC33FJXXXGPX06/X08/X10 devices have up c) Select the analog conversion clock to to 32 ADC input channels. These devices also have up match desired data rate with processor to 2 ADC modules (ADCx, where ‘x’ = 1 or 2), each with clock (ADxCON3<7:0>) its own set of Special Function Registers. d) Determine how many S/H channels will be The AD12B bit (ADxCON1<10>) allows each of the used (ADxCON2<9:8> and ADC modules to be configured by the user as either a ADxPCFGH<15:0> or ADxPCFGL<15:0>) 10-bit, 4-sample/hold ADC (default configuration) or a e) Select the appropriate sample/conversion 12-bit, 1-sample/hold ADC. sequence (ADxCON1<7:5> and ADxCON3<12:8>) Note: The ADC module needs to be disabled f) Select how conversion results are before modifying the AD12B bit. presented in the buffer (ADxCON1<9:8>) 21.1 Key Features g) Turn on ADC module (ADxCON1<15>) 2. Configure ADC interrupt (if required): The 10-bit ADC configuration has the following key a) Clear the ADxIF bit features: b) Select ADC interrupt priority • Successive Approximation (SAR) conversion • Conversion speeds of up to 1.1 Msps 21.3 ADC and DMA • Up to 32 analog input pins If more than one conversion result needs to be buffered • External voltage reference input pins before triggering an interrupt, DMA data transfers can • Simultaneous sampling of up to four analog input be used. Both ADC1 and ADC2 can trigger a DMA data pins transfer. If ADC1 or ADC2 is selected as the DMA IRQ • Automatic Channel Scan mode source, a DMA transfer occurs when the AD1IF or • Selectable conversion trigger source AD2IF bit gets set as a result of an ADC1 or ADC2 sample conversion sequence. • Selectable Buffer Fill modes • Four result alignment options (signed/unsigned, The SMPI<3:0> bits (ADxCON2<5:2>) are used to fractional/integer) select how often the DMA RAM buffer pointer is incremented. • Operation during CPU Sleep and Idle modes The ADDMABM bit (ADxCON1<12>) determines how The 12-bit ADC configuration supports all the above the conversion results are filled in the DMA RAM buffer features, except: area being used for ADC. If this bit is set, DMA buffers • In the 12-bit configuration, conversion speeds of are written in the order of conversion. The module will up to 500 ksps are supported provide an address to the DMA channel that is the • There is only 1 sample/hold amplifier in the 12-bit same as the address used for the non-DMA configuration, so simultaneous sampling of stand-alone buffer. If the ADDMABM bit is cleared, then multiple channels is not supported. DMA buffers are written in Scatter/Gather mode. The Depending on the particular device pinout, the ADC module will provide a scatter/gather address to the can have up to 32 analog input pins, designated AN0 DMA channel, based on the index of the analog input through AN31. In addition, there are two analog input and the size of the DMA buffer. pins for external voltage reference connections. These voltage reference inputs may be shared with other © 2009 Microchip Technology Inc. DS70286C-page 225

dsPIC33FJXXXGPX06/X08/X10 FIGURE 21-1: ADCx MODULE BLOCK DIAGRAM AN0 ANy(3) S/H0 CHANNEL SCAN + CH0SB<4:0> CH0SA<4:0> - CH0 CSCNA AN1 VREF- CH0NA CH0NB VREF+(1) AVDD VREF-(1) AVSS AN0 AN3 S/H1 + CH123SA CH123SB - CH1(2) AN6 AN9 VREF- VREFH VREFL CH123NA CH123NB SAR ADC ADC1BUF0 AN1 AN4 S/H2 + CH123SACH123SB - CH2(2) AN7 AN10 VREF- CH123NA CH123NB AN2 AN5 S/H3 + CH123SA CH123SB CH3(2) - AN8 AN11 VREF- CH123NA CH123NB Alternate Input Selection Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs. 2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation. 3: For 64-pin devices, y = 17; for 80-pin devices, y = 23; for 100-pin devices, y = 31; for ADC2, y = 15. DS70286C-page 226 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 FIGURE 21-2: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM ADxCON3<15> ADC Internal RC Clock(2) 0 TAD ADxCON3<5:0> 1 6 ADC Conversion TCY Clock Multiplier TOSC(1) X2 1, 2, 3, 4, 5,..., 64 Note 1: Refer to Figure9-2 for the derivation of FOSC when the PLL is enabled. If the PLL is not used, FOSC is equal to the clock source frequency. TOSC = 1/FOSC. 2: See the ADC electrical specifications for the exact RC clock value. © 2009 Microchip Technology Inc. DS70286C-page 227

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 21-1: ADxCON1: ADCx CONTROL REGISTER 1 (where x = 1 or 2) R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 ADON — ADSIDL ADDMABM — AD12B FORM<1:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/C-0 HC,HS HC, HS SSRC<2:0> — SIMSAM ASAM SAMP DONE bit 7 bit 0 Legend: HC = Cleared by hardware HS = Set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADON: ADC Operating Mode bit 1 = ADC module is operating 0 = ADC is off bit 14 Unimplemented: Read as ‘0’ bit 13 ADSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12 ADDMABM: DMA Buffer Build Mode bit 1 = DMA buffers are written in the order of conversion. The module will provide an address to the DMA channel that is the same as the address used for the non-DMA stand-alone buffer 0 = DMA buffers are written in Scatter/Gather mode. The module will provide a scatter/gather address to the DMA channel, based on the index of the analog input and the size of the DMA buffer bit 11 Unimplemented: Read as ‘0’ bit 10 AD12B: 10-Bit or 12-Bit Operation Mode bit 1 = 12-bit, 1-channel ADC operation 0 = 10-bit, 4-channel ADC operation bit 9-8 FORM<1:0>: Data Output Format bits For 10-bit operation: 11 = Signed fractional (DOUT = sddd dddd dd00 0000, where s = .NOT.d<9>) 10 = Fractional (DOUT = dddd dddd dd00 0000) 01 = Signed integer (DOUT = ssss sssd dddd dddd, where s = .NOT.d<9>) 00 = Integer (DOUT = 0000 00dd dddd dddd) For 12-bit operation: 11 = Signed fractional (DOUT = sddd dddd dddd 0000, where s = .NOT.d<11>) 10 = Fractional (DOUT = dddd dddd dddd 0000) 01 = Signed Integer (DOUT = ssss sddd dddd dddd, where s = .NOT.d<11>) 00 = Integer (DOUT = 0000 dddd dddd dddd) bit 7-5 SSRC<2:0>: Sample Clock Source Select bits 111 = Internal counter ends sampling and starts conversion (auto-convert) 110 = Reserved 101 = Reserved 100 = Reserved 011 = MPWM interval ends sampling and starts conversion 010 = GP timer (Timer3 for ADC1, Timer5 for ADC2) compare ends sampling and starts conversion 001 = Active transition on INT0 pin ends sampling and starts conversion 000 = Clearing sample bit ends sampling and starts conversion bit 4 Unimplemented: Read as ‘0’ DS70286C-page 228 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 REGISTER 21-1: ADxCON1: ADCx CONTROL REGISTER 1 (where x = 1 or 2) (CONTINUED) bit 3 SIMSAM: Simultaneous Sample Select bit (only applicable when CHPS<1:0> = 01 or 1x) When AD12B = 1, SIMSAM is: U-0, Unimplemented, Read as ‘0’ 1 = Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or Samples CH0 and CH1 simultaneously (when CHPS<1:0> = 01) 0 = Samples multiple channels individually in sequence bit 2 ASAM: ADC Sample Auto-Start bit 1 = Sampling begins immediately after last conversion. SAMP bit is auto-set 0 = Sampling begins when SAMP bit is set bit 1 SAMP: ADC Sample Enable bit 1 = ADC sample/hold amplifiers are sampling 0 = ADC sample/hold amplifiers are holding If ASAM = 0, software may write ‘1’ to begin sampling. Automatically set by hardware if ASAM = 1. If SSRC = 000, software may write ‘0’ to end sampling and start conversion. If SSRC ≠ 000, automatically cleared by hardware to end sampling and start conversion. bit 0 DONE: ADC Conversion Status bit 1 = ADC conversion cycle is completed 0 = ADC conversion not started or in progress Automatically set by hardware when ADC conversion is complete. Software may write ‘0’ to clear DONE status (software not allowed to write ‘1’). Clearing this bit will NOT affect any operation in prog- ress. Automatically cleared by hardware at start of a new conversion. © 2009 Microchip Technology Inc. DS70286C-page 229

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 21-2: ADxCON2: ADCx CONTROL REGISTER 2 (where x = 1 or 2) R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 VCFG<2:0> — — CSCNA CHPS<1:0> bit 15 bit 8 R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUFS — SMPI<3:0> BUFM ALTS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 VCFG<2:0>: Converter Voltage Reference Configuration bits VREF+ VREF- 000 AVDD AVSS 001 External VREF+ AVSS 010 AVDD External VREF- 011 External VREF+ External VREF- 1xx AVDD Avss bit 12-11 Unimplemented: Read as ‘0’ bit 10 CSCNA: Scan Input Selections for CH0+ during Sample A bit 1 = Scan inputs 0 = Do not scan inputs bit 9-8 CHPS<1:0>: Selects Channels Utilized bits When AD12B = 1, CHPS<1:0> is: U-0, Unimplemented, Read as ‘0’ 1x = Converts CH0, CH1, CH2 and CH3 01 = Converts CH0 and CH1 00 = Converts CH0 bit 7 BUFS: Buffer Fill Status bit (only valid when BUFM = 1) 1 = ADC is currently filling second half of buffer, user should access data in first half 0 = ADC is currently filling first half of buffer, user should access data in second half bit 6 Unimplemented: Read as ‘0’ bit 5-2 SMPI<3:0>: Selects Increment Rate for DMA Addresses bits or number of sample/conversion operations per interrupt 1111 = Increments the DMA address or generates interrupt after completion of every 16th sample/conversion operation 1110 = Increments the DMA address or generates interrupt after completion of every 15th sample/conversion operation • • • 0001 = Increments the DMA address or generates interrupt after completion of every 2nd sample/conversion operation 0000 = Increments the DMA address or generates interrupt after completion of every sample/conversion operation bit 1 BUFM: Buffer Fill Mode Select bit 1 = Starts filling first half of buffer on first interrupt and second half of the buffer on next interrupt 0 = Always starts filling buffer from the beginning bit 0 ALTS: Alternate Input Sample Mode Select bit 1 = Uses channel input selects for Sample A on first sample and Sample B on next sample 0 = Always uses channel input selects for Sample A DS70286C-page 230 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 21-3: ADxCON3: ADCx CONTROL REGISTER 3 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADRC — — SAMC<4:0>(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCS<7:0>(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADRC: ADC Conversion Clock Source bit 1 = ADC internal RC clock 0 = Clock derived from system clock bit 14-13 Unimplemented: Read as ‘0’ bit 12-8 SAMC<4:0>: Auto Sample Time bits(1) 11111 = 31 TAD • • • 00001 = 1 TAD 00000 = 0 TAD bit 7-0 ADCS<7:0>: ADC Conversion Clock Select bits(2) 11111111 = Reserved • • • 01000000 = Reserved 00111111 = TCY · (ADCS<7:0> + 1) = 64 · TCY = TAD • • • 00000010 = TCY · (ADCS<7:0> + 1) = 3 · TCY = TAD 00000001 = TCY · (ADCS<7:0> + 1) = 2 · TCY = TAD 00000000 = TCY · (ADCS<7:0> + 1) = 1 · TCY = TAD Note1: This bit only used if ADxCON1<SSRC> = 1. 2: This bit is not used if ADxCON3<ADRC> = 1. © 2009 Microchip Technology Inc. DS70286C-page 231

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 21-4: ADxCON4: ADCx CONTROL REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — DMABL<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 DMABL<2:0>: Selects Number of DMA Buffer Locations per Analog Input bits 111 = Allocates 128 words of buffer to each analog input 110 = Allocates 64 words of buffer to each analog input 101 = Allocates 32 words of buffer to each analog input 100 = Allocates 16 words of buffer to each analog input 011 = Allocates 8 words of buffer to each analog input 010 = Allocates 4 words of buffer to each analog input 001 = Allocates 2 words of buffer to each analog input 000 = Allocates 1 word of buffer to each analog input DS70286C-page 232 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 21-5: ADxCHS123: ADCx INPUT CHANNEL 1, 2, 3 SELECT REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — CH123NB<1:0> CH123SB bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — CH123NA<1:0> CH123SA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-9 CH123NB<1:0>: Channel 1, 2, 3 Negative Input Select for Sample B bits When AD12B = 1, CHxNB is: U-0, Unimplemented, Read as ‘0’ 11 = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11 10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8 0x = CH1, CH2, CH3 negative input is VREF- bit 8 CH123SB: Channel 1, 2, 3 Positive Input Select for Sample B bit When AD12B = 1, CHxSB is: U-0, Unimplemented, Read as ‘0’ 1 = CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5 0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2 bit 7-3 Unimplemented: Read as ‘0’ bit 2-1 CH123NA<1:0>: Channel 1, 2, 3 Negative Input Select for Sample A bits When AD12B = 1, CHxNA is: U-0, Unimplemented, Read as ‘0’ 11 = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11 10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8 0x = CH1, CH2, CH3 negative input is VREF- bit 0 CH123SA: Channel 1, 2, 3 Positive Input Select for Sample A bit When AD12B = 1, CHxSA is: U-0, Unimplemented, Read as ‘0’ 1 = CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5 0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2 © 2009 Microchip Technology Inc. DS70286C-page 233

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 21-6: ADxCHS0: ADCx INPUT CHANNEL 0 SELECT REGISTER R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NB — — CH0SB<4:0> bit 15 bit 8 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NA — — CH0SA<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CH0NB: Channel 0 Negative Input Select for Sample B bit Same definition as bit 7. bit 14-13 Unimplemented: Read as ‘0’ bit 12-8 CH0SB<4:0>: Channel 0 Positive Input Select for Sample B bits Same definition as bit<4:0>. bit 7 CH0NA: Channel 0 Negative Input Select for Sample A bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VREF- bit 6-5 Unimplemented: Read as ‘0’ bit 4-0 CH0SA<4:0>: Channel 0 Positive Input Select for Sample A bits 11111 = Channel 0 positive input is AN31 11110 = Channel 0 positive input is AN30 • • • 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 00000 = Channel 0 positive input is AN0 Note: ADC2 can only select AN0 through AN15 as positive input. DS70286C-page 234 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 21-7: ADxCSSH: ADCx INPUT SCAN SELECT REGISTER HIGH(1,2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS31 CSS30 CSS29 CSS28 CSS27 CSS26 CSS25 CSS24 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS23 CSS22 CSS21 CSS20 CSS19 CSS18 CSS17 CSS16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 CSS<31:16>: ADC Input Scan Selection bits 1 = Select ANx for input scan 0 = Skip ANx for input scan Note1: On devices without 32 analog inputs, all ADxCSSH bits may be selected by user. However, inputs selected for scan without a corresponding input on device will convert VREFL. 2: CSSx = ANx, where x = 16 through 31. REGISTER 21-8: ADxCSSL: ADCx INPUT SCAN SELECT REGISTER LOW(1,2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS15 CSS14 CSS13 CSS12 CSS11 CSS10 CSS9 CSS8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 CSS<15:0>: ADC Input Scan Selection bits 1 = Select ANx for input scan 0 = Skip ANx for input scan Note1: On devices without 16 analog inputs, all ADxCSSL bits may be selected by user. However, inputs selected for scan without a corresponding input on device will convert VREFL. 2: CSSx = ANx, where x = 0 through 15. © 2009 Microchip Technology Inc. DS70286C-page 235

dsPIC33FJXXXGPX06/X08/X10 R EGISTER 21-9: AD1PCFGH: ADC1 PORT CONFIGURATION REGISTER HIGH(1,2,3) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PCFG31 PCFG30 PCFG29 PCFG28 PCFG27 PCFG26 PCFG25 PCFG24 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PCFG23 PCFG22 PCFG21 PCFG20 PCFG19 PCFG18 PCFG17 PCFG16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PCFG<31:16>: ADC Port Configuration Control bits 1 = Port pin in Digital mode, port read input enabled, ADC input multiplexer connected to AVSS 0 = Port pin in Analog mode, port read input disabled, ADC samples pin voltage Note1: On devices without 32 analog inputs, all PCFG bits are R/W by user. However, PCFG bits are ignored on ports without a corresponding input on device. 2: ADC2 only supports analog inputs AN0-AN15; therefore, no ADC2 port Configuration register exists. 3: PCFGx = ANx, where x = 16 through 31. REGISTER 21-10: ADxPCFGL: ADCx PORT CONFIGURATION REGISTER LOW(1,2,3) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 PCFG<15:0>: ADC Port Configuration Control bits 1 = Port pin in Digital mode, port read input enabled, ADC input multiplexer connected to AVSS 0 = Port pin in Analog mode, port read input disabled, ADC samples pin voltage Note1: On devices without 16 analog inputs, all PCFG bits are R/W by user. However, PCFG bits are ignored on ports without a corresponding input on device. 2: On devices with two analog-to-digital modules, both AD1PCFGL and AD2PCFGL will affect the configuration of port pins multiplexed with AN0-AN15. 3: PCFGx = ANx, where x = 0 through 15. DS70286C-page 236 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 22.0 SPECIAL FEATURES 22.1 Configuration Bits Note: This data sheet summarizes the features The Configuration bits can be programmed (read as of the dsPIC33FJXXXGPX06/X08/X10 ‘0’), or left unprogrammed (read as ‘1’), to select family of devices. However, it is not various device configurations. These bits are mapped intended to be a comprehensive reference starting at program memory location 0xF80000. source. To complement the information in The device Configuration register map is shown in this data sheet, refer to Section 23. Table22-1. “CodeGuard™ Security” (DS70199), The individual Configuration bit descriptions for the Section 24. “Programming and FBS, FSS, FGS, FOSCSEL, FOSC, FWDT, FPOR and Diagnostics” (DS70207), and Section FICD Configuration registers are shown in Table22-2. 25. “Device Configuration” (DS70194) in the “dsPIC33F Family Reference Note that address 0xF80000 is beyond the user program Manual”, which is available from the memory space. In fact, it belongs to the configuration Microchip web site (www.microchip.com). memory space (0x800000-0xFFFFFF) which can only be accessed using table reads and table writes. dsPIC33FJXXXGPX06/X08/X10 devices include The upper byte of all device Configuration registers several features intended to maximize application should always be ‘1111 1111’. This makes them flexibility and reliability, and minimize cost through elim- appear to be NOP instructions in the remote event that ination of external components. These are: their locations are ever executed by accident. Since • Flexible Configuration Configuration bits are not implemented in the • Watchdog Timer (WDT) corresponding locations, writing ‘1’s to these locations • Code Protection and CodeGuard™ Security has no effect on device operation. • JTAG Boundary Scan Interface To prevent inadvertent configuration changes during • In-Circuit Serial Programming™ (ICSP™) code execution, all programmable Configuration bits • In-Circuit Emulation are write-once. After a bit is initially programmed during a power cycle, it cannot be written to again. Changing a device configuration requires that power to the device be cycled. TABLE 22-1: DEVICE CONFIGURATION REGISTER MAP Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0xF80000 FBS RBS<1:0> — — BSS<2:0> BWRP 0xF80002 FSS RSS<1:0> — — SSS<2:0> SWRP 0xF80004 FGS — — — — — GSS1 GSS0 GWRP 0xF80006 FOSCSEL IESO Reserved(2) — — — FNOSC<2:0> 0xF80008 FOSC FCKSM<1:0> — — — OSCIOFNC POSCMD<1:0> 0xF8000A FWDT FWDTEN WINDIS — WDTPRE WDTPOST<3:0> 0xF8000C FPOR — — — — — FPWRT<2:0> 0xF8000E FICD Reserved(1) JTAGEN — — — ICS<1:0> 0xF80010 FUID0 User Unit ID Byte 0 0xF80012 FUID1 User Unit ID Byte 1 0xF80014 FUID2 User Unit ID Byte 2 0xF80016 FUID3 User Unit ID Byte 3 Note1: When read, these bits will appear as ‘1’. When you write to these bits, set these bits to ‘1’. 2: When read, this bit returns the current programmed value. © 2009 Microchip Technology Inc. DS70286C-page 237

dsPIC33FJXXXGPX06/X08/X10 TABLE 22-2: dsPIC33FJXXXGPX06/X08/X10 CONFIGURATION BITS DESCRIPTION Bit Field Register Description BWRP FBS Boot Segment Program Flash Write Protection 1 = Boot segment may be written 0 = Boot segment is write-protected BSS<2:0> FBS Boot Segment Program Flash Code Protection Size X11 = No Boot program Flash segment Boot space is 1K IW less VS 110 = Standard security; boot program Flash segment starts at End of VS, ends at 0007FEh 010 = High security; boot program Flash segment starts at End of VS, ends at 0007FEh Boot space is 4K IW less VS 101 = Standard security; boot program Flash segment starts at End of VS, ends at 001FFEh 001 = High security; boot program Flash segment starts at End of VS, ends at 001FFEh Boot space is 8K IW less VS 100 = Standard security; boot program Flash segment starts at End of VS, ends at 003FFEh 000 = High security; boot program Flash segment starts at End of VS, ends at 003FFEh RBS<1:0> FBS Boot Segment RAM Code Protection 11 = No Boot RAM defined 10 = Boot RAM is 128 Bytes 01 = Boot RAM is 256 Bytes 00 = Boot RAM is 1024 Bytes SWRP FSS Secure Segment Program Flash Write Protection 1 = Secure segment may be written 0 = Secure segment is write-protected DS70286C-page 238 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 TABLE 22-2: dsPIC33FJXXXGPX06/X08/X10 CONFIGURATION BITS DESCRIPTION (CONTINUED) Bit Field Register Description SSS<2:0> FSS Secure Segment Program Flash Code Protection Size (FOR 128K and 256K DEVICES) X11 = No Secure program Flash segment Secure space is 8K IW less BS 110 = Standard security; secure program Flash segment starts at End of BS, ends at 0x003FFE 010 = High security; secure program Flash segment starts at End of BS, ends at 0x003FFE Secure space is 16K IW less BS 101 = Standard security; secure program Flash segment starts at End of BS, ends at 0x007FFE 001 = High security; secure program Flash segment starts at End of BS, ends at 0x007FFE Secure space is 32K IW less BS 100 = Standard security; secure program Flash segment starts at End of BS, ends at 0x00FFFE 000 = High security; secure program Flash segment starts at End of BS, ends at 0x00FFFE (FOR 64K DEVICES) X11 = No Secure program Flash segment Secure space is 4K IW less BS 110 = Standard security; secure program Flash segment starts at End of BS, ends at 0x001FFE 010 = High security; secure program Flash segment starts at End of BS, ends at 0x001FFE Secure space is 8K IW less BS 101 = Standard security; secure program Flash segment starts at End of BS, ends at 0x003FFE 001 = High security; secure program Flash segment starts at End of BS, ends at 0x003FFE Secure space is 16K IW less BS 100 = Standard security; secure program Flash segment starts at End of BS, ends at 007FFEh 000 = High security; secure program Flash segment starts at End of BS, ends at 0x007FFE RSS<1:0> FSS Secure Segment RAM Code Protection 11 = No Secure RAM defined 10 = Secure RAM is 256 Bytes less BS RAM 01 = Secure RAM is 2048 Bytes less BS RAM 00 = Secure RAM is 4096 Bytes less BS RAM GSS<1:0> FGS General Segment Code-Protect bit 11 = User program memory is not code-protected 10 = Standard security; general program Flash segment starts at End of SS, ends at EOM 0x = High security; general program Flash segment starts at End of SS, ends at EOM GWRP FGS General Segment Write-Protect bit 1 = User program memory is not write-protected 0 = User program memory is write-protected © 2009 Microchip Technology Inc. DS70286C-page 239

dsPIC33FJXXXGPX06/X08/X10 TABLE 22-2: dsPIC33FJXXXGPX06/X08/X10 CONFIGURATION BITS DESCRIPTION (CONTINUED) Bit Field Register Description IESO FOSCSEL Two-speed Oscillator Start-up Enable bit 1 = Start-up device with FRC, then automatically switch to the user-selected oscillator source when ready 0 = Start-up device with user-selected oscillator source FNOSC<2:0> FOSCSEL Initial Oscillator Source Selection bits 111 = Internal Fast RC (FRC) oscillator with postscaler 110 = Internal Fast RC (FRC) oscillator with divide-by-16 101 = LPRC oscillator 100 = Secondary (LP) oscillator 011 = Primary (XT, HS, EC) oscillator with PLL 010 = Primary (XT, HS, EC) oscillator 001 = Internal Fast RC (FRC) oscillator with PLL 000 = FRC oscillator FCKSM<1:0> FOSC Clock Switching Mode bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled OSCIOFNC FOSC OSC2 Pin Function bit (except in XT and HS modes) 1 = OSC2 is clock output 0 = OSC2 is general purpose digital I/O pin POSCMD<1:0> FOSC Primary Oscillator Mode Select bits 11 = Primary oscillator disabled 10 = HS Crystal Oscillator mode 01 = XT Crystal Oscillator mode 00 = EC (External Clock) mode FWDTEN FWDT Watchdog Timer Enable bit 1 = Watchdog Timer always enabled (LPRC oscillator cannot be disabled. Clearing the SWDTEN bit in the RCON register will have no effect.) 0 = Watchdog Timer enabled/disabled by user software (LPRC can be disabled by clearing the SWDTEN bit in the RCON register) WINDIS FWDT Watchdog Timer Window Enable bit 1 = Watchdog Timer in Non-Window mode 0 = Watchdog Timer in Window mode WDTPRE FWDT Watchdog Timer Prescaler bit 1 = 1:128 0 = 1:32 WDTPOST FWDT Watchdog Timer Postscaler bits 1111 = 1:32,768 1110 = 1:16,384 . . . 0001 = 1:2 0000 = 1:1 JTAGEN FICD JTAG Enable bits 1 = JTAG enabled 0 = JTAG disabled ICS<1:0> FICD ICD Communication Channel Select bits 11 = Communicate on PGEC1 and PGED1 10 = Communicate on PGEC2 and PGED2 01 = Communicate on PGEC3 and PGED3 00 = Reserved DS70286C-page 240 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 22.2 On-Chip Voltage Regulator 22.3 BOR: Brown-Out Reset All of the dsPIC33FJXXXGPX06/X08/X10 devices The BOR (Brown-out Reset) module is based on an power their core digital logic at a nominal 2.5V. This internal voltage reference circuit that monitors the may create an issue for designs that are required to regulated voltage VCAP/VDDCORE. The main purpose of operate at a higher typical voltage, such as 3.3V. To the BOR module is to generate a device Reset when a simplify system design, all devices in the brown-out condition occurs. Brown-out conditions are dsPIC33FJXXXGPX06/X08/X10 family incorporate an generally caused by glitches on the AC mains (i.e., on-chip regulator that allows the device to run its core missing portions of the AC cycle waveform due to bad logic from VDD. power transmission lines or voltage sags due to excessive current draw when a large inductive load is The regulator provides power to the core from the turned on). other VDD pins. The regulator requires that a low-ESR (less than 5 ohms) capacitor (such as A BOR will generate a Reset pulse which will reset the tantalum or ceramic) be connected to the device. The BOR will select the clock source, based on VCAP/VDDCORE pin (Figure22-1). This helps to the device Configuration bit values (FNOSC<2:0> and maintain the stability of the regulator. The POSCMD<1:0>). Furthermore, if an oscillator mode is recommended value for the filter capacitor is selected, the BOR will activate the Oscillator Start-up provided in Table25-13 of Section25.0 “Electrical Timer (OST). The system clock is held until OST Characteristics”. expires. If the PLL is used, then the clock will be held until the LOCK bit (OSCCON<5>) is ‘1’. Note: It is important for the low-ESR capacitor to be placed as close as possible to the Concurrently, the PWRT time-out (TPWRT) will be VCAP/VDDCORE pin. applied before the internal Reset is released. If TPWRT= 0 and a crystal oscillator is being used, then On a POR, it takes approximately 20μs for the on-chip a nominal delay of TFSCM = 100 is applied. The total voltage regulator to generate an output voltage. During delay in this case is TFSCM. this time, designated as TSTARTUP, code execution is disabled. TSTARTUP is applied every time the device The BOR Status bit (RCON<1>) will be set to indicate resumes operation after any power-down. that a BOR has occurred. The BOR circuit continues to operate while in Sleep or Idle modes and will reset the device should VDD fall below the BOR threshold FIGURE 22-1: CONNECTIONS FOR THE voltage. ON-CHIP VOLTAGE REGULATOR(1) 3.3V dsPIC33F VDD VCAP/VDDCORE CEFC VSS Note 1: These are typical operating voltages. Refer to TABLE 25-13: “Internal Voltage Regulator Specifications” located in Section25.1 “DC Characteristics” for the full operating ranges of VDD and VCAP/VDDCORE. 2: It is important for the low-ESR capacitor to be placed as close as possible to the VCAP/VDDCORE pin. © 2009 Microchip Technology Inc. DS70286C-page 241

dsPIC33FJXXXGPX06/X08/X10 22.4 Watchdog Timer (WDT) If the WDT is enabled, it will continue to run during Sleep or Idle modes. When the WDT time-out occurs, the For dsPIC33FJXXXGPX06/X08/X10 devices, the WDT device will wake the device and code execution will is driven by the LPRC oscillator. When the WDT is continue from where the PWRSAV instruction was enabled, the clock source is also enabled. executed. The corresponding SLEEP or IDLE bits The nominal WDT clock source from LPRC is 32kHz. (RCON<3,2>) will need to be cleared in software after the This feeds a prescaler and then can be configured for device wakes up. either 5-bit (divide-by-32) or 7-bit (divide-by-128) The WDT flag bit, WDTO (RCON<4>), is not automatically operation. The prescaler is set by the WDTPRE cleared following a WDT time-out. To detect subsequent Configuration bit. With a 32kHz input, the prescaler WDT events, the flag must be cleared in software. yields a nominal WDT time-out period (TWDT) of 1ms in 5-bit mode, or 4ms in 7-bit mode. Note: The CLRWDT and PWRSAV instructions clear the prescaler and postscaler counts A variable postscaler divides down the WDT prescaler when executed. output and allows for a wide range of time-out periods. The postscaler is controlled by the WDTPOST<3:0> The WDT is enabled or disabled by the FWDTEN Configuration bits (FWDT<3:0>) which allow the Configuration bit in the FWDT Configuration register. selection of a total of 16 settings, from 1:1 to 1:32,768. When the FWDTEN Configuration bit is set, the WDT is Using the prescaler and postscaler, time-out periods always enabled. ranging from 1ms to 131 seconds can be achieved. The WDT can be optionally controlled in software when The WDT, prescaler and postscaler are reset: the FWDTEN Configuration bit has been programmed to ‘0’. The WDT is enabled in software by setting the • On any device Reset SWDTEN control bit (RCON<5>). The SWDTEN • On the completion of a clock switch, whether control bit is cleared on any device Reset. The software invoked by software (i.e., setting the OSWEN bit WDT option allows the user to enable the WDT for after changing the NOSC bits) or by hardware critical code segments and disable the WDT during (i.e., Fail-Safe Clock Monitor) non-critical segments for maximum power savings. • When a PWRSAV instruction is executed (i.e., Sleep or Idle mode is entered) Note: If the WINDIS bit (FWDT<6>) is cleared, the CLRWDT instruction should be executed by • When the device exits Sleep or Idle mode to the application software only during the last resume normal operation 1/4 of the WDT period. This CLRWDT • By a CLRWDT instruction during normal execution window can be determined by using a timer. If a CLRWDT instruction is executed before this window, a WDT Reset occurs. FIGURE 22-2: WDT BLOCK DIAGRAM All Device Resets Transition to New Clock Source Exit Sleep or Idle Mode PWRSAV Instruction CLRWDT Instruction Watchdog Timer Sleep/Idle WDTPRE WDTPOST<3:0> SWDTEN WDT FWDTEN Wake-up RS RS 1 Prescaler Postscaler LPRC Clock (divide by N1) (divide by N2) WDT 0 Reset WINDIS WDT Window Select CLRWDT Instruction DS70286C-page 242 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 22.5 JTAG Interface 22.8 In-Circuit Debugger dsPIC33FJXXXGPX06/X08/X10 devices implement a When MPLAB® ICD 2 is selected as a debugger, the JTAG interface, which supports boundary scan device in-circuit debugging functionality is enabled. This testing, as well as in-circuit programming. Detailed function allows simple debugging functions when used information on the interface will be provided in future with MPLAB IDE. Debugging functionality is controlled revisions of the document. through the PGECx (Emulation/Debug Clock) and PGEDx (Emulation/Debug Data) pin functions. 22.6 Code Protection and Any one out of three pairs of debugging clock/data pins CodeGuard™ Security may be used: The dsPIC33F product families offer the advanced • PGEC1 and PGED1 implementation of CodeGuard™ Security. CodeGuard™ • PGEC2 and PGED2 Security enables multiple parties to securely share • PGEC3 and PGED3 resources (memory, interrupts and peripherals) on a To use the in-circuit debugger function of the device, single chip. This feature helps protect individual the design must implement ICSP connections to Intellectual Property in collaborative system designs. MCLR, VDD, VSS and the PGEDx/PGECx pin pair. In When coupled with software encryption libraries, addition, when the feature is enabled, some of the CodeGuard Security can be used to securely update resources are not available for general use. These Flash even when multiple IP are resident on the single resources include the first 80 bytes of data RAM and chip. The code protection features vary depending on two I/O pins. the actual dsPIC33F implemented. The following sections provide an overview of these features. The code protection features are controlled by the Configuration registers: FBS, FSS and FGS. Note: Refer to Section 23. “CodeGuard™ Security” (DS70199) in the “dsPIC33F Family Reference Manual” for further information on usage, configuration and operation of CodeGuard™ Security. 22.7 In-Circuit Serial Programming dsPIC33FJXXXGPX06/X08/X10 family digital signal controllers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for power, ground and the programming sequence. This allows customers to manufacture boards with unprogrammed devices and then program the digital signal controller just before shipping the product. This also allows the most recent firmware or a custom firmware, to be programmed. Please refer to the “dsPIC33F/PIC24H Flash Programming Specification” (DS70152) document for details about ICSP. Any one out of three pairs of programming clock/data pins may be used: • PGEC1 and PGED1 • PGEC2 and PGED2 • PGEC3 and PGED3 © 2009 Microchip Technology Inc. DS70286C-page 243

dsPIC33FJXXXGPX06/X08/X10 NOTES: DS70286C-page 244 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 23.0 INSTRUCTION SET SUMMARY Most bit-oriented instructions (including simple rotate/shift instructions) have two operands: Note: This data sheet summarizes the features • The W register (with or without an address of the dsPIC33FJXXXGPX06/X08/X10 modifier) or file register (specified by the value of family of devices. However, it is not ‘Ws’ or ‘f’) intended to be a comprehensive reference • The bit in the W register or file register source. To complement the information in (specified by a literal value or indirectly by the this data sheet, refer to the related section contents of register ‘Wb’) in the “dsPIC33F Family Reference Manual”, which is available from the The literal instructions that involve data movement may Microchip web site (www.microchip.com). use some of the following operands: The dsPIC33F instruction set is identical to that of the • A literal value to be loaded into a W register or file dsPIC30F. register (specified by the value of ‘k’) • The W register or file register where the literal Most instructions are a single program memory word value is to be loaded (specified by ‘Wb’ or ‘f’) (24 bits). Only three instructions require two program memory locations. However, literal instructions that involve arithmetic or logical operations use some of the following operands: Each single-word instruction is a 24-bit word, divided into an 8-bit opcode, which specifies the instruction • The first source operand which is a register ‘Wb’ type and one or more operands, which further specify without any address modifier the operation of the instruction. • The second source operand which is a literal The instruction set is highly orthogonal and is grouped value into five basic categories: • The destination of the result (only if not the same as the first source operand) which is typically a • Word or byte-oriented operations register ‘Wd’ with or without an address modifier • Bit-oriented operations The MAC class of DSP instructions may use some of the • Literal operations following operands: • DSP operations • The accumulator (A or B) to be used (required • Control operations operand) Table23-1 illustrates the general symbols used in • The W registers to be used as the two operands describing the instructions. • The X and Y address space prefetch operations The dsPIC33F instruction set summary in Table23-2 • The X and Y address space prefetch destinations provides all the instructions, along with the status flags • The accumulator write back destination affected by each instruction. The other DSP instructions do not involve any Most word or byte-oriented W register instructions multiplication and may include: (including barrel shift instructions) have three operands: • The accumulator to be used (required) • The first source operand which is typically a • The source or destination operand (designated as register ‘Wb’ without any address modifier Wso or Wdo, respectively) with or without an address modifier • The second source operand which is typically a register ‘Ws’ with or without an address modifier • The amount of shift specified by a W register ‘Wn’ or a literal value • The destination of the result which is typically a register ‘Wd’ with or without an address modifier The control instructions may use some of the following operands: However, word or byte-oriented file register instructions have two operands: • A program memory address • The file register specified by the value ‘f’ • The mode of the table read and table write instructions • The destination, which could either be the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2009 Microchip Technology Inc. DS70286C-page 245

dsPIC33FJXXXGPX06/X08/X10 All instructions are a single word, except for certain (unconditional/computed branch), indirect CALL/GOTO, double-word instructions, which were made all table reads and writes and RETURN/RETFIE double-word instructions so that all the required instructions, which are single-word instructions but take information is available in these 48 bits. In the second two or three cycles. Certain instructions that involve skip- word, the 8MSbs are ‘0’s. If this second word is ping over the subsequent instruction require either two executed as an instruction (by itself), it will execute as or three cycles if the skip is performed, depending on a NOP. whether the instruction being skipped is a single-word or two-word instruction. Moreover, double-word moves Most single-word instructions are executed in a single require two cycles. The double-word instructions instruction cycle, unless a conditional test is true, or the execute in two instruction cycles. program counter is changed as a result of the instruction. In these cases, the execution takes two Note: For more details on the instruction set, instruction cycles with the additional instruction cycle(s) refer to the “dsPIC30F/33F Programmer’s executed as a NOP. Notable exceptions are the BRA Reference Manual” (DS70157). TABLE 23-1: SYMBOLS USED IN OPCODE DESCRIPTIONS Field Description #text Means literal defined by “text” (text) Means “content of text” [text] Means “the location addressed by text” { } Optional field or operation <n:m> Register bit field .b Byte mode selection .d Double-Word mode selection .S Shadow register select .w Word mode selection (default) Acc One of two accumulators {A, B} AWB Accumulator write back destination address register ∈ {W13, [W13]+ = 2} bit4 4-bit bit selection field (used in word addressed instructions) ∈ {0...15} C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero Expr Absolute address, label or expression (resolved by the linker) f File register address ∈ {0x0000...0x1FFF} lit1 1-bit unsigned literal ∈ {0,1} lit4 4-bit unsigned literal ∈ {0...15} lit5 5-bit unsigned literal ∈ {0...31} lit8 8-bit unsigned literal ∈ {0...255} lit10 10-bit unsigned literal ∈ {0...255} for Byte mode, {0:1023} for Word mode lit14 14-bit unsigned literal ∈ {0...16384} lit16 16-bit unsigned literal ∈ {0...65535} lit23 23-bit unsigned literal ∈ {0...8388608}; LSb must be ‘0’ None Field does not require an entry, may be blank OA, OB, SA, SB DSP Status bits: AccA Overflow, AccB Overflow, AccA Saturate, AccB Saturate PC Program Counter Slit10 10-bit signed literal ∈ {-512...511} Slit16 16-bit signed literal ∈ {-32768...32767} Slit6 6-bit signed literal ∈ {-16...16} Wb Base W register ∈ {W0..W15} Wd Destination W register ∈ { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Wdo Destination W register ∈ { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Wm,Wn Dividend, Divisor working register pair (direct addressing) DS70286C-page 246 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 TABLE 23-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED) Field Description Wm*Wm Multiplicand and Multiplier working register pair for Square instructions ∈ {W4 * W4,W5 * W5,W6 * W6,W7 * W7} Wm*Wn Multiplicand and Multiplier working register pair for DSP instructions ∈ {W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7} Wn One of 16 working registers ∈ {W0..W15} Wnd One of 16 destination working registers ∈ {W0...W15} Wns One of 16 source working registers ∈ {W0...W15} WREG W0 (working register used in file register instructions) Ws Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } Wso Source W register ∈ { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } Wx X data space prefetch address register for DSP instructions ∈ {[W8]+ = 6, [W8]+ = 4, [W8]+ = 2, [W8], [W8]- = 6, [W8]- = 4, [W8]- = 2, [W9]+ = 6, [W9]+ = 4, [W9]+ = 2, [W9], [W9]- = 6, [W9]- = 4, [W9]- = 2, [W9 + W12], none} Wxd X data space prefetch destination register for DSP instructions ∈ {W4...W7} Wy Y data space prefetch address register for DSP instructions ∈ {[W10]+ = 6, [W10]+ = 4, [W10]+ = 2, [W10], [W10]- = 6, [W10]- = 4, [W10]- = 2, [W11]+ = 6, [W11]+ = 4, [W11]+ = 2, [W11], [W11]- = 6, [W11]- = 4, [W11]- = 2, [W11 + W12], none} Wyd Y data space prefetch destination register for DSP instructions ∈ {W4...W7} © 2009 Microchip Technology Inc. DS70286C-page 247

dsPIC33FJXXXGPX06/X08/X10 TABLE 23-2: INSTRUCTION SET OVERVIEW Base Assembly # of # of Status Flags Instr Assembly Syntax Description Mnemonic Words Cycles Affected # 1 ADD ADD Acc Add Accumulators 1 1 OA,OB,SA,SB ADD f f = f + WREG 1 1 C,DC,N,OV,Z ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z ADD Wso,#Slit4,Acc 16-bit Signed Add to Accumulator 1 1 OA,OB,SA,SB 2 ADDC ADDC f f = f + WREG + (C) 1 1 C,DC,N,OV,Z ADDC f,WREG WREG = f + WREG + (C) 1 1 C,DC,N,OV,Z ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C,DC,N,OV,Z ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C,DC,N,OV,Z ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C,DC,N,OV,Z 3 AND AND f f = f .AND. WREG 1 1 N,Z AND f,WREG WREG = f .AND. WREG 1 1 N,Z AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N,Z AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N,Z AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N,Z 4 ASR ASR f f = Arithmetic Right Shift f 1 1 C,N,OV,Z ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C,N,OV,Z ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C,N,OV,Z ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N,Z ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N,Z 5 BCLR BCLR f,#bit4 Bit Clear f 1 1 None BCLR Ws,#bit4 Bit Clear Ws 1 1 None 6 BRA BRA C,Expr Branch if Carry 1 1 (2) None BRA GE,Expr Branch if greater than or equal 1 1 (2) None BRA GEU,Expr Branch if unsigned greater than or equal 1 1 (2) None BRA GT,Expr Branch if greater than 1 1 (2) None BRA GTU,Expr Branch if unsigned greater than 1 1 (2) None BRA LE,Expr Branch if less than or equal 1 1 (2) None BRA LEU,Expr Branch if unsigned less than or equal 1 1 (2) None BRA LT,Expr Branch if less than 1 1 (2) None BRA LTU,Expr Branch if unsigned less than 1 1 (2) None BRA N,Expr Branch if Negative 1 1 (2) None BRA NC,Expr Branch if Not Carry 1 1 (2) None BRA NN,Expr Branch if Not Negative 1 1 (2) None BRA NOV,Expr Branch if Not Overflow 1 1 (2) None BRA NZ,Expr Branch if Not Zero 1 1 (2) None BRA OA,Expr Branch if Accumulator A overflow 1 1 (2) None BRA OB,Expr Branch if Accumulator B overflow 1 1 (2) None BRA OV,Expr Branch if Overflow 1 1 (2) None BRA SA,Expr Branch if Accumulator A saturated 1 1 (2) None BRA SB,Expr Branch if Accumulator B saturated 1 1 (2) None BRA Expr Branch Unconditionally 1 2 None BRA Z,Expr Branch if Zero 1 1 (2) None BRA Wn Computed Branch 1 2 None 7 BSET BSET f,#bit4 Bit Set f 1 1 None BSET Ws,#bit4 Bit Set Ws 1 1 None 8 BSW BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None 9 BTG BTG f,#bit4 Bit Toggle f 1 1 None BTG Ws,#bit4 Bit Toggle Ws 1 1 None DS70286C-page 248 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 TABLE 23-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Assembly Syntax Description Mnemonic Words Cycles Affected # 10 BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 None (2 or 3) BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 None (2 or 3) 11 BTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None (2 or 3) BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None (2 or 3) 12 BTST BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z 13 BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z 14 CALL CALL lit23 Call subroutine 2 2 None CALL Wn Call indirect subroutine 1 2 None 15 CLR CLR f f = 0x0000 1 1 None CLR WREG WREG = 0x0000 1 1 None CLR Ws Ws = 0x0000 1 1 None CLR Acc,Wx,Wxd,Wy,Wyd,AWB Clear Accumulator 1 1 OA,OB,SA,SB 16 CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO,Sleep 17 COM COM f f = f 1 1 N,Z COM f,WREG WREG = f 1 1 N,Z COM Ws,Wd Wd = Ws 1 1 N,Z 18 CP CP f Compare f with WREG 1 1 C,DC,N,OV,Z CP Wb,#lit5 Compare Wb with lit5 1 1 C,DC,N,OV,Z CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C,DC,N,OV,Z 19 CP0 CP0 f Compare f with 0x0000 1 1 C,DC,N,OV,Z CP0 Ws Compare Ws with 0x0000 1 1 C,DC,N,OV,Z 20 CPB CPB f Compare f with WREG, with Borrow 1 1 C,DC,N,OV,Z CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C,DC,N,OV,Z CPB Wb,Ws Compare Wb with Ws, with Borrow 1 1 C,DC,N,OV,Z (Wb – Ws – C) 21 CPSEQ CPSEQ Wb, Wn Compare Wb with Wn, skip if = 1 1 None (2 or 3) 22 CPSGT CPSGT Wb, Wn Compare Wb with Wn, skip if > 1 1 None (2 or 3) 23 CPSLT CPSLT Wb, Wn Compare Wb with Wn, skip if < 1 1 None (2 or 3) 24 CPSNE CPSNE Wb, Wn Compare Wb with Wn, skip if ≠ 1 1 None (2 or 3) 25 DAW DAW Wn Wn = decimal adjust Wn 1 1 C 26 DEC DEC f f = f – 1 1 1 C,DC,N,OV,Z DEC f,WREG WREG = f – 1 1 1 C,DC,N,OV,Z DEC Ws,Wd Wd = Ws – 1 1 1 C,DC,N,OV,Z 27 DEC2 DEC2 f f = f – 2 1 1 C,DC,N,OV,Z DEC2 f,WREG WREG = f – 2 1 1 C,DC,N,OV,Z DEC2 Ws,Wd Wd = Ws – 2 1 1 C,DC,N,OV,Z 28 DISI DISI #lit14 Disable Interrupts for k instruction cycles 1 1 None © 2009 Microchip Technology Inc. DS70286C-page 249

dsPIC33FJXXXGPX06/X08/X10 TABLE 23-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Assembly Syntax Description Mnemonic Words Cycles Affected # 29 DIV DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N,Z,C,OV DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N,Z,C,OV 30 DIVF DIVF Wm,Wn Signed 16/16-bit Fractional Divide 1 18 N,Z,C,OV 31 DO DO #lit14,Expr Do code to PC + Expr, lit14 + 1 times 2 2 None DO Wn,Expr Do code to PC + Expr, (Wn) + 1 times 2 2 None 32 ED ED Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance (no accumulate) 1 1 OA,OB,OAB, SA,SB,SAB 33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance 1 1 OA,OB,OAB, SA,SB,SAB 34 EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None 35 FBCL FBCL Ws,Wnd Find Bit Change from Left (MSb) Side 1 1 C 36 FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C 37 FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C 38 GOTO GOTO Expr Go to address 2 2 None GOTO Wn Go to indirect 1 2 None 39 INC INC f f = f + 1 1 1 C,DC,N,OV,Z INC f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z INC Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z 40 INC2 INC2 f f = f + 2 1 1 C,DC,N,OV,Z INC2 f,WREG WREG = f + 2 1 1 C,DC,N,OV,Z INC2 Ws,Wd Wd = Ws + 2 1 1 C,DC,N,OV,Z 41 IOR IOR f f = f .IOR. WREG 1 1 N,Z IOR f,WREG WREG = f .IOR. WREG 1 1 N,Z IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N,Z IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N,Z IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N,Z 42 LAC LAC Wso,#Slit4,Acc Load Accumulator 1 1 OA,OB,OAB, SA,SB,SAB 43 LNK LNK #lit14 Link Frame Pointer 1 1 None 44 LSR LSR f f = Logical Right Shift f 1 1 C,N,OV,Z LSR f,WREG WREG = Logical Right Shift f 1 1 C,N,OV,Z LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C,N,OV,Z LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N,Z LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N,Z 45 MAC MAC Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply and Accumulate 1 1 OA,OB,OAB, , SA,SB,SAB AWB MAC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square and Accumulate 1 1 OA,OB,OAB, SA,SB,SAB 46 MOV MOV f,Wn Move f to Wn 1 1 None MOV f Move f to f 1 1 N,Z MOV f,WREG Move f to WREG 1 1 N,Z MOV #lit16,Wn Move 16-bit literal to Wn 1 1 None MOV.b #lit8,Wn Move 8-bit literal to Wn 1 1 None MOV Wn,f Move Wn to f 1 1 None MOV Wso,Wdo Move Ws to Wd 1 1 None MOV WREG,f Move WREG to f 1 1 N,Z MOV.D Wns,Wd Move Double from W(ns):W(ns + 1) to Wd 1 2 None MOV.D Ws,Wnd Move Double from Ws to W(nd + 1):W(nd) 1 2 None 47 MOVSAC MOVSAC Acc,Wx,Wxd,Wy,Wyd,AWB Prefetch and store accumulator 1 1 None DS70286C-page 250 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 TABLE 23-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Assembly Syntax Description Mnemonic Words Cycles Affected # 48 MPY MPY Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB, Wm*Wn,Acc,Wx,Wxd,Wy,Wyd SA,SB,SAB MPY Square Wm to Accumulator 1 1 OA,OB,OAB, Wm*Wm,Acc,Wx,Wxd,Wy,Wyd SA,SB,SAB 49 MPY.N MPY.N -(Multiply Wm by Wn) to Accumulator 1 1 None Wm*Wn,Acc,Wx,Wxd,Wy,Wyd 50 MSC MSC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Multiply and Subtract from Accumulator 1 1 OA,OB,OAB, , SA,SB,SAB AWB 51 MUL MUL.SS Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * signed(Ws) 1 1 None MUL.SU Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws) 1 1 None MUL.US Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws) 1 1 None MUL.UU Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * 1 1 None unsigned(Ws) MUL.SU Wb,#lit5,Wnd {Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5) 1 1 None MUL.UU Wb,#lit5,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * 1 1 None unsigned(lit5) MUL f W3:W2 = f * WREG 1 1 None 52 NEG NEG Acc Negate Accumulator 1 1 OA,OB,OAB, SA,SB,SAB NEG f f = f + 1 1 1 C,DC,N,OV,Z NEG f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z NEG Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z 53 NOP NOP No Operation 1 1 None NOPR No Operation 1 1 None 54 POP POP f Pop f from Top-of-Stack (TOS) 1 1 None POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None POP.D Wnd Pop from Top-of-Stack (TOS) to 1 2 None W(nd):W(nd + 1) POP.S Pop Shadow Registers 1 1 All 55 PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None PUSH.D Wns Push W(ns):W(ns + 1) to Top-of-Stack (TOS) 1 2 None PUSH.S Push Shadow Registers 1 1 None 56 PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO,Sleep 57 RCALL RCALL Expr Relative Call 1 2 None RCALL Wn Computed Call 1 2 None 58 REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None 59 RESET RESET Software device Reset 1 1 None 60 RETFIE RETFIE Return from interrupt 1 3 (2) None 61 RETLW RETLW #lit10,Wn Return with literal in Wn 1 3 (2) None 62 RETURN RETURN Return from Subroutine 1 3 (2) None 63 RLC RLC f f = Rotate Left through Carry f 1 1 C,N,Z RLC f,WREG WREG = Rotate Left through Carry f 1 1 C,N,Z RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C,N,Z 64 RLNC RLNC f f = Rotate Left (No Carry) f 1 1 N,Z RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N,Z RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N,Z 65 RRC RRC f f = Rotate Right through Carry f 1 1 C,N,Z RRC f,WREG WREG = Rotate Right through Carry f 1 1 C,N,Z RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C,N,Z © 2009 Microchip Technology Inc. DS70286C-page 251

dsPIC33FJXXXGPX06/X08/X10 TABLE 23-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly # of # of Status Flags Instr Assembly Syntax Description Mnemonic Words Cycles Affected # 66 RRNC RRNC f f = Rotate Right (No Carry) f 1 1 N,Z RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z 67 SAC SAC Acc,#Slit4,Wdo Store Accumulator 1 1 None SAC.R Acc,#Slit4,Wdo Store Rounded Accumulator 1 1 None 68 SE SE Ws,Wnd Wnd = sign-extended Ws 1 1 C,N,Z 69 SETM SETM f f = 0xFFFF 1 1 None SETM WREG WREG = 0xFFFF 1 1 None SETM Ws Ws = 0xFFFF 1 1 None 70 SFTAC SFTAC Acc,Wn Arithmetic Shift Accumulator by (Wn) 1 1 OA,OB,OAB, SA,SB,SAB SFTAC Acc,#Slit6 Arithmetic Shift Accumulator by Slit6 1 1 OA,OB,OAB, SA,SB,SAB 71 SL SL f f = Left Shift f 1 1 C,N,OV,Z SL f,WREG WREG = Left Shift f 1 1 C,N,OV,Z SL Ws,Wd Wd = Left Shift Ws 1 1 C,N,OV,Z SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N,Z SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N,Z 72 SUB SUB Acc Subtract Accumulators 1 1 OA,OB,OAB, SA,SB,SAB SUB f f = f – WREG 1 1 C,DC,N,OV,Z SUB f,WREG WREG = f – WREG 1 1 C,DC,N,OV,Z SUB #lit10,Wn Wn = Wn – lit10 1 1 C,DC,N,OV,Z SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C,DC,N,OV,Z SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C,DC,N,OV,Z 73 SUBB SUBB f f = f – WREG – (C) 1 1 C,DC,N,OV,Z SUBB f,WREG WREG = f – WREG – (C) 1 1 C,DC,N,OV,Z SUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 C,DC,N,OV,Z SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C,DC,N,OV,Z SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 C,DC,N,OV,Z 74 SUBR SUBR f f = WREG – f 1 1 C,DC,N,OV,Z SUBR f,WREG WREG = WREG – f 1 1 C,DC,N,OV,Z SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C,DC,N,OV,Z SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 C,DC,N,OV,Z 75 SUBBR SUBBR f f = WREG – f – (C) 1 1 C,DC,N,OV,Z SUBBR f,WREG WREG = WREG – f – (C) 1 1 C,DC,N,OV,Z SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C,DC,N,OV,Z SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 C,DC,N,OV,Z 76 SWAP SWAP.b Wn Wn = nibble swap Wn 1 1 None SWAP Wn Wn = byte swap Wn 1 1 None 77 TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 None 78 TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None 79 TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None 80 TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None 81 ULNK ULNK Unlink Frame Pointer 1 1 None 82 XOR XOR f f = f .XOR. WREG 1 1 N,Z XOR f,WREG WREG = f .XOR. WREG 1 1 N,Z XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N,Z XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N,Z XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N,Z 83 ZE ZE Ws,Wnd Wnd = Zero-extend Ws 1 1 C,Z,N DS70286C-page 252 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 24.0 DEVELOPMENT SUPPORT 24.1 MPLAB Integrated Development Environment Software The PIC® microcontrollers are supported with a full range of hardware and software development tools: The MPLAB IDE software brings an ease of software • Integrated Development Environment development previously unseen in the 8/16-bit - MPLAB® IDE Software microcontroller market. The MPLAB IDE is a Windows® operating system-based application that contains: • Assemblers/Compilers/Linkers • A single graphical interface to all debugging tools - MPASMTM Assembler - Simulator - MPLAB C18 and MPLAB C30 C Compilers - Programmer (sold separately) - MPLINKTM Object Linker/ MPLIBTM Object Librarian - Emulator (sold separately) - MPLAB ASM30 Assembler/Linker/Library - In-Circuit Debugger (sold separately) • Simulators • A full-featured editor with color-coded context - MPLAB SIM Software Simulator • A multiple project manager • Emulators • Customizable data windows with direct edit of contents - MPLAB ICE 2000 In-Circuit Emulator • High-level source code debugging - MPLAB REAL ICE™ In-Circuit Emulator • Visual device initializer for easy register • In-Circuit Debugger initialization - MPLAB ICD 2 • Mouse over variable inspection • Device Programmers • Drag and drop variables from source to watch - PICSTART® Plus Development Programmer windows - MPLAB PM3 Device Programmer • Extensive on-line help - PICkit™ 2 Development Programmer • Integration of select third party tools, such as • Low-Cost Demonstration and Development HI-TECH Software C Compilers and IAR Boards and Evaluation Kits C Compilers The MPLAB IDE allows you to: • Edit your source files (either assembly or C) • One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) • Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. © 2009 Microchip Technology Inc. DS70286C-page 253

dsPIC33FJXXXGPX06/X08/X10 24.2 MPASM Assembler 24.5 MPLAB ASM30 Assembler, Linker and Librarian The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. MPLAB ASM30 Assembler produces relocatable The MPASM Assembler generates relocatable object machine code from symbolic assembly language for files for the MPLINK Object Linker, Intel® standard HEX dsPIC30F devices. MPLAB C30 C Compiler uses the files, MAP files to detail memory usage and symbol assembler to produce its object file. The assembler reference, absolute LST files that contain source lines generates relocatable object files that can then be and generated machine code and COFF files for archived or linked with other relocatable object files and debugging. archives to create an executable file. Notable features of the assembler include: The MPASM Assembler features include: • Support for the entire dsPIC30F instruction set • Integration into MPLAB IDE projects • Support for fixed-point and floating-point data • User-defined macros to streamline • Command line interface assembly code • Rich directive set • Conditional assembly for multi-purpose source files • Flexible macro language • Directives that allow complete control over the • MPLAB IDE compatibility assembly process 24.6 MPLAB SIM Software Simulator 24.3 MPLAB C18 and MPLAB C30 The MPLAB SIM Software Simulator allows code C Compilers development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an The MPLAB C18 and MPLAB C30 Code Development instruction level. On any given instruction, the data Systems are complete ANSI C compilers for areas can be examined or modified and stimuli can be Microchip’s PIC18 and PIC24 families of applied from a comprehensive stimulus controller. microcontrollers and the dsPIC30 and dsPIC33 family Registers can be logged to files for further run-time of digital signal controllers. These compilers provide analysis. The trace buffer and logic analyzer display powerful integration capabilities, superior code extend the power of the simulator to record and track optimization and ease of use not found with other program execution, actions on I/O, most peripherals compilers. and internal registers. For easy source level debugging, the compilers provide The MPLAB SIM Software Simulator fully supports symbol information that is optimized to the MPLAB IDE symbolic debugging using the MPLAB C18 and debugger. MPLAB C30 CCompilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator 24.4 MPLINK Object Linker/ offers the flexibility to develop and debug code outside MPLIB Object Librarian of the hardware laboratory environment, making it an excellent, economical software development tool. The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction DS70286C-page 254 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 24.7 MPLAB ICE 2000 24.9 MPLAB ICD 2 In-Circuit Debugger High-Performance Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a In-Circuit Emulator powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed The MPLAB ICE 2000 In-Circuit Emulator is intended USB interface. This tool is based on the Flash PIC to provide the product development engineer with a MCUs and can be used to develop for these and other complete microcontroller design tool set for PIC PIC MCUs and dsPIC DSCs. The MPLAB ICD2 utilizes microcontrollers. Software control of the MPLAB ICE the in-circuit debugging capability built into theFlash 2000 In-Circuit Emulator is advanced by the MPLAB devices. This feature, along with Microchip’s In-Circuit Integrated Development Environment, which allows Serial ProgrammingTM (ICSPTM) protocol, offers editing, building, downloading and source debugging cost-effective, in-circuit Flash debugging from the from a single environment. graphical user interface of the MPLAB Integrated The MPLAB ICE 2000 is a full-featured emulator Development Environment. This enables a designer to system with enhanced trace, trigger and data develop and debug source code by setting breakpoints, monitoring features. Interchangeable processor single stepping and watching variables, and CPU modules allow the system to be easily reconfigured for status and peripheral registers. Running at full speed emulation of different processors. The architecture of enables testing hardware and applications in real the MPLAB ICE 2000 In-Circuit Emulator allows time. MPLAB ICD2 also serves as a development expansion to support new PIC microcontrollers. programmer for selected PIC devices. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with 24.10 MPLAB PM3 Device Programmer advanced features that are typically found on more The MPLAB PM3 Device Programmer is a universal, expensive development tools. The PC platform and Microsoft® Windows® 32-bit operating system were CE compliant device programmer with programmable chosen to best make these features available in a voltage verification at VDDMIN and VDDMAX for simple, unified application. maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support 24.8 MPLAB REAL ICE In-Circuit various package types. The ICSP cable assembly is Emulator System included as a standard item. In Stand-Alone mode, the MPLAB REAL ICE In-Circuit Emulator System is MPLAB PM3 Device Programmer can read, verify and Microchip’s next generation high-speed emulator for program PIC devices without a PC connection. It can Microchip Flash DSC and MCU devices. It debugs and also set code protection in this mode. The MPLAB PM3 programs PIC® Flash MCUs and dsPIC® Flash DSCs connects to the host PC via an RS-232 or USB cable. with the easy-to-use, powerful graphical user interface of The MPLAB PM3 has high-speed communications and the MPLAB Integrated Development Environment (IDE), optimized algorithms for quick programming of large included with each kit. memory devices and incorporates an SD/MMC card for file storage and secure data applications. The MPLAB REAL ICE probe is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with the popular MPLAB ICD 2 system (RJ11) or with the new high-speed, noise tolerant, Low-Voltage Differential Signal (LVDS) interconnection (CAT5). MPLAB REAL ICE is field upgradeable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added, such as software breakpoints and assembly code trace. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. © 2009 Microchip Technology Inc. DS70286C-page 255

dsPIC33FJXXXGPX06/X08/X10 24.11 PICSTART Plus Development 24.13 Demonstration, Development and Programmer Evaluation Boards The PICSTART Plus Development Programmer is an A wide variety of demonstration, development and easy-to-use, low-cost, prototype programmer. It evaluation boards for various PIC MCUs and dsPIC connects to the PC via a COM (RS-232) port. MPLAB DSCs allows quick application development on fully Integrated Development Environment software makes functional systems. Most boards include prototyping using the programmer simple and efficient. The areas for adding custom circuitry and provide application PICSTART Plus Development Programmer supports firmware and source code for examination and most PIC devices in DIP packages up to 40 pins. modification. Larger pin count devices, such as the PIC16C92X and The boards support a variety of features, including LEDs, PIC17C76X, may be supported with an adapter socket. temperature sensors, switches, speakers, RS-232 The PICSTART Plus Development Programmer is CE interfaces, LCD displays, potentiometers and additional compliant. EEPROM memory. The demonstration and development boards can be 24.12 PICkit 2 Development Programmer used in teaching environments, for prototyping custom The PICkit 2 Development Programmer is a low-cost circuits and for learning about various microcontroller programmer and selected Flash device debugger with applications. an easy-to-use interface for programming many of In addition to the PICDEM™ and dsPICDEM™ Microchip’s baseline, mid-range and PIC18F families of demonstration/development board series of circuits, Flash memory microcontrollers. The PICkit 2 Starter Kit Microchip has a line of evaluation kits and includes a prototyping development board, twelve demonstration software for analog filter design, sequential lessons, software and HI-TECH’s PICC™ KEELOQ® security ICs, CAN, IrDA®, PowerSmart Lite C compiler, and is designed to help get up to speed battery management, SEEVAL® evaluation system, quickly using PIC microcontrollers. The kit provides Sigma-Delta ADC, flow rate sensing, plus many more. everything needed to program, evaluate and develop Check the Microchip web page (www.microchip.com) applications using Microchip’s powerful, mid-range for the complete list of demonstration, development Flash memory family of microcontrollers. and evaluation kits. DS70286C-page 256 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 25.0 ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC33FJXXXGPX06/X08/X10 electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the dsPIC33FJXXXGPX06/X08/X10 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied. Absolute Maximum Ratings(1) Ambient temperature under bias...............................................................................................................-40°C to +85°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any combined analog and digital pin and MCLR, with respect to VSS .........................-0.3V to (VDD + 0.3V) Voltage on any digital-only pin with respect to VSS .................................................................................. -0.3V to +5.6V Voltage on VCAP/VDDCORE with respect to VSS ....................................................................................... 2.25V to 2.75V Maximum current out of VSS pin...........................................................................................................................300 mA Maximum current into VDD pin(2)...........................................................................................................................250 mA Maximum output current sunk by any I/O pin(3)........................................................................................................4 mA Maximum output current sourced by any I/O pin(3)...................................................................................................4 mA Maximum current sunk by all ports.......................................................................................................................200 mA Maximum current sourced by all ports(2)...............................................................................................................200 mA Note1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2: Maximum allowable current is a function of device maximum power dissipation (see Table25-2). 3: Exceptions are CLKOUT, which is able to sink/source 25 mA, and the VREF+, VREF-, SCLx, SDAx, PGECx and PGEDx pins, which are able to sink/source 12 mA. © 2009 Microchip Technology Inc. DS70286C-page 257

dsPIC33FJXXXGPX06/X08/X10 25.1 DC Characteristics TABLE 25-1: OPERATING MIPS VS. VOLTAGE Max MIPS VDD Range Temp Range Characteristic (in Volts) (in °C) dsPIC33FJXXXGPX06/X08/X10 DC5 3.0-3.6V -40°C to +85°C 40 TABLE 25-2: THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit dsPIC33FJXXXGPX06/X08/X10 Operating Junction Temperature Range TJ -40 — +125 °C Operating Ambient Temperature Range TA -40 — +85 °C Power Dissipation: Internal chip power dissipation: PINT = VDD x (IDD - Σ IOH) PD PINT + PI/O W I/O Pin Power Dissipation: I/O = Σ ({VDD - VOH} x IOH) + Σ (VOL x IOL) Maximum Allowed Power Dissipation PDMAX (TJ - TA)/θJA W TABLE 25-3: THERMAL PACKAGING CHARACTERISTICS Characteristic Symbol Typ Max Unit Notes θ Package Thermal Resistance, 100-pin TQFP (14x14x1 mm) JA 40 — °C/W 1 θ Package Thermal Resistance, 100-pin TQFP (12x12x1 mm) JA 40 — °C/W 1 θ Package Thermal Resistance, 80-pin TQFP (12x12x1 mm) JA 40 — °C/W 1 θ Package Thermal Resistance, 64-pin TQFP (10x10x1 mm) JA 40 — °C/W 1 θ Note 1: Junction to ambient thermal resistance, Theta-JA ( JA) numbers are achieved by package simulations. DS70286C-page 258 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 TABLE 25-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V DC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C≤ TA ≤ +85°C for Industrial Param Symbol Characteristic Min Typ(1) Max Units Conditions No. Operating Voltage DC10 Supply Voltage VDD — 3.0 — 3.6 V — DC12 VDR RAM Data Retention Voltage(2) 1.8 — — V — DC16 VPOR VDD Start Voltage(4) — — VSS V — to ensure internal Power-on Reset signal DC17 SVDD VDD Rise Rate 0.03 — — V/ms 0-3.0V in 0.1s to ensure internal Power-on Reset signal DC18 VCORE VDD Core(3) 2.25 — 2.75 V Voltage is dependent on Internal regulator voltage load, temperature and VDD Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 2: This is the limit to which VDD can be lowered without losing RAM data. 3: These parameters are characterized but not tested in manufacturing. 4: VDD voltage must remain at VSS for a minimum of 200 μs to ensure POR. © 2009 Microchip Technology Inc. DS70286C-page 259

dsPIC33FJXXXGPX06/X08/X10 TABLE 25-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 3.0V to 3.6V DC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C≤ TA ≤ +85°C for Industrial Parameter Typical(1) Max Units Conditions No. Operating Current (IDD)(2) DC20d 27 30 mA -40°C DC20a 27 30 mA +25°C 3.3V 10 MIPS DC20b 27 30 mA +85°C DC21d 36 40 mA -40°C DC21a 37 40 mA +25°C 3.3V 16 MIPS DC21b 38 45 mA +85°C DC22d 43 50 mA -40°C DC22a 46 50 mA +25°C 3.3V 20 MIPS DC22b 46 55 mA +85°C DC23d 65 70 mA -40°C DC23a 65 70 mA +25°C 3.3V 30 MIPS DC23b 65 70 mA +85°C DC24d 84 90 mA -40°C DC24a 84 90 mA +25°C 3.3V 40 MIPS DC24b 84 90 mA +85°C Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1 driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VSS. MCLR = VDD, WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are operational. No peripheral modules are operating; however, every peripheral is being clocked (PMD bits are all zeroed). DS70286C-page 260 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 TABLE 25-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 3.0V to 3.6V DC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C≤ TA ≤ +85°C for Industrial Parameter Typical(1) Max Units Conditions No. Idle Current (IIDLE): Core OFF Clock ON Base Current(2) DC40d 3 25 mA -40°C DC40a 3 25 mA +25°C 10 MIPS 3.3V DC40b 3 25 mA +85°C DC41d 4 25 mA -40°C DC41a 5 25 mA +25°C 3.3V 16 MIPS DC41b 6 25 mA +85°C DC42d 8 25 mA -40°C DC42a 9 25 mA +25°C 3.3V 20 MIPS DC42b 10 25 mA +85°C DC43a 15 25 mA +25°C DC43d 15 25 mA -40°C 3.3V 30 MIPS DC43b 15 25 mA +85°C DC44d 16 25 mA -40°C DC44a 16 25 mA +25°C 3.3V 40 MIPS DC44b 16 25 mA +85°C Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. 2: Base IIDLE current is measured with core off, clock on and all modules turned off. Peripheral Module Disable SFR registers are zeroed. All I/O pins are configured as inputs and pulled to VSS. © 2009 Microchip Technology Inc. DS70286C-page 261

dsPIC33FJXXXGPX06/X08/X10 TABLE 25-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 3.0V to 3.6V DC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C≤ TA ≤ +85°C for Industrial Parameter Typical(1) Max Units Conditions No. Power-Down Current (IPD)(2) DC60d 55 500 μA -40°C DC60a 211 500 μA +25°C 3.3V Base Power-Down Current(3,4) DC60b 244 500 μA +85°C DC61d 8 13 μA -40°C DC61a 10 15 μA +25°C 3.3V Watchdog Timer Current: ΔIWDT(3) DC61b 12 20 μA +85°C Note 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated. 2: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled to VSS. WDT, etc., are all switched off and VREGS (RCON<8>) = 1. 3: The Δ current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. 4: These currents are measured on the device containing the most memory in this family. TABLE 25-8: DC CHARACTERISTICS: DOZE CURRENT (IDOZE) Standard Operating Conditions: 3.0V to 3.6V DC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C≤ TA ≤ +85°C for Industrial Parameter Typical(1) Max Doze Ratio Units Conditions No. DC73a 11 35 1:2 mA DC73f 11 30 1:64 mA -40°C 3.3V 40 MIPS DC73g 11 30 1:128 mA DC70a 42 50 1:2 mA DC70f 26 30 1:64 mA +25°C 3.3V 40 MIPS DC70g 25 30 1:128 mA DC71a 41 50 1:2 mA DC71f 25 30 1:64 mA +85°C 3.3V 40 MIPS DC71g 24 30 1:128 mA Note 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated. DS70286C-page 262 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 TABLE 25-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V DC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C≤ TA≤ +85°C for Industrial Param Symbol Characteristic Min Typ(1) Max Units Conditions No. VIL Input Low Voltage DI10 I/O pins VSS — 0.2VDD V DI15 MCLR VSS — 0.2VDD V DI16 I/O Pins with OSC1 or SOSCI VSS — 0.2VDD V DI18 I/O Pins with I2C VSS — 0.3 VDD V SMbus disabled DI19 I/O Pins with I2C VSS — 0.2 VDD V SMbus enabled VIH Input High Voltage DI20 I/O Pins Not 5V Tolerant(4) 0.8VDD — VDD V I/O Pins 5V Tolerant(4) 0.8VDD — 5.5 V I/O Pins Not 5V Tolerant(4) 2 — VDD V VDD = 3.3V I/O Pins 5V Tolerant(4) 2 — 5.5 V VDD = 3.3V DI26 I/O Pins with OSC1 or SOSCI 0.7VDD — VDD V DI28 I/O Pins with I2C 0.7VDD — 5.5 V SMbus disabled DI29 I/O Pins with I2C 0.8VDD — 5.5 V SMbus enabled ICNPU CNx Pull-up Current DI30 50 250 400 μA VDD = 3.3V, VPIN = VSS IIL Input Leakage Current(2,3) DI50 I/O Pins — — ±2 μA VSS ≤ VPIN ≤ VDD, Pin at high-impedance DI51 I/O Pins Not 5V Tolerant(4) — — ±2 μA VSS ≤ VPIN ≤ VDD, Pin at high-impedance DI51a I/O Pins Not 5V Tolerant(4) — — ±2 μA Shared with external reference pins DI51b I/O Pins Not 5V Tolerant(4) — — ±3.5 μA VSS ≤ VPIN ≤ VDD, Pin at high-impedance DI51c I/O Pins Not 5V Tolerant(4) — — ±8 μA Analog pins shared with external reference pins DI55 MCLR — — ±2 μA VSS ≤ VPIN ≤ VDD DI56 OSC1 — — ±2 μA VSS ≤ VPIN ≤ VDD, XT and HS modes Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: See “Pin Diagrams” for a list of 5V tolerant pins. © 2009 Microchip Technology Inc. DS70286C-page 263

dsPIC33FJXXXGPX06/X08/X10 TABLE 25-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V DC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C≤ TA ≤ +85°C for Industrial Param Symbol Characteristic Min Typ Max Units Conditions No. VOL Output Low Voltage DO10 I/O ports — — 0.4 V IOL = 2 mA, VDD = 3.3V DO16 OSC2/CLKO — — 0.4 V IOL = 2 mA, VDD = 3.3V VOH Output High Voltage DO20 I/O ports 2.40 — — V IOH = -2.3 mA, VDD = 3.3V DO26 OSC2/CLKO 2.41 — — V IOH = -1.3 mA, VDD = 3.3V TABLE 25-11: ELECTRICAL CHARACTERISTICS: BOR Standard Operating Conditions: 3.0V to 3.6V DC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C≤ TA ≤ +85°C for Industrial Param Symbol Characteristic Min(1) Typ Max(1) Units Conditions No. BO10 VBOR BOR Event on VDD transition 2.40 — 2.55 V — high-to-low BOR event is tied to VDD core voltage decrease Note 1: Parameters are for design guidance only and are not tested in manufacturing. DS70286C-page 264 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 TABLE 25-12: DC CHARACTERISTICS: PROGRAM MEMORY Standard Operating Conditions: 3.0V to 3.6V DC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C≤ TA ≤ +85°C for Industrial Param Symbol Characteristic Min Typ(1) Max Units Conditions No. Program Flash Memory D130a EP Cell Endurance 100 1000 — E/W See Note 2 D131 VPR VDD for Read VMIN — 3.6 V VMIN = Minimum operating voltage D132B VPEW VDD for Self-Timed Write VMIN — 3.6 V VMIN = Minimum operating voltage D134 TRETD Characteristic Retention 20 — — Year Provided no other specifications are violated D135 IDDP Supply Current during — 10 — mA Programming D136a TRW Row Write Time 1.32 — 1.74 ms TRW = 11064 FRC cycles, See Note 2 D137a TPE Page Erase Time 20.1 — 26.5 ms TPE = 168517 FRC cycles, See Note 2 D138a TWW Word Write Cycle Time 42.3 — 55.9 µs TWW = 355 FRC cycles, See Note 2 Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 2: Other conditions: FRC = 7.37 MHz, TUN<5:0> = b'011111 (for Min), TUN<5:0> = b'100000 (for Max). This parameter depends on the FRC accuracy (see Table25-19) and the value of the FRC Oscillator Tuning register (see Register9-4). For complete details on calculating the Minimum and Maximum time see Section5.3 “Programming Operations”. TABLE 25-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C≤ TA ≤ +85°C for Industrial Param Symbol Characteristics Min Typ Max Units Comments No. CEFC External Filter Capacitor 4.7 10 — μF Capacitor must be low Value series resistance (< 5 ohms) © 2009 Microchip Technology Inc. DS70286C-page 265

dsPIC33FJXXXGPX06/X08/X10 25.2 AC Characteristics and Timing Parameters The information contained in this section defines dsPIC33FJXXXGPX06/X08/X10 AC characteristics and timing parameters. TABLE 25-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial Operating voltage VDD range as described in Section25.0 “Electrical Characteristics”. FIGURE 25-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 - for all pins except OSC2 Load Condition 2 - for OSC2 VDD/2 RL Pin CL VSS Pin CL RL = 464Ω CL = 50 pF for all pins except OSC2 VSS 15 pF for OSC2 output TABLE 25-15: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS Param Symbol Characteristic Min Typ Max Units Conditions No. DO50 COSC2 OSC2/SOSC2 pin — — 15 pF In XT and HS modes when external clock is used to drive OSC1 DO56 CIO All I/O pins and OSC2 — — 50 pF EC mode DO58 CB SCLx, SDAx — — 400 pF In I2C™ mode DS70286C-page 266 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 FIGURE 25-2: EXTERNAL CLOCK TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 OS20 OS30 OS30 OS31 OS31 OS25 CLKO OS41 OS40 TABLE 25-16: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C≤ TA ≤ +85°C for Industrial Param Sym Characteristic Min Typ(1) Max Units Conditions No. bol OS10 FIN External CLKI Frequency DC — 40 MHz EC (External clocks allowed only in EC and ECPLL modes) Oscillator Crystal Frequency 3.5 — 10 MHz XT 10 — 40 MHz HS — — 33 kHz SOSC OS20 TOSC TOSC = 1/FOSC 12.5 — DC ns — OS25 TCY Instruction Cycle Time(2) 25 — DC ns — OS30 TosL, External Clock in (OSC1) 0.375 x TOSC — 0.625 x TOSC ns EC TosH High or Low Time OS31 TosR, External Clock in (OSC1) — — 20 ns EC TosF Rise or Fall Time OS40 TckR CLKO Rise Time(3) — 5.2 — ns — OS41 TckF CLKO Fall Time(3) — 5.2 — ns — OS42 GM External Oscillator 14 16 18 mA/V VDD = 3.3V Transconductance(4) TA = +25ºC Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 2: Instruction cycle period (TCY) equals two times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. 3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin. 4: Data for this parameter is Preliminary. This parameter is characterized, but not tested in manufacturing. © 2009 Microchip Technology Inc. DS70286C-page 267

dsPIC33FJXXXGPX06/X08/X10 TABLE 25-17: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial Param Symbol Characteristic Min Typ(1) Max Units Conditions No. OS50 FPLLI PLL Voltage Controlled 0.8 — 8.0 MHz ECPLL, HSPLL, XTPLL Oscillator (VCO) Input modes Frequency Range(2) OS51 FSYS On-Chip VCO System 100 — 200 MHz — Frequency OS52 TLOCK PLL Start-up Time (Lock Time) 0.9 1.5 3.1 ms — OS53 DCLK CLKO Stability (Jitter) -3.0 0.5 3.0 % Measured over 100 ms period Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. TABLE 25-18: AC CHARACTERISTICS: INTERNAL FRC ACCURACY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial Param Characteristic Min Typ Max Units Conditions No. Internal FRC Accuracy @ FRC Frequency = 7.37 MHz(1,2) F20 FRC -2 — +2 % -40°C ≤ TA ≤ +85°C VDD = 3.0-3.6V Note 1: Frequency calibrated at 25°C and 3.3V. TUN bits can be used to compensate for temperature drift. 2: FRC is set to initial frequency of 7.37 MHz (±2%) at 25°C FRC. TABLE 25-19: INTERNAL LPRC ACCURACY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C≤ TA ≤ +85°C for Industrial Param Characteristic Min Typ Max Units Conditions No. LPRC @ 32.768 kHz(1) F21 LPRC -20 ±6 +20 % -40°C ≤ TA ≤ +85°C VDD = 3.0-3.6V Note 1: Change of LPRC frequency as VDD changes. DS70286C-page 268 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 FIGURE 25-3: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin Old Value New Value (Output) DO31 DO32 Note: Refer to Figure25-1 for load conditions. TABLE 25-20: I/O TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C≤ TA ≤ +85°C for Industrial Param Symbol Characteristic Min Typ(1) Max Units Conditions No. DO31 TIOR Port Output Rise Time — 10 25 ns — DO32 TIOF Port Output Fall Time — 10 25 ns — DI35 TINP INTx Pin High or Low Time (output) 20 — — ns — DI40 TRBP CNx High or Low Time (input) 2 — — TCY — Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. © 2009 Microchip Technology Inc. DS70286C-page 269

dsPIC33FJXXXGPX06/X08/X10 FIGURE 25-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS VDD SY12 MCLR Internal SY10 POR SY11 PWRT Time-out SY30 OSC Time-out Internal Reset Watchdog Timer Reset SY20 SY13 SY13 I/O Pins SY35 FSCM Delay Note: Refer to Figure25-1 for load conditions. DS70286C-page 270 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 T A B LE 25-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C≤ TA ≤ +85°C for Industrial Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SY10 TMCL MCLR Pulse-Width (low) 2 — — μs -40°C to +85°C SY11 TPWRT Power-up Timer Period — 2 — ms -40°C to +85°C — 4 — User programmable — 8 — — 16 — — 32 — — 64 — — 128 — SY12 TPOR Power-on Reset Delay 3 10 30 μs -40°C to +85°C SY13 TIOZ I/O High-Impedance from 0.68 0.72 1.2 μs — MCLR Low or Watchdog Timer Reset SY20 TWDT1 Watchdog Timer — — — — See Section22.4 “Watchdog Time-out Period Timer (WDT)” and LPRC specification F21 (Table25-19) SY30 TOST Oscillator Start-up Timer — 1024TOSC — — TOSC = OSC1 period Period SY35 TFSCM Fail-Safe Clock Monitor — 500 900 μs -40°C to +85°C Delay Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. © 2009 Microchip Technology Inc. DS70286C-page 271

dsPIC33FJXXXGPX06/X08/X10 FIGURE 25-5: TIMER1, 2, 3, 4, 5, 6, 7, 8 AND 9 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx10 Tx11 Tx15 Tx20 OS60 TMRx Note: Refer to Figure25-1 for load conditions. TABLE 25-22: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 3.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C≤ TA ≤ +85°C for Industrial Param Symbol Characteristic Min Typ Max Units Conditions No. TA10 TTXH TxCK High Time Synchronous, 0.5 TCY + 20 — — ns Must also meet no prescaler parameter TA15 Synchronous, 10 — — ns with prescaler Asynchronous 10 — — ns TA11 TTXL TxCK Low Time Synchronous, 0.5 TCY + 20 — — ns Must also meet no prescaler parameter TA15 Synchronous, 10 — — ns with prescaler Asynchronous 10 — — ns TA15 TTXP TxCK Input Period Synchronous, TCY + 40 — — ns — no prescaler Synchronous, Greater of: — — — N = prescale with prescaler 20 ns or value (TCY + 40)/N (1, 8, 64, 256) Asynchronous 20 — — ns — OS60 Ft1 SOSC1/T1CK Oscillator Input DC — 50 kHz — frequency Range (oscillator enabled by setting bit TCS (T1CON<1>)) TA20 TCKEXTMRL Delay from External TxCK Clock 0.5 TCY — 1.5 TCY — — Edge to Timer Increment Note 1: Timer1 is a Type A. DS70286C-page 272 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 T ABLE 25-23: TIMER2, TIMER4, TIMER6 AND TIMER8 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C≤ TA ≤ +85°C for Industrial Param Symbol Characteristic Min Typ Max Units Conditions No. TB10 TtxH TxCK High Time Synchronous, 0.5 TCY + 20 — — ns Must also meet no prescaler parameter TB15 Synchronous, 10 — — ns with prescaler TB11 TtxL TxCK Low Time Synchronous, 0.5 TCY + 20 — — ns Must also meet no prescaler parameter TB15 Synchronous, 10 — — ns with prescaler TB15 TtxP TxCK Input Synchronous, TCY + 40 — — ns N = prescale Period no prescaler value Synchronous, Greater of: (1, 8, 64, 256) with prescaler 20 ns or (TCY + 40)/N TB20 TCKEXT- Delay from External TxCK Clock 0.5 TCY — 1.5 TCY — — MRL Edge to Timer Increment TABLE 25-24: TIMER3, TIMER5, TIMER7 AND TIMER9 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C Param Symbol Characteristic Min Typ Max Units Conditions No. TC10 TtxH TxCK High Time Synchronous 0.5 TCY + 20 — — ns Must also meet parameter TC15 TC11 TtxL TxCK Low Time Synchronous 0.5 TCY + 20 — — ns Must also meet parameter TC15 TC15 TtxP TxCK Input Period Synchronous, TCY + 40 — — ns N = prescale no prescaler value Synchronous, Greater of: (1, 8, 64, 256) with prescaler 20 ns or (TCY + 40)/N TC20 TCKEXTMRL Delay from External TxCK Clock 0.5 TCY — 1.5 — — Edge to Timer Increment TCY © 2009 Microchip Technology Inc. DS70286C-page 273

dsPIC33FJXXXGPX06/X08/X10 FIGURE 25-6: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS ICx IC10 IC11 IC15 Note: Refer to Figure25-1 for load conditions. TABLE 25-25: INPUT CAPTURE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C Param Symbol Characteristic(1) Min Max Units Conditions No. IC10 TccL ICx Input Low Time No Prescaler 0.5 TCY + 20 — ns — With Prescaler 10 — ns IC11 TccH ICx Input High Time No Prescaler 0.5 TCY + 20 — ns — With Prescaler 10 — ns IC15 TccP ICx Input Period (TCY + 40)/N — ns N = prescale value (1, 4, 16) Note 1: These parameters are characterized but not tested in manufacturing. FIGURE 25-7: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS OCx (Output Compare or PWM Mode) OC11 OC10 Note: Refer to Figure25-1 for load conditions. TABLE 25-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C Param Symbol Characteristic(1) Min Typ Max Units Conditions No. OC10 TccF OCx Output Fall Time — — — ns See parameter D032 OC11 TccR OCx Output Rise Time — — — ns See parameter D031 Note 1: These parameters are characterized but not tested in manufacturing. DS70286C-page 274 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 FIGURE 25-8: OC/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA/OCFB OC15 OCx TABLE 25-27: SIMPLE OC/PWM MODE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C Param Symbol Characteristic(1) Min Typ Max Units Conditions No. OC15 TFD Fault Input to PWM I/O — — 50 ns — Change OC20 TFLT Fault Input Pulse-Width 50 — — ns — Note 1: These parameters are characterized but not tested in manufacturing. © 2009 Microchip Technology Inc. DS70286C-page 275

dsPIC33FJXXXGPX06/X08/X10 FIGURE 25-9: SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP11 SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP31 SP30 SDIx MSb In Bit 14 - - - -1 LSb In SP40 SP41 Note: Refer to Figure25-1 for load conditions. TABLE 25-28: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP10 TscL SCKx Output Low Time TCY/2 — — ns See Note 3 SP11 TscH SCKx Output High Time TCY/2 — — ns See Note 3 SP20 TscF SCKx Output Fall Time — — — ns See parameter D032 and Note 4 SP21 TscR SCKx Output Rise Time — — — ns See parameter D031 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See parameter D032 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See parameter D031 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns — TscL2doV SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 23 — — ns — TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns — TscL2diL to SCKx Edge Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 3: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins. DS70286C-page 276 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 FIGURE 25-10: SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS SP36 SCKX (CKP = 0) SP11 SP10 SP21 SP20 SCKX (CKP = 1) SP35 SP20 SP21 SDOX MSb Bit 14 - - - - - -1 LSb SP40 SP30,SP31 SDIX MSb In Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure25-1 for load conditions. TABLE 25-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP10 TscL SCKx Output Low Time(3) TCY/2 — — ns — SP11 TscH SCKx Output High Time(3) TCY/2 — — ns — SP20 TscF SCKx Output Fall Time(4) — — — ns See parameter D032 SP21 TscR SCKx Output Rise Time(4) — — — ns See parameter D031 SP30 TdoF SDOx Data Output Fall — — — ns See parameter D032 Time(4) SP31 TdoR SDOx Data Output Rise — — — ns See parameter D031 Time(4) SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns — TscL2doV SCKx Edge SP36 TdoV2sc, SDOx Data Output Setup to 30 — — ns — TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data 23 — — ns — TdiV2scL Input to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns — TscL2diL to SCKx Edge Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 3: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins. © 2009 Microchip Technology Inc. DS70286C-page 277

dsPIC33FJXXXGPX06/X08/X10 FIGURE 25-11: SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS SSX SP50 SP52 SCKX (CKP = 0) SP71 SP70 SP73 SP72 SCKX (CKP = 1) SP72 SP73 SP35 SDOX MSb Bit 14 - - - - - -1 LSb SP30,SP31 SP51 SDIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure25-1 for load conditions. TABLE 25-30: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP70 TscL SCKx Input Low Time 30 — — ns — SP71 TscH SCKx Input High Time 30 — — ns — SP72 TscF SCKx Input Fall Time(3) — 10 25 ns — SP73 TscR SCKx Input Rise Time(3) — 10 25 ns — SP30 TdoF SDOx Data Output Fall Time(3) — — — ns See parameter D032 SP31 TdoR SDOx Data Output Rise Time(3) — — — ns See parameter D031 SP35 TscH2doV, SDOx Data Output Valid after — — 30 ns — TscL2doV SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 20 — — ns — TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 20 — — ns — TscL2diL to SCKx Edge SP50 TssL2scH, SSx ↓ to SCKx ↑ or SCKx Input 120 — — ns — TssL2scL SP51 TssH2doZ SSx ↑ to SDOx Output 10 — 50 ns — High-Impedance(3) SP52 TscH2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns — TscL2ssH Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 3: Assumes 50 pF load on all SPIx pins. DS70286C-page 278 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 FIGURE 25-12: SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP71 SP70 SP73 SP72 SCKx (CKP = 1) SP35 SP72 SP73 SP52 SDOx MSb Bit 14 - - - - - -1 LSb SP30,SP31 SP51 SSDDIIx MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure25-1 for load conditions. © 2009 Microchip Technology Inc. DS70286C-page 279

dsPIC33FJXXXGPX06/X08/X10 TABLE 25-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP70 TscL SCKx Input Low Time 30 — — ns — SP71 TscH SCKx Input High Time 30 — — ns — SP72 TscF SCKx Input Fall Time(3) — 10 25 ns — SP73 TscR SCKx Input Rise Time(3) — 10 25 ns — SP30 TdoF SDOx Data Output Fall Time(3) — — — ns See parameter D032 SP31 TdoR SDOx Data Output Rise Time(3) — — — ns See parameter D031 SP35 TscH2doV, SDOx Data Output Valid after — — 30 ns — TscL2doV SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 20 — — ns — TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 20 — — ns — TscL2diL to SCKx Edge SP50 TssL2scH, SSx ↓ to SCKx ↓ or SCKx ↑ 120 — — ns — TssL2scL Input SP51 TssH2doZ SSx ↑ to SDOX Output 10 — 50 ns — High-Impedance(4) SP52 TscH2ssH SSx ↑ after SCKx Edge 1.5 TCY + 40 — — ns — TscL2ssH SP60 TssL2doV SDOx Data Output Valid after — — 50 ns — SSx Edge Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 3: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins. DS70286C-page 280 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 FIGURE 25-13: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM34 IM30 IM33 SDAx Start Stop Condition Condition Note: Refer to Figure25-1 for load conditions. FIGURE 25-14: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM11 IM21 IM10 SCLx IM11 IM26 IM10 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure25-1 for load conditions. © 2009 Microchip Technology Inc. DS70286C-page 281

dsPIC33FJXXXGPX06/X08/X10 T ABLE 25-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 3.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C Param Symbol Characteristic Min(1) Max Units Conditions No. IM10 TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1) — μs — 400 kHz mode TCY/2 (BRG + 1) — μs — 1 MHz mode(2) TCY/2 (BRG + 1) — μs — IM11 THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 1) — μs — 400 kHz mode TCY/2 (BRG + 1) — μs — 1 MHz mode(2) TCY/2 (BRG + 1) — μs — IM20 TF:SCL SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be Fall Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF 1 MHz mode(2) — 100 ns IM21 TR:SCL SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be Rise Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF 1 MHz mode(2) — 300 ns IM25 TSU:DAT Data Input 100 kHz mode 250 — ns — Setup Time 400 kHz mode 100 — ns 1 MHz mode(2) 40 — ns IM26 THD:DAT Data Input 100 kHz mode 0 — μs — Hold Time 400 kHz mode 0 0.9 μs 1 MHz mode(2) 0.2 — μs IM30 TSU:STA Start Condition 100 kHz mode TCY/2 (BRG + 1) — μs Only relevant for Setup Time 400 kHz mode TCY/2 (BRG + 1) — μs Repeated Start condition 1 MHz mode(2) TCY/2 (BRG + 1) — μs IM31 THD:STA Start Condition 100 kHz mode TCY/2 (BRG + 1) — μs After this period the Hold Time 400 kHz mode TCY/2 (BRG + 1) — μs first clock pulse is generated 1 MHz mode(2) TCY/2 (BRG + 1) — μs IM33 TSU:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) — μs — Setup Time 400 kHz mode TCY/2 (BRG + 1) — μs 1 MHz mode(2) TCY/2 (BRG + 1) — μs IM34 THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) — ns — Hold Time 400 kHz mode TCY/2 (BRG + 1) — ns 1 MHz mode(2) TCY/2 (BRG + 1) — ns IM40 TAA:SCL Output Valid 100 kHz mode — 3500 ns — From Clock 400 kHz mode — 1000 ns — 1 MHz mode(2) — 400 ns — IM45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be 400 kHz mode 1.3 — μs free before a new transmission can start 1 MHz mode(2) 0.5 — μs IM50 CB Bus Capacitive Loading — 400 pF — Note 1: BRG is the value of the I2C Baud Rate Generator. Refer to Section 19. “Inter-Integrated Circuit™ (I2C™)” in the “dsPIC33F Family Reference Manual”. 2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). DS70286C-page 282 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 FIGURE 25-15: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS31 IS34 IS30 IS33 SDAx Start Stop Condition Condition FIGURE 25-16: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS11 IS21 IS10 SCLx IS30 IS26 IS31 IS25 IS33 SDAx In IS40 IS40 IS45 SDAx Out © 2009 Microchip Technology Inc. DS70286C-page 283

dsPIC33FJXXXGPX06/X08/X10 TABLE 25-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 3.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C≤ TA ≤ +85°C for Industrial Param Symbol Characteristic Min Max Units Conditions No. IS10 TLO:SCL Clock Low Time 100 kHz mode 4.7 — μs Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — μs Device must operate at a minimum of 10 MHz 1 MHz mode(1) 0.5 — μs — IS11 THI:SCL Clock High Time 100 kHz mode 4.0 — μs Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — μs Device must operate at a minimum of 10 MHz 1 MHz mode(1) 0.5 — μs — IS20 TF:SCL SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be from Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 100 ns IS21 TR:SCL SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be from Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 300 ns IS25 TSU:DAT Data Input 100 kHz mode 250 — ns — Setup Time 400 kHz mode 100 — ns 1 MHz mode(1) 100 — ns IS26 THD:DAT Data Input 100 kHz mode 0 — μs — Hold Time 400 kHz mode 0 0.9 μs 1 MHz mode(1) 0 0.3 μs IS30 TSU:STA Start Condition 100 kHz mode 4.7 — μs Only relevant for Repeated Setup Time 400 kHz mode 0.6 — μs Start condition 1 MHz mode(1) 0.25 — μs IS31 THD:STA Start Condition 100 kHz mode 4.0 — μs After this period, the first Hold Time 400 kHz mode 0.6 — μs clock pulse is generated 1 MHz mode(1) 0.25 — μs IS33 TSU:STO Stop Condition 100 kHz mode 4.7 — μs — Setup Time 400 kHz mode 0.6 — μs 1 MHz mode(1) 0.6 — μs IS34 THD:STO Stop Condition 100 kHz mode 4000 — ns — Hold Time 400 kHz mode 600 — ns 1 MHz mode(1) 250 ns IS40 TAA:SCL Output Valid 100 kHz mode 0 3500 ns — From Clock 400 kHz mode 0 1000 ns 1 MHz mode(1) 0 350 ns IS45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — μs Time the bus must be free 400 kHz mode 1.3 — μs before a new transmission 1 MHz mode(1) 0.5 — μs can start IS50 CB Bus Capacitive Loading — 400 pF — Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). DS70286C-page 284 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 FIGURE 25-17: DCI MODULE (MULTI-CHANNEL, I2S MODES) TIMING CHARACTERISTICS CSCK (SCKE = 0) CS11 CS10 CS21 CS20 CSCK (SCKE = 1) CS20 CS21 COFS CS55CS56 CS35 CS51 CS50 70 High-Z MSb LSb High-Z CSDO CS30 CS31 CSDI MSb In LSb In CS40 CS41 Note: Refer to Figure25-1 for load conditions. © 2009 Microchip Technology Inc. DS70286C-page 285

dsPIC33FJXXXGPX06/X08/X10 T ABLE 25-34: DCI MODULE (MULTI-CHANNEL, I2S MODES) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C≤ TA ≤ +85°C for Industrial Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. CS10 TCSCKL CSCK Input Low Time TCY/2 + 20 — — ns — (CSCK pin is an input) CSCK Output Low Time(3) 30 — — ns — (CSCK pin is an output) CS11 TCSCKH CSCK Input High Time TCY/2 + 20 — — ns — (CSCK pin is an input) CSCK Output High Time(3) 30 — — ns — (CSCK pin is an output) CS20 TCSCKF CSCK Output Fall Time(4) — 10 25 ns — (CSCK pin is an output) CS21 TCSCKR CSCK Output Rise Time(4) — 10 25 ns — (CSCK pin is an output) CS30 TCSDOF CSDO Data Output Fall Time(4) — 10 25 ns — CS31 TCSDOR CSDO Data Output Rise Time(4) — 10 25 ns — CS35 TDV Clock Edge to CSDO Data Valid — — 10 ns — CS36 TDIV Clock Edge to CSDO Tri-Stated 10 — 20 ns — CS40 TCSDI Setup Time of CSDI Data Input 20 — — ns — to CSCK Edge (CSCK pin is input or output) CS41 THCSDI Hold Time of CSDI Data Input to 20 — — ns — CSCK Edge (CSCK pin is input or output) CS50 TCOFSF COFS Fall Time — 10 25 ns See Note 1 (COFS pin is output) CS51 TCOFSR COFS Rise Time — 10 25 ns See Note 1 (COFS pin is output) CS55 TSCOFS Setup Time of COFS Data Input 20 — — ns — to CSCK Edge (COFS pin is input) CS56 THCOFS Hold Time of COFS Data Input to 20 — — ns — CSCK Edge (COFS pin is input) Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for CSCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all DCI pins. DS70286C-page 286 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 FIGURE 25-18: DCI MODULE (AC-LINK MODE) TIMING CHARACTERISTICS BIT_CLK (CSCK) CS61 CS60 CS62 CS21 CS20 CS71 CS70 CS72 SYNC (COFS) CS76 CS75 CS80 LSb MSb LSb SDOx (CSDO) CS76 CS75 SDIx MSb In (CSDI) CS65 CS66 TABLE 25-35: DCI MODULE (AC-LINK MODE) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C Param Symbol Characteristic(1,2) Min Typ(3) Max Units Conditions No. CS60 TBCLKL BIT_CLK Low Time 36 40.7 45 ns — CS61 TBCLKH BIT_CLK High Time 36 40.7 45 ns — CS62 TBCLK BIT_CLK Period — 81.4 — ns Bit clock is input CS65 TSACL Input Setup Time to — — 10 ns — Falling Edge of BIT_CLK CS66 THACL Input Hold Time from — — 10 ns — Falling Edge of BIT_CLK CS70 TSYNCLO SYNC Data Output Low Time — 19.5 — μs See Note 1 CS71 TSYNCHI SYNC Data Output High Time — 1.3 — μs See Note 1 CS72 TSYNC SYNC Data Output Period — 20.8 — μs See Note 1 CS75 TRACL Rise Time, SYNC, SDATA_OUT — 10 25 ns CLOAD = 50 pF, VDD = 5V CS76 TFACL Fall Time, SYNC, SDATA_OUT — 10 25 ns CLOAD = 50 pF, VDD = 5V CS77 TRACL Rise Time, SYNC, SDATA_OUT — — 30 ns CLOAD = 50 pF, VDD = 3V CS78 TFACL Fall Time, SYNC, SDATA_OUT — — 30 ns CLOAD = 50 pF, VDD = 3V CS80 TOVDACL Output Valid Delay from Rising — — 15 ns — Edge of BIT_CLK Note 1: These parameters are characterized but not tested in manufacturing. 2: These values assume BIT_CLK frequency is 12.288 MHz. 3: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2009 Microchip Technology Inc. DS70286C-page 287

dsPIC33FJXXXGPX06/X08/X10 FIGURE 25-19: CAN MODULE I/O TIMING CHARACTERISTICS CiTx Pin Old Value New Value (output) CA10 CA11 CiRx Pin (input) CA20 TABLE 25-36: ECAN™ MODULE I/O TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C Param Symbol Characteristic(1) Min Typ Max Units Conditions No. CA10 TioF Port Output Fall Time — — — ns See parameter D032 CA11 TioR Port Output Rise Time — — — ns See parameter D031 CA20 Tcwf Pulse-Width to Trigger 120 — — ns — CAN Wake-up Filter Note 1: These parameters are characterized but not tested in manufacturing. DS70286C-page 288 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 T ABLE 25-37: ADC MODULE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Param Symbol Characteristic Min. Typ Max. Units Conditions No. Device Supply AD01 AVDD Module VDD Supply Greater of — Lesser of V — VDD - 0.3 VDD + 0.3 or 3.0 or 3.6 AD02 AVSS Module VSS Supply VSS - 0.3 — VSS + 0.3 V — Reference Inputs AD05 VREFH Reference Voltage High AVSS + 2.7 — AVDD V See Note 2 AD05a 3.0 — 3.6 V VREFH = AVDD VREFL = AVSS = 0 AD06 VREFL Reference Voltage Low AVSS — AVDD - 2.7 V See Note 2 AD06a 0 — 0 V VREFH = AVDD VREFL = AVSS = 0 AD07 VREF Absolute Reference 3.0 — 3.6 V VREF = VREFH - VREFL Voltage AD08 IREF Current Drain — 250 550 μΑ ADC operating, see Note 2 — — 1 μΑ ADC off, see Note 2 AD08a IAD Operating Current — 7.0 9.0 mA 10-bit ADC mode, See Note 3 — 2.7 3.2 mA 12-bit ADC mode, See Note 3 Analog Input AD12 VINH Input Voltage Range VINL — VREFH V This voltage reflects Sample VINH and Hold Channels 0, 1, 2, and 3 (CH0-CH3), positive input. See Note 1 AD13 VINL Input Voltage Range VREFL — AVSS + 1V V This voltage reflects Sample VINL and Hold Channels 0, 1, 2, and 3 (CH0-CH3), negative input. See Note 1 AD17 RIN Recommended Imped- — — 200 Ω 10-bit ance of Analog Voltage 200 Ω 12-bit Source Note 1: The ADC conversion result never decreases with an increase in the input voltage, and has no missing codes. 2: These parameters are not characterized or tested in manufacturing. 3: These parameters are characterized; but are not tested in manufacturing. © 2009 Microchip Technology Inc. DS70286C-page 289

dsPIC33FJXXXGPX06/X08/X10 TABLE 25-38: ADC MODULE SPECIFICATIONS (12-BIT MODE) Standard Operating Conditions: 3.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Param Symbol Characteristic Min. Typ Max. Units Conditions No. ADC Accuracy (12-bit Mode) - Measurements with external VREF+/VREF- AD20a Nr Resolution 12 data bits bits AD21a INL Integral Nonlinearity -2 — +2 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD22a DNL Differential Nonlinearity >-1 — <1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD23a GERR Gain Error 1.25 1.5 3 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD24a EOFF Offset Error 1.25 1.52 2 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD25a — Monotonicity(1) — — — — Guaranteed ADC Accuracy (12-bit Mode) - Measurements with internal VREF+/VREF- AD20a Nr Resolution 12 data bits bits AD21a INL Integral Nonlinearity -2 — +2 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD22a DNL Differential Nonlinearity >-1 — <1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD23a GERR Gain Error 2 3 7 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD24a EOFF Offset Error 2 3 5 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD25a — Monotonicity(1) — — — — Guaranteed Dynamic Performance (12-bit Mode) AD30a THD Total Harmonic Distortion -77 -69 -61 dB — AD31a SINAD Signal to Noise and 59 63 64 dB — Distortion AD32a SFDR Spurious Free Dynamic 63 72 74 dB — Range AD33a FNYQ Input Signal Band-Width — — 250 kHz — AD34a ENOB Effective Number of Bits 10.95 11.1 — bits — Note 1: The ADC conversion result never decreases with an increase in the input voltage, and has no missing codes. DS70286C-page 290 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 TABLE 25-39: ADC MODULE SPECIFICATIONS (10-BIT MODE) Standard Operating Conditions: 3.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Param Symbol Characteristic Min. Typ Max. Units Conditions No. ADC Accuracy (10-bit Mode) - Measurements with external VREF+/VREF- AD20b Nr Resolution 10 data bits bits AD21b INL Integral Nonlinearity -1.5 — +1.5 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD22b DNL Differential Nonlinearity >-1 — <1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD23b GERR Gain Error 1 3 6 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD24b EOFF Offset Error 1 2 5 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD25b — Monotonicity(1) — — — — Guaranteed ADC Accuracy (10-bit Mode) - Measurements with internal VREF+/VREF- AD20b Nr Resolution 10 data bits bits AD21b INL Integral Nonlinearity -1 — +1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD22b DNL Differential Nonlinearity >-1 — <1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD23b GERR Gain Error 1 5 6 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD24b EOFF Offset Error 1 2 3 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD25b — Monotonicity(1) — — — — Guaranteed Dynamic Performance (10-bit Mode) AD30b THD Total Harmonic Distortion — -64 -67 dB — AD31b SINAD Signal to Noise and — 57 58 dB — Distortion AD32b SFDR Spurious Free Dynamic — 60 62 dB — Range AD33b FNYQ Input Signal Bandwidth — — 550 kHz — AD34b ENOB Effective Number of Bits 9.1 9.7 9.8 bits — Note 1: The ADC conversion result never decreases with an increase in the input voltage, and has no missing codes. © 2009 Microchip Technology Inc. DS70286C-page 291

dsPIC33FJXXXGPX06/X08/X10 FIGURE 25-20: ADC CONVERSION (12-BIT MODE) TIMING CHARACTERISTICS (ASAM = 0, SSRC<2:0> = 000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP ch0_dischrg ch0_samp eoc AD61 AD60 TSAMP AD55 CONV ADxIF Buffer(0) 1 2 3 4 5 6 7 8 9 1 – Software sets ADxCON. SAMP to start sampling. 5 – Convert bit 11. 2 – Sampling starts after discharge period. TSAMP is described 6 – Convert bit 10. in Section 16. “Analog-to-Digital Converter (ADC)” (DS70183) in the “dsPIC33F Family Reference Manual”. 7 – Convert bit 1. 3 – Software clears ADxCON. SAMP to start conversion. 8 – Convert bit 0. 4 – Sampling ends, conversion sequence starts. 9 – One TAD for end of conversion. DS70286C-page 292 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 TABLE 25-40: ADC CONVERSION (12-BIT MODE) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Param Symbol Characteristic Min. Typ(1) Max. Units Conditions No. Clock Parameters AD50a TAD ADC Clock Period 117.6 — — ns — AD51a tRC ADC Internal RC Oscillator — 250 — ns — Period Conversion Rate AD55a tCONV Conversion Time — 14 TAD ns — AD56a FCNV Throughput Rate — — 500 ksps — AD57a TSAMP Sample Time 3 TAD — — — — Timing Parameters AD60a tPCS Conversion Start from Sample 2.0 TAD — 3.0 TAD — Auto-Convert Trigger Trigger(2) (SSRC<2:0> = 111) not selected AD61a tPSS Sample Start from Setting 2.0 TAD — 3.0 TAD — — Sample (SAMP) bit(2) AD62a tCSS Conversion Completion to — 0.5 TAD — — — Sample Start (ASAM = 1)(2) AD63a tDPU Time to Stabilize Analog Stage — — 20 μs — from ADC Off to ADC On(2,3) Note 1: These parameters are characterized but not tested in manufacturing. 2: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. 3: tDPU is the time required for the ADC module to stabilize when it is turned on (AD1CON1<ADON> = 1). During this time, the ADC result is indeterminate. © 2009 Microchip Technology Inc. DS70286C-page 293

dsPIC33FJXXXGPX06/X08/X10 FIGURE 25-21: ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc AD61 AD60 TSAMP AD55 AD55 CONV ADxIF Buffer(0) Buffer(1) 1 2 3 4 5 6 7 8 5 6 7 8 1 – Software sets ADxCON. SAMP to start sampling. 2 – Sampling starts after discharge period. TSAMP is described in Section 16. “Analog-to-Digital Converter (ADC)” (DS70183) in the “dsPIC33F Family Reference Manual”. 3 – Software clears ADxCON. SAMP to start conversion. 4 – Sampling ends, conversion sequence starts. 5 – Convert bit 9. 6 – Convert bit 8. 7 – Convert bit 0. 8 – One TAD for end of conversion. DS70286C-page 294 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 FIGURE 25-22: ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001) AD50 ADCLK Instruction Execution Set ADON SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc TSAMP TSAMP AD55 AD55 TCONV CONV ADxIF Buffer(0) Buffer(1) 1 2 3 4 5 6 7 3 4 5 6 8 3 4 1 – Software sets ADxCON. ADON to start AD operation. 5 – Convert bit 0. 2 – Sampling starts after discharge period. TSAMP is described 6 – One TAD for end of conversion. in Section 16. “Analog-to-Digital Converter (ADC)” (DS70183) in the “dsPIC33F Family Reference Manual”. 7 – Begin conversion of next channel. 3 – Convert bit 9. 8 – Sample for time specified by SAMC<4:0>. 4 – Convert bit 8. © 2009 Microchip Technology Inc. DS70286C-page 295

dsPIC33FJXXXGPX06/X08/X10 TABLE 25-41: ADC CONVERSION (10-BIT MODE) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V AC CHARACTERISTICS (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Param Symbol Characteristic Min. Typ(1) Max. Units Conditions No. Clock Parameters AD50b TAD ADC Clock Period 65 — — ns — AD51b TRC ADC Internal RC Oscillator Period — 250 — ns — Conversion Rate AD55b TCONV Conversion Time — 12 TAD — — — AD56b FCNV Throughput Rate — — 1.1 Msps — AD57b TSAMP Sample Time 2 TAD — — — — Timing Parameters AD60b TPCS Conversion Start from Sample 2.0 TAD — 3.0 TAD — Auto-Convert Trigger Trigger(2) (SSRC<2:0> = 111) not selected AD61b TPSS Sample Start from Setting 2.0 TAD — 3.0 TAD — — Sample (SAMP) bit(2) AD62b TCSS Conversion Completion to — 0.5 TAD — — — Sample Start (ASAM = 1)(2) AD63b TDPU Time to Stabilize Analog Stage — — 20 μs — from ADC Off to ADC On(2,3) Note 1: These parameters are characterized but not tested in manufacturing. 2: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. 3: TDPU is the time required for the ADC module to stabilize when it is turned on (AD1CON1<ADON> = 1). During this time, the ADC result is indeterminate. DS70286C-page 296 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 26.0 PACKAGING INFORMATION 26.1 Package Marking Information 64-Lead TQFP (10x10x1 mm) Example XXXXXXXXXX dsPIC33FJ XXXXXXXXXX 256GP706 XXXXXXXXXX -I/PTe3 YYWWNNN 0510017 80-Lead TQFP (12x12x1 mm) Example XXXXXXXXXXXX dsPIC33FJ128 XXXXXXXXXXXX GP708-I/PTe3 YYWWNNN 0510017 100-Lead TQFP (12x12x1 mm) Example XXXXXXXXXXXX dsPIC33FJ256 XXXXXXXXXXXX GP710-I/PTe3 YYWWNNN 0510017 100-Lead TQFP (14x14x1mm) 100-Lead TQFP (14x14x1mm) XXXXXXXXXXXX dsPIC33FJ256 XXXXXXXXXXXX GP710-I/PFe3 YYWWNNN 0510017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2009 Microchip Technology Inc. DS70286C-page 297

dsPIC33FJXXXGPX06/X08/X10 26.2 Package Details 64-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 E e E1 N b NOTE 1 123 NOTE 2 α A c φ A2 β A1 L L1 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Leads N 64 Lead Pitch e 0.50 BSC Overall Height A – – 1.20 Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.05 – 0.15 Foot Length L 0.45 0.60 0.75 Footprint L1 1.00 REF Foot Angle φ 0° 3.5° 7° Overall Width E 12.00 BSC Overall Length D 12.00 BSC Molded Package Width E1 10.00 BSC Molded Package Length D1 10.00 BSC Lead Thickness c 0.09 – 0.20 Lead Width b 0.17 0.22 0.27 Mold Draft Angle Top α 11° 12° 13° Mold Draft Angle Bottom β 11° 12° 13° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Chamfers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-085B DS70286C-page 298 © 2009 Microchip Technology Inc.

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dsPIC33FJXXXGPX06/X08/X10 80-Lead Plastic Thin Quad Flatpack (PT) – 12x12x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 E e E1 b N NOTE 1 123 NOTE 2 α A c φ β A1 A2 L L1 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Leads N 80 Lead Pitch e 0.50 BSC Overall Height A – – 1.20 Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.05 – 0.15 Foot Length L 0.45 0.60 0.75 Footprint L1 1.00 REF Foot Angle φ 0° 3.5° 7° Overall Width E 14.00 BSC Overall Length D 14.00 BSC Molded Package Width E1 12.00 BSC Molded Package Length D1 12.00 BSC Lead Thickness c 0.09 – 0.20 Lead Width b 0.17 0.22 0.27 Mold Draft Angle Top α 11° 12° 13° Mold Draft Angle Bottom β 11° 12° 13° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Chamfers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-092B DS70286C-page 300 © 2009 Microchip Technology Inc.

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dsPIC33FJXXXGPX06/X08/X10 100-Lead Plastic Thin Quad Flatpack (PT) – 12x12x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 e E E1 N b NOTE 1 123 NOTE 2 α c A φ β L A1 L1 A2 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Leads N 100 Lead Pitch e 0.40 BSC Overall Height A – – 1.20 Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.05 – 0.15 Foot Length L 0.45 0.60 0.75 Footprint L1 1.00 REF Foot Angle φ 0° 3.5° 7° Overall Width E 14.00 BSC Overall Length D 14.00 BSC Molded Package Width E1 12.00 BSC Molded Package Length D1 12.00 BSC Lead Thickness c 0.09 – 0.20 Lead Width b 0.13 0.18 0.23 Mold Draft Angle Top α 11° 12° 13° Mold Draft Angle Bottom β 11° 12° 13° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Chamfers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-100B DS70286C-page 302 © 2009 Microchip Technology Inc.

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dsPIC33FJXXXGPX06/X08/X10 100-Lead Plastic Thin Quad Flatpack (PF) – 14x14x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 e E1 E b N α NOTE 1 123 NOTE 2 A φ c A2 β A1 L L1 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Leads N 100 Lead Pitch e 0.50 BSC Overall Height A – – 1.20 Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.05 – 0.15 Foot Length L 0.45 0.60 0.75 Footprint L1 1.00 REF Foot Angle φ 0° 3.5° 7° Overall Width E 16.00 BSC Overall Length D 16.00 BSC Molded Package Width E1 14.00 BSC Molded Package Length D1 14.00 BSC Lead Thickness c 0.09 – 0.20 Lead Width b 0.17 0.22 0.27 Mold Draft Angle Top α 11° 12° 13° Mold Draft Angle Bottom β 11° 12° 13° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Chamfers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-110B DS70286C-page 304 © 2009 Microchip Technology Inc.

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dsPIC33FJXXXGPX06/X08/X10 NOTES: DS70286C-page 306 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 APPENDIX A: REVISION HISTORY Revision A (October 2006) Initial release of this document. Revision B (March 2008) This revision includes minor typographical and formatting changes throughout the data sheet text. The major changes are referenced by their respective section in the following table. TABLE A-1: MAJOR SECTION UPDATES Section Name Update Description Section1.0 “Device Overview” Added External Interrupt pin information (INT0 through INT4) to Table1-1. Section3.0 “Memory Organization” Updated Change Notification Register Map table title to reflect application with dsPIC33FJXXXMCX10 devices (Table3-2). Added Change Notification Register Map tables (Table3-3 and Table3-4) for dsPIC33FJXXXMCX08 and dsPIC33FJXXXMCX06 devices, respectively. Updated the bit range for AD1CON3 (ADCS<7:0>) in the ADC1 Register Map and added Note 1 (Table3-15). Updated the bit range for AD2CON3 (ADCS<7:0>) in the ADC2 Register Map (Table3-16). Updated the Reset value for C1FEN1 (FFFF) in the ECAN1 Register Map When C1CTRL1.WIN = 0 or 1 (Table3-18) and updated the title to reflect applicable devices. Updated the title in the ECAN1 Register Map When C1CTRL1.WIN = 0 to reflect applicable devices (Table3-19). Updated the title in the ECAN1 Register Map When C1CTRL1.WIN = 1 to reflect applicable devices (Table3-20). Updated the Reset value for C2FEN1 (FFFF) in the ECAN2 Register Map When C2CTRL1.WIN = 0 or 1 (Table3-21) and updated the title to reflect applicable devices. Updated the title for the ECAN2 Register Map When C2CTRL1.WIN = 0 to reflect applicable devices (Table3-22). Updated the title for the ECAN2 Register Map When C2CTRL1.WIN = 1 to reflect applicable devices (Table3-23). Updated Reset value for TRISA (C6FF) and changed the bit 12 and bit 13 values for ODCA to unimplemented in the PORTA Register Map (Table3-25). Changed the bit 10 and bit 9 values for PMD1 to unimplemented in the PMD Register Map (Table3-34). Section5.0 “Reset” Added POR and BOR references in Reset Flag Bit Operation (Table5-1). Section7.0 “Direct Memory Access (DMA)” Updated the table cross-reference in Note 2 in the DMAxREQ register (Register7-2). © 2009 Microchip Technology Inc. DS70286C-page 307

dsPIC33FJXXXGPX06/X08/X10 TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section8.0 “Oscillator Configuration” Updated the third clock source item (External Clock) in Section8.1.1 “System Clock sources”. Added the center frequency in the OSCTUN register for the FRC Tuning bits (TUN<5:0>) value 011111 and updated the center frequency for bits value 011110 (Register8-4). Section15.0 “Serial Peripheral Interface Removed redundant information, which is now available in the (SPI)” related section in the dsPIC33F Family Reference Manual, while retaining the SPI Module Block Diagram (Figure15-1). Section16.0 “Inter-Integrated Circuit™ Removed sections 16.3 through 16.13, while retaining the I2C Block (I2C™)” Diagram (Figure16-1) (redundant information, which is now available in the related section in the dsPIC33F Family Reference Manual). Section17.0 “Universal Asynchronous Removed sections 17.1 through 17.7 (redundant information, which Receiver Transmitter (UART)” is now available in the related section in the dsPIC33F Family Reference Manual). Section18.0 “Enhanced CAN (ECAN™) Removed sections 18.4 through 18.6 (redundant information, which Module” is now available in the related section in the dsPIC33F Family Reference Manual). Updated Baud Rate Prescaler (BRP<5:0>) bit values in the CiCFG1 register (Register18-9). Changed default bit value from ‘0’ to ‘1’ for bits 6 through 15 (FLTEN6-FLTEN15) in the CiFEN1 register (Register18-11). Section19.0 “Data Converter Interface Removed sections 19.3 through 19.7 (redundant information, which (DCI) Module” is now available in the related section in the dsPIC33F Family Reference Manual). Section20.0 “10-Bit/12-Bit Removed Equation 20-1 (ADC Conversion Clock Period) and Figure Analog-to-Digital Converter (ADC)” 20-3 (ADC Transfer Function (10-Bit Example). Updated AN14 and AN15 ADC values in the ADC2 Module Block Diagram (FIGURE 20-2: “ADC2 Module Block Diagram(1)”). Added Note 2 to ADC Conversion Clock Period Block Diagram (Figure20-3). Updated ADC Conversion Clock Select bits in the ADxCON3 register from ADCS<5:0> to ADCS<7:0>. Any references to these bits have also been updated throughout this data sheet (Register20-3). Added Note to ADxCHS0 register (Register21-6). Section21.0 “Special Features” Updated address 0xF8000E in the Device Configuration Register Map (Table21-1). Added FICD register content (BKBUG, COE, JTAGEN and ICS<1:0>) to the dsPIC33F Configuration Bits Description and removed the last two rows (Table21-2). Added a Note after the second paragraph in Section21.2 “On-Chip Voltage Regulator”. DS70286C-page 308 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section24.0 “Electrical Characteristics” Updated typical value for parameter AD08 (Table24-37). Updated minimum and maximum (both internal and external VREF+/VREF-) values for parameter AD21a (Table24-38). Updated minimum, typical, and maximum (external VREF+/VREF-) values for parameter AD24a (Table24-38). Updated maximum value for parameter AD32a (Table24-38). Updated minimum and maximum (both internal and external VREF+/VREF-) values for parameter AD21a (Table24-38). Updated minimum and maximum (external VREF+/VREF-) values for parameter AD21b (Table24-39). Updated typical and maximum values for parameter AD32b (Table24-39). Updated minimum, typical, and maximum values for parameter AD60a (Table24-40 and Table24-41). Updated minimum and maximum values for parameter AD61a (Table24-40 and Table24-41). Updated minimum and maximum values for parameter AD63a (Table24-40 and Table24-41). Added Note 3 to ADC Conversion (12-bit Mode) Timing Requirements (Table24-40 and Table24-41). © 2009 Microchip Technology Inc. DS70286C-page 309

dsPIC33FJXXXGPX06/X08/X10 Revision C (March 2009) This revision includes minor typographical and formatting changes throughout the data sheet text. Global changes include: • Changed all instances of OSCI to OSC1 and OSCO to OSC2 • Changed all instances of VDDCORE and VDDCORE/VCAP to VCAP/VDDCORE The other changes are referenced by their respective section in the following table. TABLE A-2: MAJOR SECTION UPDATES Section Name Update Description “High-Performance, 16-Bit Digital Updated all pin diagrams to denote the pin voltage tolerance (see “Pin Signal Controllers” Diagrams”). Added Note 2 to the 28-Pin QFN-S and 44-Pin QFN pin diagrams, which references pin connections to VSS. Section1.0 “Device Overview” Updated AVDD in the PINOUT I/O Descriptions (see Table1-1). Section2.0 “Guidelines for Getting Added new section to the data sheet that provides guidelines on getting Started with 16-Bit Digital Signal started with 16-bit Digital Signal Controllers. Controllers” Section4.0 “Memory Organization” Add Accumulator A and B SFRs (ACCAL, ACCAH, ACCAU, ACCBL, ACCBH and ACCBU) and updated the Reset value for CORCON in the CPU Core Register Map (see Table4-1). Updated Reset values for IPC3, IPC4, IPC11 and IPC13-IPC15 in the Interrupt Controller Register Map (see Table4-5). Updated the Reset value for CLKDIV in the System Control Register Map (see Table4-32). Section5.0 “Flash Program Memory” Updated Section5.3 “Programming Operations” with programming time formula. Section9.0 “Oscillator Configuration” Added Note 2 to the Oscillator System Diagram (see Figure9-1). Updated default bit values for DOZE<2:0> and FRCDIV<2:0> in the Clock Divisor (CLKDIV) Register (see Register9-2). Added a paragraph regarding FRC accuracy at the end of Section9.1.1 “System Clock sources”. Added Note 1 to the FRC Oscillator Tuning (OSCTUN) Register (see Register9-4). Section10.0 “Power-Saving Added the following registers: Features” • PMD1: Peripheral Module Disable Control Register 1 (Register10-1) • PMD2: Peripheral Module Disable Control Register 2 (Register10-2) • PMD3: Peripheral Module Disable Control Register 3 (Register10-3) Section11.0 “I/O Ports” Added reference to pin diagrams for I/O pin availability and functionality (see Section11.2 “Open-Drain Configuration”). Section16.0 “Serial Peripheral Added Note 2 to the SPIxCON1 register (see Register16-2). Interface (SPI)” Section18.0 “Universal Updated the UTXINV bit settings in the UxSTA register (see Asynchronous Receiver Transmitter Register18-2). (UART)” DS70286C-page 310 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 TABLE A-2: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section19.0 “Enhanced CAN Changed bit 11 in the ECAN Control Register 1 (CiCTRL1) to Reserved (ECAN™) Module” (see Register19-1). Added the ECAN Filter 15-8 Mask Selection (CiFMSKSEL2) register (see Register19-19). Section21.0 “10-Bit/12-Bit Replaced the ADC Module Block Diagram (see Figure21-1) and removed Analog-to-Digital Converter (ADC)” Figure21-2. Section22.0 “Special Features” Added Note 2 to the Device Configuration Register Map (see Table22-1) Section25.0 “Electrical Updated Typical values for Thermal Packaging Characteristics (see Characteristics” Table25-3). Updated Min and Max values for parameter DC12 (RAM Data Retention Voltage) and added Note 4 (see Table25-4). Updated Power-Down Current Max values for parameters DC60b and DC60c (see Table25-7). Updated Characteristics for I/O Pin Input Specifications (see Table25-9). Updated Program Memory values for parameters 136, 137 and 138 (renamed to 136a, 137a and 138a), added parameters 136b, 137b and 138b, and added Note 2 (see Table25-12). Added parameter OS42 (GM) to the External Clock Timing Requirements (see Table25-16). Updated Watchdog Timer Time-out Period parameter SY20 (see Table25-21). © 2009 Microchip Technology Inc. DS70286C-page 311

dsPIC33FJXXXGPX06/X08/X10 NOTES: DS70286C-page 312 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 INDEX A CPU Clocking System......................................................138 Options.....................................................................138 A/D Converter...................................................................225 Selection...................................................................138 DMA..........................................................................225 Customer Change Notification Service.............................317 Initialization...............................................................225 Customer Notification Service..........................................317 Key Features.............................................................225 Customer Support.............................................................317 AC Characteristics............................................................266 Internal RC Accuracy................................................268 D Load Conditions........................................................266 Data Accumulators and Adder/Subtractor..........................29 ADC Module Data Space Write Saturation......................................31 ADC11 Register Map..................................................49 Overflow and Saturation.............................................29 ADC2 Register Map....................................................49 Round Logic...............................................................30 Alternate Interrupt Vector Table (AIVT)..............................81 Write Back..................................................................30 Arithmetic Logic Unit (ALU).................................................27 Data Address Space...........................................................35 Assembler Alignment....................................................................35 MPASM Assembler...................................................254 Memory Map for dsPIC33FJXXXGPX06/X08/X10 Devic- B es with 16 KB RAM.............................................37 Memory Map for dsPIC33FJXXXGPX06/X08/X10 Devic- Barrel Shifter.......................................................................31 es with 30 KB RAM.............................................38 Bit-Reversed Addressing....................................................64 Memory Map for dsPIC33FJXXXGPX06/X08/X10 Devic- Example......................................................................65 es with 8 KB RAM...............................................36 Implementation...........................................................64 Near Data Space........................................................35 Sequence Table (16-Entry).........................................65 Software Stack...........................................................61 Block Diagrams Width..........................................................................35 16-bit Timer1 Module................................................157 Data Converter Interface (DCI) Module............................217 A/D Module...............................................................226 DC Characteristics............................................................258 Connections for On-Chip Voltage Regulator.............241 I/O Pin Input Specifications......................................263 DCI Module...............................................................218 I/O Pin Output Specifications....................................264 Device Clock.....................................................137, 139 DSP Engine................................................................28 Idle Current (IIDLE)....................................................261 dsPIC33F....................................................................14 Operating Current (IDD)............................................260 dsPIC33F CPU Core...................................................22 Power-Down Current (IPD)........................................262 Program Memory......................................................265 ECAN Module...........................................................192 Temperature and Voltage Specifications..................259 Input Capture............................................................165 DCI Output Compare.......................................................167 Buffer Control...........................................................217 PLL............................................................................139 Buffer Data Alignment..............................................217 Reset System..............................................................77 Introduction...............................................................217 Shared Port Structure...............................................155 Transmit/Receive Shift Register...............................217 SPI............................................................................171 DCI I/O Pins......................................................................217 Timer2 (16-bit)..........................................................161 COFS........................................................................217 Timer2/3 (32-bit).......................................................160 CSCK........................................................................217 UART........................................................................185 CSDI.........................................................................217 Watchdog Timer (WDT)............................................242 CSDO.......................................................................217 C DCI Module Register Map..............................................................58 C Compilers Development Support.......................................................253 MPLAB C18..............................................................254 DMA Module MPLAB C30..............................................................254 DMA Register Map.....................................................50 Clock Switching.................................................................145 DMAC Registers...............................................................128 Enabling....................................................................145 DMAxCNT................................................................128 Sequence..................................................................145 DMAxCON................................................................128 Code Examples DMAxPAD................................................................128 Erasing a Program Memory Page...............................75 DMAxREQ................................................................128 Initiating a Programming Sequence............................76 DMAxSTA.................................................................128 Loading Write Buffers.................................................76 DMAxSTB.................................................................128 Port Write/Read........................................................156 DSP Engine........................................................................27 PWRSAV Instruction Syntax.....................................147 Multiplier.....................................................................29 Code Protection........................................................237, 243 Configuration Bits..............................................................237 E Description (Table)....................................................238 ECAN Module Configuration Register Map..............................................237 CiFMSKSEL2 register..............................................209 Configuring Analog Port Pins............................................156 ECAN1 Register Map (C1CTRL1.WIN = 0 or 1).........52 CPU ECAN1 Register Map (C1CTRL1.WIN = 0)................52 Control Register..........................................................24 ECAN1 Register Map (C1CTRL1.WIN = 1)................53 © 2009 Microchip Technology Inc. DS70286C-page 313

dsPIC33FJXXXGPX06/X08/X10 ECAN2 Register Map (C2CTRL1.WIN = 0 or 1).........55 Interrupt Disable.......................................................125 ECAN2 Register Map (C2CTRL1.WIN = 0)..........55, 56 Interrupt Service Routine..........................................125 Frame Types.............................................................191 Trap Service Routine................................................125 Modes of Operation..................................................193 Interrupt Vector Table (IVT)................................................81 Overview...................................................................191 Interrupts Coincident with Power Save Instructions.........148 ECAN Registers J Filter 15-8 Mask Selection Register (CiFMSKSEL2).209 Electrical Characteristics...................................................257 JTAG Boundary Scan Interface........................................237 AC.............................................................................266 M Enhanced CAN Module.....................................................191 Equations Memory Organization.........................................................33 Device Operating Frequency....................................138 Microchip Internet Web Site..............................................317 Errata..................................................................................12 Modes of Operation Disable......................................................................193 F Initialization...............................................................193 Flash Program Memory.......................................................71 Listen All Messages..................................................193 Control Registers........................................................72 Listen Only................................................................193 Operations..................................................................72 Loopback..................................................................193 Programming Algorithm..............................................75 Normal Operation.....................................................193 RTSP Operation..........................................................72 Modulo Addressing.............................................................62 Table Instructions........................................................71 Applicability.................................................................64 Flexible Configuration.......................................................237 Operation Example.....................................................63 FSCM Start and End Address...............................................63 Delay for Crystal and PLL Clock Sources...................80 W Address Register Selection....................................63 Device Resets.............................................................80 MPLAB ASM30 Assembler, Linker, Librarian...................254 MPLAB ICD 2 In-Circuit Debugger...................................255 I MPLAB ICE 2000 High-Performance Universal In-Circuit Em- I/O Ports............................................................................155 ulator.........................................................................255 Parallel I/O (PIO).......................................................155 MPLAB Integrated Development Environment Software..253 Write/Read Timing....................................................156 MPLAB PM3 Device Programmer....................................255 I2C MPLAB REAL ICE In-Circuit Emulator System................255 Operating Modes......................................................177 MPLINK Object Linker/MPLIB Object Librarian................254 Registers...................................................................177 N I2C Module I2C1 Register Map......................................................47 NVM Module I2C2 Register Map......................................................47 Register Map..............................................................60 In-Circuit Debugger...........................................................243 O In-Circuit Emulation...........................................................237 In-Circuit Serial Programming (ICSP).......................237, 243 Open-Drain Configuration.................................................156 Input Capture Output Compare...............................................................167 Registers...................................................................166 P Input Change Notification Module.....................................156 Instruction Addressing Modes.............................................61 Packaging.........................................................................297 File Register Instructions............................................61 Details.......................................................................298 Fundamental Modes Supported..................................62 Marking.....................................................................297 MAC Instructions.........................................................62 Peripheral Module Disable (PMD)....................................148 MCU Instructions........................................................61 PICSTART Plus Development Programmer.....................256 Move and Accumulator Instructions............................62 Pinout I/O Descriptions (table)............................................15 Other Instructions........................................................62 PMD Module Instruction Set Register Map..............................................................60 Overview...................................................................248 POR and Long Oscillator Start-up Times...........................80 Summary...................................................................245 PORTA Instruction-Based Power-Saving Modes...........................147 Register Map..............................................................58 Idle............................................................................148 PORTB Sleep.........................................................................147 Register Map..............................................................58 Internal RC Oscillator PORTC Use with WDT...........................................................242 Register Map..............................................................59 Internet Address................................................................317 PORTD Interrupt Control and Status Registers................................85 Register Map..............................................................59 IECx............................................................................85 PORTE IFSx.............................................................................85 Register Map..............................................................59 INTCON1....................................................................85 PORTF INTCON2....................................................................85 Register Map..............................................................59 IPCx............................................................................85 PORTG Interrupt Setup Procedures...............................................125 Register Map..............................................................60 Initialization...............................................................125 Power-Saving Features....................................................147 DS70286C-page 314 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 Clock Frequency and Switching................................147 CLKDIV (Clock Divisor)............................................142 Program Address Space.....................................................33 CORCON (Core Control)......................................26, 86 Construction................................................................66 DCICON1 (DCI Control 1)........................................219 Data Access from Program Memory Using Program DCICON2 (DCI Control 2)........................................220 Space Visibility....................................................69 DCICON3 (DCI Control 3)........................................221 Data Access from Program Memory Using Table Instruc- DCISTAT (DCI Status).............................................222 tions....................................................................68 DMACS0 (DMA Controller Status 0)........................133 Data Access from, Address Generation......................67 DMACS1 (DMA Controller Status 1)........................135 Memory Map...............................................................33 DMAxCNT (DMA Channel x Transfer Count)...........132 Table Read Instructions DMAxCON (DMA Channel x Control).......................129 TBLRDH.............................................................68 DMAxPAD (DMA Channel x Peripheral Address)....132 TBLRDL..............................................................68 DMAxREQ (DMA Channel x IRQ Select).................130 Visibility Operation......................................................69 DMAxSTA (DMA Channel x RAM Start Address A).131 Program Memory DMAxSTB (DMA Channel x RAM Start Address B).131 Interrupt Vector...........................................................34 DSADR (Most Recent DMA RAM Address).............136 Organization................................................................34 I2CxCON (I2Cx Control)...........................................179 Reset Vector...............................................................34 I2CxMSK (I2Cx Slave Mode Address Mask)............183 I2CxSTAT (I2Cx Status)...........................................181 R ICxCON (Input Capture x Control)............................166 Reader Response.............................................................318 IEC0 (Interrupt Enable Control 0)...............................98 Registers IEC1 (Interrupt Enable Control 1).............................100 ADxCHS0 (ADCx Input Channel 0 Select.................234 IEC2 (Interrupt Enable Control 2).............................102 ADxCHS123 (ADCx Input Channel 1, 2, 3 Select)...233 IEC3 (Interrupt Enable Control 3).............................104 ADxCON1 (ADCx Control 1).....................................228 IEC4 (Interrupt Enable Control 4).............................105 ADxCON2 (ADCx Control 2).....................................230 IFS0 (Interrupt Flag Status 0).....................................90 ADxCON3 (ADCx Control 3).....................................231 IFS1 (Interrupt Flag Status 1).....................................92 ADxCON4 (ADCx Control 4).....................................232 IFS2 (Interrupt Flag Status 2).....................................94 ADxCSSH (ADCx Input Scan Select High)...............235 IFS3 (Interrupt Flag Status 3).....................................96 ADxCSSL (ADCx Input Scan Select Low)................235 IFS4 (Interrupt Flag Status 4).....................................97 ADxPCFGH (ADCx Port Configuration High)...........236 INTCON1 (Interrupt Control 1)...................................87 ADxPCFGL (ADCx Port Configuration Low).............236 INTCON2 (Interrupt Control 2)...................................89 CiBUFPNT1 (ECAN Filter 0-3 Buffer Pointer)...........204 INTTREG Interrupt Control and Status Register......124 CiBUFPNT2 (ECAN Filter 4-7 Buffer Pointer)...........205 IPC0 (Interrupt Priority Control 0).............................106 CiBUFPNT3 (ECAN Filter 8-11 Buffer Pointer).........205 IPC1 (Interrupt Priority Control 1).............................107 CiBUFPNT4 (ECAN Filter 12-15 Buffer Pointer).......206 IPC10 (Interrupt Priority Control 10).........................116 CiCFG1 (ECAN Baud Rate Configuration 1)............202 IPC11 (Interrupt Priority Control 11).........................117 CiCFG2 (ECAN Baud Rate Configuration 2)............203 IPC12 (Interrupt Priority Control 12).........................118 CiCTRL1 (ECAN Control 1)......................................194 IPC13 (Interrupt Priority Control 13).........................119 CiCTRL2 (ECAN Control 2)......................................195 IPC14 (Interrupt Priority Control 14).........................120 CiEC (ECAN Transmit/Receive Error Count)............201 IPC15 (Interrupt Priority Control 15).........................121 CiFCTRL (ECAN FIFO Control)................................197 IPC16 (Interrupt Priority Control 16).........................122 CiFEN1 (ECAN Acceptance Filter Enable)...............204 IPC17 (Interrupt Priority Control 17).........................123 CiFIFO (ECAN FIFO Status).....................................198 IPC2 (Interrupt Priority Control 2).............................108 CiFMSKSEL1 (ECAN Filter 7-0 Mask Selection).....208, IPC3 (Interrupt Priority Control 3).............................109 209 IPC4 (Interrupt Priority Control 4).............................110 CiINTE (ECAN Interrupt Enable)..............................200 IPC5 (Interrupt Priority Control 5).............................111 CiINTF (ECAN Interrupt Flag)...................................199 IPC6 (Interrupt Priority Control 6).............................112 CiRXFnEID (ECAN Acceptance Filter n Extended Identi- IPC7 (Interrupt Priority Control 7).............................113 fier)....................................................................207 IPC8 (Interrupt Priority Control 8).............................114 CiRXFnSID (ECAN Acceptance Filter n Standard Identi- IPC9 (Interrupt Priority Control 9).............................115 fier)....................................................................207 NVMCOM (Flash Memory Control)......................73, 74 CiRXFUL1 (ECAN Receive Buffer Full 1).................211 OCxCON (Output Compare x Control).....................169 CiRXFUL2 (ECAN Receive Buffer Full 2).................211 OSCCON (Oscillator Control)...................................140 CiRXMnEID (ECAN Acceptance Filter Mask n Extended OSCTUN (FRC Oscillator Tuning)............................144 Identifier)...........................................................210 PLLFBD (PLL Feedback Divisor).............................143 CiRXMnSID (ECAN Acceptance Filter Mask n Standard PMD1 (Peripheral Module Disable Control Register 1).. Identifier)...........................................................210 149 CiRXOVF1 (ECAN Receive Buffer Overflow 1)........212 PMD2 (Peripheral Module Disable Control Register 2).. CiRXOVF2 (ECAN Receive Buffer Overflow 2)........212 151 CiTRBnDLC (ECAN Buffer n Data Length Control)..215 PMD3 (Peripheral Module Disable Control Register 3).. CiTRBnDm (ECAN Buffer n Data Field Byte m).......215 153 CiTRBnEID (ECAN Buffer n Extended Identifier).....214 RCON (Reset Control)................................................78 CiTRBnSID (ECAN Buffer n Standard Identifier)......214 RSCON (DCI Receive Slot Control).........................223 CiTRBnSTAT (ECAN Receive Buffer n Status)........216 SPIxCON1 (SPIx Control 1).....................................173 CiTRmnCON (ECAN TX/RX Buffer m Control).........213 SPIxCON2 (SPIx Control 2).....................................175 CiVEC (ECAN Interrupt Code)..................................196 © 2009 Microchip Technology Inc. DS70286C-page 315

dsPIC33FJXXXGPX06/X08/X10 SPIxSTAT (SPIx Status and Control).......................172 Input Capture (CAPx)...............................................274 SR (CPU Status)...................................................24, 86 OC/PWM...................................................................275 T1CON (Timer1 Control)...........................................158 Output Compare (OCx).............................................274 TSCON (DCI Transmit Slot Control).........................223 Reset, Watchdog Timer, Oscillator Start-up Timer and TxCON (T2CON, T4CON, T6CON or T8CON Control).. Power-up Timer................................................270 162 SPIx Master Mode (CKE = 0)...................................276 TyCON (T3CON, T5CON, T7CON or T9CON Control).. SPIx Master Mode (CKE = 1)...................................277 163 SPIx Slave Mode (CKE = 0).....................................278 UxMODE (UARTx Mode)..........................................186 SPIx Slave Mode (CKE = 1).....................................279 UxSTA (UARTx Status and Control).........................188 Timer1, 2, 3, 4, 5, 6, 7, 8, 9 External Clock..............272 Reset Timing Requirements Clock Source Selection...............................................79 CLKO and I/O...........................................................269 Special Function Register Reset States.....................80 DCI AC-Link Mode............................................287, 289 Times..........................................................................79 DCI Multi-Channel, I2S Modes..........................286, 289 Reset Sequence..................................................................81 External Clock...........................................................267 Resets.................................................................................77 Input Capture............................................................274 Timing Specifications S 10-bit A/D Conversion Requirements.......................296 Serial Peripheral Interface (SPI).......................................171 12-bit A/D Conversion Requirements.......................293 Software Simulator (MPLAB SIM).....................................254 CAN I/O Requirements.............................................288 Software Stack Pointer, Frame Pointer I2Cx Bus Data Requirements (Master Mode)...........282 CALLL Stack Frame....................................................61 I2Cx Bus Data Requirements (Slave Mode).............284 Special Features of the CPU.............................................237 Output Compare Requirements................................274 SPI Module PLL Clock.................................................................268 SPI1 Register Map......................................................48 Reset, Watchdog Timer, Oscillator Start-up Timer, Pow- SPI2 Register Map......................................................48 er-up Timer and Brown-out Reset Requirements... Symbols Used in Opcode Descriptions.............................246 271 System Control Simple OC/PWM Mode Requirements.....................275 Register Map...............................................................60 SPIx Master Mode (CKE = 0) Requirements............276 SPIx Master Mode (CKE = 1) Requirements............277 T SPIx Slave Mode (CKE = 0) Requirements..............278 Temperature and Voltage Specifications SPIx Slave Mode (CKE = 1) Requirements..............280 AC.............................................................................266 Timer1 External Clock Requirements.......................272 Timer1...............................................................................157 Timer2, Timer4, Timer6 and Timer8 External Clock Re- Timer2/3, Timer4/5, Timer6/7 and Timer8/9.....................159 quirements........................................................273 Timing Characteristics Timer3, Timer5, Timer7 and Timer9 External Clock Re- CLKO and I/O...........................................................269 quirements........................................................273 Timing Diagrams U 10-bit A/D Conversion (CHPS = 01, SIMSAM = 0, ASAM = 0, SSRC = 000)..............................................294 UART Module = 01, SIMSAM = 10-bit A/D Conversion (CHPS UART1 Register Map..................................................48 0, ASAM = 1, SSRC = 111, SAMC = UART2 Register Map..................................................48 00001) ...........................................................295 V 12-bit A/D Conversion (ASAM = 0, SSRC = 000).....292 CAN I/O.....................................................................288 Voltage Regulator (On-Chip)............................................241 DCI AC-Link Mode....................................................287 W DCI Multi -Channel, I2S Modes.................................285 External Clock...........................................................267 Watchdog Timer (WDT)............................................237, 242 I2Cx Bus Data (Master Mode)..................................281 Programming Considerations...................................242 I2Cx Bus Data (Slave Mode)....................................283 WWW Address.................................................................317 I2Cx Bus Start/Stop Bits (Master Mode)...................281 WWW, On-Line Support.....................................................12 I2Cx Bus Start/Stop Bits (Slave Mode).....................283 DS70286C-page 316 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following informa- tion: • Field Application Engineer (FAE) • Technical Support • Product Support – Data sheets and errata, appli- cation notes and sample programs, design Customers should contact their distributor, representa- resources, user’s guides and hardware support tive or field application engineer (FAE) for support. documents, latest software releases and archived Local sales offices are also available to help custom- software ers. A listing of sales offices and locations is included in • General Technical Support – Frequently Asked the back of this document. Questions (FAQs), technical support requests, Technical support is available through the web site online discussion groups, Microchip consultant at: http://support.microchip.com program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Micro- chip sales offices, distributors and factory repre- sentatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a spec- ified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notifi- cation and follow the registration instructions. © 2009 Microchip Technology Inc. DS70286C-page 317

dsPIC33FJXXXGPX06/X08/X10 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: dsPIC33FJXXXGPX06/X08/X10 Literature Number: DS70286C Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS70286C-page 318 © 2009 Microchip Technology Inc.

dsPIC33FJXXXGPX06/X08/X10 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. dsPIC 33 FJ 256 GP7 10 T I / PT - XXX Examples: a) dsPIC33FJ256GP710I/PT: Microchip Trademark General-purpose dsPIC33, 64KB program memory, 100-pin, Industrial temp., Architecture TQFP package. Flash Memory Family Program Memory Size (KB) Product Group Pin Count Tape and Reel Flag (if applicable) Temperature Range Package Pattern Architecture: 33 = 16-bit Digital Signal Controller Flash Memory Family: FJ = Flash program memory, 3.3V Product Group: GP2 = General purpose family GP3 = General purpose family GP5 = General purpose family GP7 = General purpose family Pin Count: 06 = 64-pin 08 = 80-pin 10 = 100-pin Temperature Range: I = -40°C to +85°C (Industrial) Package: PT = 10x10 or 12x12 mm TQFP (Thin Quad Flatpack) PF = 14x14 mm TQFP (Thin Quad Flatpack) Pattern Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise) ES = Engineering Sample © 2009 Microchip Technology Inc. DS70286C-page 319

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