Product Sample & Technical Tools & Support & Folder Buy Documents Software Community DS90LV047A SNLS044D–MAY2000–REVISEDJULY2016 DS90LV047A 3-V LVDS Quad CMOS Differential Line Driver 1 Features 3 Description • >400-Mbps(200MHz)SwitchingRates The DS90LV047A device is a quad CMOS flow- 1 through differential line driver designed for • Flow-ThroughPinoutSimplifiesPCBLayout applications requiring ultra-low power dissipation and • 300-psTypicalDifferentialSkew high data rates. The device is designed to support • 400-psMaximumDifferentialSkew data rates in excess of 400 Mbps (200 MHz) using Low Voltage Differential Signaling (LVDS) • 1.7-nsMaximumPropagationDelay technology. • 3.3-VPowerSupplyDesign The DS90LV047A accepts low voltage TTL/CMOS • ±350-mVDifferentialSignaling inputlevelsandtranslatesthemtolowvoltage • LowPowerDissipation(13mWat3.3-VStatic) (350 mV) differential output signals. In addition, the • InteroperableWithExisting5-VLVDSReceivers driver supports a TRI-STATE function that may be • HighimpedanceonLVDSOutputsonPower used to disable the output stage, disabling the load current, and thus dropping the device to an ultra low Down idle power state of 13 mW typical. The DS90LV047A • ConformstoTIA/EIA-644LVDSStandard hasaflow-throughpinoutforeasyPCBlayout. • IndustrialOperatingTemperatureRange The EN and EN* inputs are ANDed together and (−40°Cto+85°C) control the TRI-STATE outputs. The enables are • AvailableinSurfaceMountSOICandLowProfile common to all four drivers. The DS90LV047A and TSSOPPackage companion line receiver (DS90LV048A) provide a new alternative to high power psuedo-ECL devices 2 Applications forhighspeedpoint-to-pointinterfaceapplications. • MultifunctionPrinters DeviceInformation(1) • LVDS–LVCMOSTranslation PARTNUMBER PACKAGE BODYSIZE(NOM) SOIC(16) 9.90mm×3.91mm DS90LV048A TSSOP(16) 5.00mm×4.40mm (1) For all available packages, see the orderable addendum at theendofthedatasheet. FunctionalDiagram 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

DS90LV047A SNLS044D–MAY2000–REVISEDJULY2016 www.ti.com Table of Contents 1 Features.................................................................. 1 8.3 FeatureDescription.................................................12 2 Applications........................................................... 1 8.4 DeviceFunctionalModes........................................13 3 Description............................................................. 1 9 ApplicationandImplementation........................ 14 4 RevisionHistory..................................................... 2 9.1 ApplicationInformation............................................14 9.2 TypicalApplication .................................................14 5 PinConfigurationandFunctions......................... 3 10 PowerSupplyRecommendations..................... 16 6 Specifications......................................................... 3 11 Layout................................................................... 16 6.1 AbsoluteMaximumRatings......................................3 6.2 ESDRatings..............................................................4 11.1 LayoutGuidelines.................................................16 6.3 RecommendedOperatingConditions.......................4 11.2 LayoutExample....................................................17 6.4 ThermalInformation..................................................4 12 DeviceandDocumentationSupport................. 18 6.5 ElectricalCharacteristics..........................................4 12.1 DocumentationSupport........................................18 6.6 SwitchingCharacteristics .........................................5 12.2 ReceivingNotificationofDocumentationUpdates18 6.7 TypicalCharacteristics..............................................6 12.3 CommunityResources..........................................18 7 ParameterMeasurementInformation..................8 12.4 Trademarks...........................................................18 12.5 ElectrostaticDischargeCaution............................18 8 DetailedDescription............................................ 11 12.6 Glossary................................................................18 8.1 Overview.................................................................11 13 Mechanical,Packaging,andOrderable 8.2 FunctionalBlockDiagram.......................................12 Information........................................................... 18 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionC(April2013)toRevisionD Page • AddedESDRatingstable,ThermalInformationtable,FeatureDescriptionsection,DeviceFunctionalModes, ApplicationandImplementationsection,PowerSupplyRecommendationssection,Layoutsection,Deviceand DocumentationSupportsection,andMechanical,Packaging,andOrderableInformationsection....................................... 1 ChangesfromRevisionB(April2013)toRevisionC Page • ChangedlayoutofNationalSemiconductorDataSheettoTIformat.................................................................................. 15 2 SubmitDocumentationFeedback Copyright©2000–2016,TexasInstrumentsIncorporated ProductFolderLinks:DS90LV047A

DS90LV047A www.ti.com SNLS044D–MAY2000–REVISEDJULY2016 5 Pin Configuration and Functions DorPWPackage 16-PinSOICorTSSOP TopView PinFunctions PIN I/O DESCRIPTION NAME NO. D 2,3,6,7 I Driverinputpin,TTL/CMOScompatible IN D 10,11,14,15 O Non-invertingdriveroutputpin,LVDSlevels OUT+ D 9,12,13,16 O Invertingdriveroutputpin,LVDSlevels OUT− Driverenablepin:WhenENislow,thedriverisdisabled.WhenENishighandEN*islow EN 1 I oropen,thedriverisenabled.IfbothENandEN*areopencircuit,thenthedriveris disabled. Driverenablepin:WhenEN*ishigh,thedriverisdisabled.WhenEN*isloworopenand EN* 8 I ENishigh,thedriverisenabled.IfbothENandEN*areopencircuit,thenthedriveris disabled. GND 5 — Groundpin V 4 — Powersupplypin,+3.3V±0.3V CC 6 Specifications 6.1 Absolute Maximum Ratings See (1) MIN MAX UNIT Supplyvoltage(V ) −0.3 4 V CC Inputvoltage(D ) −0.3 V +0.3 V IN CC Enableinputvoltage(EN,EN*) −0.3 V +0.3 V CC Outputvoltage(D ,D ) −0.3 3.9 V OUT+ OUT– Short-circuitduration (D ,D ) Continuous OUT+ OUT– D0016Apackage 1088 mW Maximumpackagepower PW0016Apackage 866 dissipationat+25°C DerateD0016Apackage above+25°C 8.5 mW/°C DeratePW0016Apackage above+25°C 6.9 Leadtemperature Soldering(4s) 260 °C Maximumjunctiontemperature 150 °C Storagetemperature,T −65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. Copyright©2000–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DS90LV047A

DS90LV047A SNLS044D–MAY2000–REVISEDJULY2016 www.ti.com 6.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM) ±10000 V Electrostaticdischarge(1) V (ESD) MachineModel ±1200 (1) ESDRatings: HBM(1.5kΩ,100pF) EIAJ(0Ω,200pF) 6.3 Recommended Operating Conditions MIN NOM MAX UNIT Supplyvoltage,V 3 3.3 3.6 V CC Operatingfreeairtemperature,T −40 25 85 °C A 6.4 Thermal Information DS90LV047A THERMALMETRIC(1) PW(TSSOP) UNIT 16PINS R Junction-to-ambientthermalresistance 114 °C/W θJA R Junction-to-case(top)thermalresistance 51 °C/W θJC(top) R Junction-to-boardthermalresistance 59 °C/W θJB ψ Junction-to-topcharacterizationparameter 8 °C/W JT ψ Junction-to-boardcharacterizationparameter 58 °C/W JB (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report. 6.5 Electrical Characteristics Oversupplyvoltageandoperatingtemperatureranges,unlessotherwisespecified(1)(2)(3) PARAMETER TESTCONDITIONS PIN MIN TYP MAX UNIT V Differentialoutputvoltage 250 310 450 mV OD1 ChangeinmagnitudeofV for ΔV OD1 1 35 |mV| OD1 complementaryoutputstates VOS Offsetvoltage R =100Ω(Figure17) DOUT− 1.125 1.17 1.375 V ΔV ChangeinmagnitudeofVOSfor L DOUT+ 1 25 |mV| OS complementaryoutputstates V Outputhighvoltage 1.33 1.6 V OH V Outputlowvoltage 0.9 1.02 V OL V Inputhighvoltage 2 V V IH CC V Inputlowvoltage GND 0.8 V IL D , IN I Inputhighcurrent V =V or2.5V EN, −10 2 +10 µA IH IN CC EN* I Inputlowcurrent V =GNDor0.4V −10 −2 +10 µA IL IN V Inputclampvoltage I =−18mA −1.5 −0.8 V CL CL (1) Currentintodevicepinsisdefinedaspositive.Currentoutofdevicepinsisdefinedasnegative.Allvoltagesarereferencedtoground except:V andΔV . OD1 OD1 (2) Alltypicalsaregivenfor:V =3.3V,T =+25°C. CC A (3) TheDS90LV047Aisacurrentmodedeviceandonlyfunctionswithindatasheetspecificationswhenaresistiveloadisappliedtothe driveroutputstypicalrangeis(90Ωto110Ω). 4 SubmitDocumentationFeedback Copyright©2000–2016,TexasInstrumentsIncorporated ProductFolderLinks:DS90LV047A

DS90LV047A www.ti.com SNLS044D–MAY2000–REVISEDJULY2016 Electrical Characteristics (continued) Oversupplyvoltageandoperatingtemperatureranges,unlessotherwisespecified(1)(2)(3) PARAMETER TESTCONDITIONS PIN MIN TYP MAX UNIT ENABLED, I Outputshort-circuitcurrent(4) D =V ,D =0Vor −4.2 −9 mA OS IN CC OUT+ D =GND,D =0V IN OUT− Differentialoutputshort-circuit IOSD current(4) ENABLED,VOD=0V DOUT− −4.2 −9 mA D OUT+ V =0Vor3.6V,V =0Vor I Power-offleakage OUT CC −20 ±1 20 µA OFF Open EN=0.8VandEN*=2.0V I OutputTRI-STATEcurrent −10 ±1 10 µA OZ V =0VorV OUT CC I Noloadsupplycurrentdriversenabled D =V orGND 4 8 mA CC IN CC R =100Ωallchannels,D =V I Loadedsupplycurrentdriversenabled L IN CC 20 30 mA CCL orGND(allinputs) V CC I Noloadsupplycurrentdrivers DIN=VCCorGND,EN=GND, 2.2 6 mA CCZ disabled EN*=V CC (4) Outputshortcircuitcurrent(I )isspecifiedasmagnitudeonly,minussignindicatesdirectiononly. OS 6.6 Switching Characteristics V =+3.3V±10%,T =−40°Cto+85°C(1)(2)(3) CC A PARAMETER TESTCONDITIONS MIN TYP MAX UNIT Differentialpropagationdelayhighto t 0.5 0.9 1.7 ns PHLD low Differentialpropagationdelaylowto t 0.5 1.2 1.7 ns PLHD high t Differentialpulseskew|t −t |(4) 0 0.3 0.4 ns SKD1 PHLD PLHD R =100Ω,C =15pF tSKD2 Channel-to-channelskew(5) (FLigure18andLFigure19) 0 0.4 0.5 ns t Differentialpart-to-partskew(6) 0 1 ns SKD3 t Differentialpart-to-partskew(7) 0 1.2 ns SKD4 t Risetime 0.5 1.5 ns TLH t Falltime 0.5 1.5 ns THL t DisabletimehightoZ 2 5 ns PHZ tPLZ DisabletimelowtoZ RL=100Ω,CL=15pF 2 5 ns t EnabletimeZtohigh (Figure20andFigure21) 3 7 ns PZH t EnabletimeZtolow 3 7 ns PZL f Maximumoperatingfrequency(8) 200 250 MHz MAX (1) Alltypicalsaregivenfor:V =3.3V,T =+25°C. CC A (2) Generatorwaveformforalltestsunlessotherwisespecified:f=1MHz,Z =50Ω,t ≤1ns,andt ≤1ns. O r f (3) C includesprobeandjigcapacitance. L (4) t |t –t |isthemagnitudedifferenceindifferentialpropagationdelaytimebetweenthepositivegoingedgeandthenegative SKD1 PHLD PLHD goingedgeofthesamechannel. (5) t isthedifferentialchannel-to-channelskewofanyeventonthesamedevice. SKD2 (6) t ,differentialpart-to-partskew,isdefinedasthedifferencebetweentheminimumandmaximumspecifieddifferentialpropagation SKD3 delays.ThisspecificationappliestodevicesatthesameV andwithin5°Cofeachotherwithintheoperatingtemperaturerange. CC (7) t ,parttopartskew,isthedifferentialchannel-to-channelskewofanyeventbetweendevices.Thisspecificationappliestodevices SKD4 overrecommendedoperatingtemperatureandvoltageranges,andacrossprocessdistribution.t isdefinedas|Max−Min| SKD4 differentialpropagationdelay. (8) f generatorinputconditions:t =t <1ns(0%to100%),50%dutycycle,0Vto3V.Outputcriteria:dutycycle=45%/55%, MAX r f VOD>250mV,allchannelsswitching. Copyright©2000–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS90LV047A

DS90LV047A SNLS044D–MAY2000–REVISEDJULY2016 www.ti.com 6.7 Typical Characteristics Figure1.OutputHighVoltagevsPowerSupplyVoltage Figure2.OutputLowVoltagevsPowerSupplyVoltage Figure3.OutputShortCircuitCurrentvs Figure4.OutputTRI-STATECurrentvs PowerSupplyVoltage PowerSupplyVoltage Figure5.DifferentialOutputVoltagevs Figure6.DifferentialOutputVoltagevsLoadResistor PowerSupplyVoltage 6 SubmitDocumentationFeedback Copyright©2000–2016,TexasInstrumentsIncorporated ProductFolderLinks:DS90LV047A

DS90LV047A www.ti.com SNLS044D–MAY2000–REVISEDJULY2016 Typical Characteristics (continued) Figure7.OffsetVoltagevsPowerSupplyVoltage Figure8.PowerSupplyCurrentvsPowerSupplyVoltage Figure9.PowerSupplyCurrentvsAmbientTemperature Figure10.DifferentialPropagationDelayvs PowerSupplyVoltage Figure11.DifferentialPropagationDelayvs Figure12.DifferentialSkewvsPowerSupplyVoltage AmbientTemperature Copyright©2000–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS90LV047A

DS90LV047A SNLS044D–MAY2000–REVISEDJULY2016 www.ti.com Typical Characteristics (continued) Figure13.DifferentialSkewvsAmbientTemperature Figure14.TransitionTimevsPowerSupplyVoltage Figure15.TransitionTimevsAmbientTemperature Figure16.DataRatevsCableLength 7 Parameter Measurement Information Figure17. DriverV andV TestCircuit OD OS 8 SubmitDocumentationFeedback Copyright©2000–2016,TexasInstrumentsIncorporated ProductFolderLinks:DS90LV047A

DS90LV047A www.ti.com SNLS044D–MAY2000–REVISEDJULY2016 Parameter Measurement Information (continued) Figure18. DriverPropagationDelayandTransitionTimeTestCircuit Figure19. DriverPropagationDelayandTransitionTimeWaveforms Figure20. DriverTRI-STATEDelayTestCircuit Copyright©2000–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DS90LV047A

DS90LV047A SNLS044D–MAY2000–REVISEDJULY2016 www.ti.com Parameter Measurement Information (continued) Figure21. DriverTRI-STATEDelayWaveform 10 SubmitDocumentationFeedback Copyright©2000–2016,TexasInstrumentsIncorporated ProductFolderLinks:DS90LV047A

DS90LV047A www.ti.com SNLS044D–MAY2000–REVISEDJULY2016 8 Detailed Description 8.1 Overview LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as is shown in Figure 23. This configuration provides a clean signaling environment for the fast edge rates of the drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable,aparallelpaircable,orsimplyPCBtraces.Typically,thecharacteristicdifferentialimpedanceofthemedia isintherangeof100Ω.Aterminationresistorof100 Ω(selectedtomatchthemedia),andislocatedascloseto the receiver input pins as possible. The termination resistor converts the driver output current (current mode) into a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as wellasgroundshifting,noisemarginlimits,andtotalterminationloadingmustbetakenintoaccount. The DS90LV047A differential line driver is a balanced current source design. A current mode driver, generally speaking has a high output impedance and supplies a constant current for a range of loads (a voltage mode driverontheotherhandsuppliesaconstantvoltageforarangeofloads).Currentisswitchedthroughtheloadin one direction to produce a logic state and in the other direction to produce the other logic state. The output current is typically 3.1 mA, a minimum of 2.5 mA, and a maximum of 4.5 mA. The current mode driver requires (as discussed above) that a resistive termination be employed to terminate the signal and to complete the loop as shown in Figure 23. AC or unterminated configurations are not allowed. The 3.1-mA loop current develops a differential voltage of 310 mV across the 100-Ω termination resistor which the receiver detects with a 250-mV minimum differential noise margin, (driven signal minus receiver threshold (250 mV – 100 mV = 150 mV). The signaliscenteredaround+1.2V(DriverOffset,V )withrespecttogroundasshowninFigure22. OS NOTE The steady-state voltage (V ) peak-to-peak swing is twice the differential voltage (V ) SS OD andistypically620mV. The current mode driver provides substantial benefits over voltage mode drivers, such as an RS-422 driver. Its quiescent current remains relatively flat versus switching frequency. Whereas the RS-422 voltage mode driver increases exponentially in most case from 20 MHz to 50 MHz. This is due to the overlap current that flows between the rails of the device when the internal gates switch. Whereas the current mode driver switches a fixed current between its output without any substantial overlap current. This is similar to some ECL and PECL devices, but without the heavy static I requirements of the ECL/PECL designs. LVDS requires > 80% less CC current than similar PECL devices. AC specifications for the driver are a tenfold improvement over other existing RS-422drivers. TheTRI-STATEfunctionallowsthedriveroutputstobedisabled,thusobtaininganevenlowerpowerstatewhen thetransmissionofdataisnotrequired. Copyright©2000–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:DS90LV047A

DS90LV047A SNLS044D–MAY2000–REVISEDJULY2016 www.ti.com 8.2 Functional Block Diagram 8.3 Feature Description 8.3.1 LVDSFail-Safe Thissectionaddressesthecommonconcernoffail-safebiasingofLVDSinterconnects,specificallylookingatthe DS90LV047AdriveroutputsandtheDS90LV048Areceiverinputs. The LVDS receiver is a high-gain, high-speed device that amplifies a small differential signal (20 mV) to CMOS logiclevels.Duetothehighgainandtightthresholdofthereceiver,takecaretopreventnoisefromappearingas avalidsignal. The internal fail-safe circuitry of the receiver is designed to source or sink a small amount of current, providing fail-safe protection (a stable known state of HIGH output voltage) for floating, terminated, or shorted receiver inputs. 1. Open Input Pins. The DS90LV048A is a quad receiver device, and if an application requires only 1, 2, or 3 receivers, the unused channel(s) inputs must be left OPEN. Do not tie unused receiver inputs to ground or any other voltages. The input is biased by internal high value pullup and pulldown resistors to set the output toaHIGHstate.ThisinternalcircuitryensuresaHIGH,stableoutputstateforopeninputs. 2. Terminated Input. If the DS90LV047A driver is disconnected (cable unplugged), or if the DS90LV047A driver is in a TRI-STATE or power-off condition, the receiver output is again in a HIGH state, even with the end of cable 100-Ω termination resistor across the input pins. The unplugged cable can become a floating antenna which can pick up noise. If the cable picks up more than 10 mV of differential noise, the receiver may see the noise as a valid signal and switch. To insure that any noise is seen as common-mode and not differential, a balanced interconnect must be used. Twisted pair cable offers better balance than flat ribbon cable. 3. Shorted Inputs. If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0-V differential input voltage, the receiver output remains in a HIGH state. Shorted input fail-safe is not supported acrossthecommon-moderangeofthedevice(GNDto2.4V).Itisonlysupportedwithinputsshortedandno externalcommon-modevoltageapplied. 12 SubmitDocumentationFeedback Copyright©2000–2016,TexasInstrumentsIncorporated ProductFolderLinks:DS90LV047A

DS90LV047A www.ti.com SNLS044D–MAY2000–REVISEDJULY2016 Feature Description (continued) External lower value pullup and pulldown resistors (for a stronger bias) may be used to boost fail-safe in the presence of higher noise levels. The pullup and pulldown resistors should be in the 5-kΩ to 15-kΩ range to minimize loading and waveform distortion to the driver. The common-mode bias point should be set to approximately1.2V(lessthan1.75V)tobecompatiblewiththeinternalcircuitry. Figure22. DriverOutputLevels 8.4 Device Functional Modes Table1liststhefunctionalmodesDS90LV047A. Table1.TruthTable ENABLES INPUT OUTPUTS EN EN* D D D IN OUT+ OUT− L L H H LorOpen H H L AllothercombinationsofENABLEinputs X Z Z Copyright©2000–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:DS90LV047A

DS90LV047A SNLS044D–MAY2000–REVISEDJULY2016 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information The DS90LV047A has a flow-through pinout that allows for easy PCB layout. The LVDS signals on one side of the device easily allows for matching electrical lengths of the differential pair trace lines between the driver and the receiver as well as allowing the trace lines to be close together to couple noise as common-mode. Noise isolationisachievedwiththeLVDSsignalsononesideofthedeviceandtheTTLsignalsontheotherside. 9.2 Typical Application Figure23. Point-to-PointApplication 9.2.1 DesignRequirements When using LVDS devices, it is important to remember to specify controlled impedance PCB traces, cable assemblies, and connectors. All components of the transmission media should have a matched differential impedanceofabout100Ω.Theyshouldnotintroducemajorimpedancediscontinuities. Balanced cables (for example, twisted pair) are usually better than unbalanced cables (ribbon cable) for noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and also tend to pick up electromagnetic radiation as common-mode (not differential mode) noise which is rejected by the LVDSreceiver. For cable distances < 0.5 M, most cables can be made to work effectively. For distances 0.5 M ≤ d ≤ 10 M, CAT5(Category5)twistedpaircableworkswell,isreadilyavailableandrelativelyinexpensive. 9.2.2 DetailedDesignProcedure 9.2.2.1 ProbingLVDSTransmissionLines Always use high impedance (> 100 kΩ), low capacitance (< 2 pF) scope probes with a wide bandwidth (1 GHz) scope.Improperprobinggivesdeceivingresults. 9.2.2.2 DataRatevsCableLengthGraphTestProcedure A pseudo-random bit sequence (PRBS) of 29−1 bits was programmed into a function generator (Tektronix HFS9009) and connected to the driver inputs through 50-Ω cables and SMB connectors. An oscilloscope (Tektronix 11801B) was used to probe the resulting eye pattern, measured differentially at the input to the receiver. A 100-Ω resistor was used to terminate the pair at the far end of the cable. The measurements were taken at the far end of the cable, at the input of the receiver, and used for the jitter analysis for this graph (Figure 16). The frequency of the input signal was increased until the measured jitter (t ) equaled 20% with tcs respect to the unit interval (t ) for the particular cable length under test. Twenty percent jitter is a reasonable tui place to start with many system designs. The data used was NRZ. Jitter was measured at the 0-V differential voltage of the differential eye pattern. The DS90LV047A and DS90LV048A can be evaluated using the new DS90LV047-048AEVM. 14 SubmitDocumentationFeedback Copyright©2000–2016,TexasInstrumentsIncorporated ProductFolderLinks:DS90LV047A

DS90LV047A www.ti.com SNLS044D–MAY2000–REVISEDJULY2016 Typical Application (continued) Figure 24 shows very good typical performance that can be used as a design guideline for data rate vs cable length. Increasing the jitter percentage increases the curve respectively, allowing the device to transmit faster over longer cable lengths. This relaxes the jitter tolerance of the system allowing more jitter into the system, which could reduce the reliability and efficiency of the system. Alternatively, decreasing the jitter percentage has the opposite effect on the system. The area under the curve is considered the safe operating area based on the above signal quality criteria. For more information on eye pattern testing, please see AN-808 Long Transmission LinesandDataSignalQuality (SNLA028). 9.2.3 ApplicationCurve Figure24. PowerSupplyCurrentvsFrequency Copyright©2000–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:DS90LV047A

DS90LV047A SNLS044D–MAY2000–REVISEDJULY2016 www.ti.com 10 Power Supply Recommendations Although the DS90LV047A draws very little power while at rest. At higher switching frequencies there is a dynamic current component which increases the overall power consumption. The DS90LV047A power supply connectionmusttakethisadditionalcurrentconsumptionintoconsiderationformaximumpowerrequirements. 11 Layout 11.1 Layout Guidelines • Useatleast4PCBlayers(toptobottom);LVDSsignals,ground,power,TTLsignals. • Isolate TTL signals from LVDS signals, otherwise the TTL may couple onto the LVDS lines. It is best to put TTLandLVDSsignalsondifferentlayerswhichareisolatedbyapower/groundplane(s). • Keepdriversandreceiversasclosetothe(LVDSportside)connectorsaspossible. 11.1.1 PowerDecouplingRecommendations Bypass capacitors must be used on power pins. Use high frequency ceramic (surface mount is recommended) 0.1-µFand0.001-µFcapacitorsinparallelatthepowersupplypinwiththesmallestvaluecapacitorclosesttothe device supply pin. Additional scattered capacitors over the printed-circuit board improves decoupling. Multiple vias must be used to connect the decoupling capacitors to the power planes. A 10-µF (35-V) or greater solid tantalum capacitor must be connected at the power entry point on the printed-circuit board between the supply andground. 11.1.2 DifferentialTraces Use controlled impedance traces which match the differential impedance of your transmission medium (that is, cable) and termination resistor. Run the differential pair trace lines as close together as possible as soon as they leave the IC (stubs must be < 10 mm long). This helps eliminate reflections and ensure noise is coupled as common-mode. In fact, we have seen that differential signals which are 1 mm apart radiate far less noise than traces 3 mm apart since magnetic field cancellation is much better with the closer traces. In addition, noise induced on the differential lines is much more likely to appear as common-mode which is rejected by the receiver. Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase difference between signals, which destroys the magnetic field cancellation benefits of differential signals and EMI,results. NOTE The velocity of propagation, v = c/Er where c (the speed of light) = 0.2997mm/ps or 0.0118in/ps Do not rely solely on the autoroute function for differential traces. Carefully review dimensions to match differential impedance and provide isolation for the differential lines. Minimize the number or vias and other discontinuitiesontheline. Avoid90° turns(thesecauseimpedancediscontinuities).Usearcsor45° bevels. Within a pair of traces, the distance between the two traces must be minimized to maintain common-mode rejection of the receivers. On the printed-circuit board, this distance must remain constant to avoid discontinuities indifferentialimpedance.Minorviolationsatconnectionpointsareallowable. 11.1.3 Termination Use a termination resistor which best matches the differential impedance or your transmission line. The resistor must be between 90 Ω and 130 Ω. Remember that the current mode outputs need the termination resistor to generate the differential voltage. LVDS does not work without resistor termination. Typically, connecting a single resistoracrossthepairatthereceiverendwillsuffice. 16 SubmitDocumentationFeedback Copyright©2000–2016,TexasInstrumentsIncorporated ProductFolderLinks:DS90LV047A

DS90LV047A www.ti.com SNLS044D–MAY2000–REVISEDJULY2016 Layout Guidelines (continued) Surface mount 1% to 2% resistors are best. PCB stubs, component lead, and the distance from the termination to the receiver inputs must be minimized. The distance between the termination resistor and the receiver should be<10mm(12mmmaximum). 11.2 Layout Example DS90LV047A DS90LV048A 1 EN DOUT1- 16 1 RIN1- EN 16 Series Termination (optional) 2 DIN1 DOUT1+ 15 2 RIN1+ ROUT1 15 LVCMOS LVCMOS Inputs 3 DIN2 DOUT2+ 14 3 RIN2+ ROUT2 14 Outputs 4 VCC DOUT2- 13 4 RIN2- VCC 13 Decoupling Cap 5 GND DOUT3- 12 5 RIN3- GND 12 Decoupling Cap 6 DIN3 DOUT3+ 11 6 RIN3+ ROUT3 11 7 DIN4 DOUT4+ 10 7 RIN4+ ROUT4 10 8 EN* DOUT4- 9 8 RIN4- EN* 9 Series Termination (optional) Input Termination (Required) Figure25. LayoutRecommendation Copyright©2000–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:DS90LV047A

DS90LV047A SNLS044D–MAY2000–REVISEDJULY2016 www.ti.com 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 RelatedDocumentation Forrelateddocumentation,seethefollowing: • LVDSOwner'sManual(SNLA187) • AN-808LongTransmissionLinesandDataSignalQuality (SNLA028) • AN-977LVDSSignalQuality:JitterMeasurementsUsingEyePatternsTestReport#1 (SNLA166) • AN-971AnOverviewofLVDSTechnology (SNLA165) • AN-916APracticalGuidetoCableSelection(SNLA219) • AN-805CalculatingPowerDissipationforDifferentialLineDrivers (SNOA233) • AN-903AComparisonofDifferentialTerminationTechniques (SNLA034) • AN-1194FailsafeBiasingofLVDSInterfaces (SNLA051) 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument. 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 12.4 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 12.5 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 12.6 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 18 SubmitDocumentationFeedback Copyright©2000–2016,TexasInstrumentsIncorporated ProductFolderLinks:DS90LV047A

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) DS90LV047ATM NRND SOIC D 16 48 TBD Call TI Call TI -40 to 85 DS90LV047A TM DS90LV047ATM/NOPB ACTIVE SOIC D 16 48 Green (RoHS SN Level-1-260C-UNLIM -40 to 85 DS90LV047A & no Sb/Br) TM DS90LV047ATMTC NRND TSSOP PW 16 92 TBD Call TI Call TI -40 to 85 DS90LV 047AT DS90LV047ATMTC/NOPB ACTIVE TSSOP PW 16 92 Green (RoHS SN Level-1-260C-UNLIM -40 to 85 DS90LV & no Sb/Br) 047AT DS90LV047ATMTCX/NOPB ACTIVE TSSOP PW 16 2500 Green (RoHS SN Level-1-260C-UNLIM -40 to 85 DS90LV & no Sb/Br) 047AT DS90LV047ATMX/NOPB ACTIVE SOIC D 16 2500 Green (RoHS SN Level-1-260C-UNLIM -40 to 85 DS90LV047A & no Sb/Br) TM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2016 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) DS90LV047ATMTCX/NO TSSOP PW 16 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1 PB DS90LV047ATMX/NOPB SOIC D 16 2500 330.0 16.4 6.5 10.3 2.3 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2016 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) DS90LV047ATMTCX/NOP TSSOP PW 16 2500 367.0 367.0 35.0 B DS90LV047ATMX/NOPB SOIC D 16 2500 367.0 367.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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