CM1293A-04SO 4-Channel Low Capacitance ESD Protection Array Product Description CM1293A−04SO has been designed to provide ESD protection for http://onsemi.com electronic components or subsystems requiring minimal capacitive loading. This device is ideal for protecting systems with high data and clock rates or for circuits requiring low capacitive loading. Each ESD channel consists of a pair of diodes in series that steer the positive or SC−74 negative ESD current pulse to either the positive (V ) or negative (V ) SO SUFFIX P N CASE 318F supply rail. A Zener diode is embedded between VP and VN which helps protect the V rail against ESD strikes. This device protects CC BLOCK DIAGRAM against ESD pulses up to 8 kV contact discharge) per the IEC61000−4−2 Level 4 standard. VP This device is particularly well−suited for protecting systems using CH1 CH2 CH3 CH4 high−speed ports such as USB2.0, IEEE1394 (FireWire, i.LINK(cid:2)), Serial ATA, DVI, HDMI, and corresponding ports in removable storage, digital camcorders, DVD−RW drives and other applications where extremely low loading capacitance with ESD protection are required in a small package footprint. VN CM1293A−04SO Features  Four Channels of ESD Protection MARKING DIAGRAM  Provides ESD Protection to IEC61000−4−2  8 kV Contact Discharge  Low Loading Capacitance of 2.0 pF Max XXXM(cid:3) (cid:3)  Low Clamping Voltage 1  Channel I/O to I/O Capacitance 1.5 pF Typical  Zener Diode Protects Supply Rail and Eliminates the Need for External By−Pass Capacitors XXX = Specific Device Code M = Date Code  Each I/O Pin Can Withstand over 1000 ESD Strikes* (cid:3) = Pb−Free Package  This Device is Pb−Free and is RoHS Compliant** (Note: Microdot may be in either location) Applications ORDERING INFORMATION  DVI Ports, HDMI Ports in Notebooks, Set Top Boxes, Digital TVs, LCD Displays Device Package Shipping†  Serial ATA Ports in Desktop PCs and Hard Disk Drives CM1293A−04SO SC−74 3,000 / (Pb−Free) Tape & Reel  PCI Express Ports  General Purpose High−Speed Data Line ESD Protection †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. **Standard test condition is IEC61000−4−2 level 4 test circuit with each pin subjected to 8 kV contact discharge for 1000 pulses. Discharges are timed at 1 second intervals and all 1000 strikes are completed in one continuous test run. The part is then subjected to standard production test to verify that all of the tested parameters are within spec after the 1000 strikes. **For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.  Semiconductor Components Industries, LLC, 2012 1 Publication Order Number: January, 2012 − Rev. 0 CM1293A−04SO/D

CM1293A−04SO PACKAGE/PINOUT DIAGRAM Table 1. PIN DESCRIPTIONS Pin Name Type Description Top View 1 CH1 I/O ESD Channel CH1 CH4 2 VN GND Negative Voltage Supply Rail VN 63 VP 3 CH2 I/O ESD Channel 5 CH2 CH3 4 CH3 I/O ESD Channel 4−Channel SC−74 5 VP PWR Positive Voltage Supply Rail 6 CH4 I/O ESD Channel SPECIFICATIONS Table 2. ABSOLUTE MAXIMUM RATINGS Parameter Rating Units Operating Supply Voltage (VP − VN) 6.0 V Operating Temperature Range –40 to +85 C Storage Temperature Range –65 to +150 C DC Voltage at any Channel Input (VN − 0.5) to (VP + 0.5) V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 3. STANDARD OPERATING CONDITIONS Parameter Rating Units Operating Temperature Range –40 to +85 C Package Power Rating 225 mW Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note 1) Symbol Parameter Conditions Min Typ Max Units VP Operating Supply Voltage (VP−VN) 3.3 5.5 V IP Operating Supply Current (VP−VN) = 3.3 V 8.0 (cid:2)A VF Diode Forward Voltage IF = 8 mA, TA = 25C 0.90 V ILEAK Channel Leakage Current TA = 25C, VP = 5 V, VN = 0 V 0.1 1.0 (cid:2)A CIN Channel Input Capacitance At 1 MHz, VP = 3.3 V, VN = 0 V, VIN = 1.65 V 2.0 pF (cid:3)CIO Channel I/O to I/O Capacitance 1.5 pF VESD ESD Protection kV Peak Discharge Voltage at any Channel Input, in System Contact Discharge per TA = 25C (Notes 2 and 3) 8 IEC 61000−4−2 Standard VCL Channel Clamp Voltage TA = 25C, IPP = 1A, tP = 8/20 (cid:2)S V Positive Transients (Note 3) +9.9 Negative Transients –1.6 RDYN Dynamic Resistance TA = 25C, IPP = 1A, tP = 8/20 (cid:2)S (cid:4) Positive Transients (Note 3) 0.96 Negative Transients 0.5 1. All parameters specified at TA = –40C to +85C unless otherwise noted. 2. Standard IEC 61000−4−2 with CDischarge = 150 pF, RDischarge = 330 (cid:4), VP = 3.3 V, VN grounded. 3. These measurements performed with no external capacitor on VP. http://onsemi.com 2

CM1293A−04SO PERFORMANCE INFORMATION Input Channel Capacitance Performance Curves Figure 1. Typical Variation of C vs. V IN IN (f = 1 MHz, V = 3.3 V, V = 0 V, 0.1 (cid:2)F Chip Capacitor between V and V , 25(cid:2)C) P N P N Figure 2. Typical Variation of C vs. Temp IN (f = 1 MHz, V = 30 mV, V = 3.3 V, V = 0 V, 0.1 (cid:2)F Chip Capacitor between V and V ) IN P N P N http://onsemi.com 3

CM1293A−04SO PERFORMANCE INFORMATION (Cont’d) Typical Filter Performance (nominal conditions unless specified otherwise, 50 (cid:3) Environment) Figure 3. Insertion Loss (S21) vs. Frequency (0 V DC Bias, VP = 3.3 V) Figure 4. Insertion Loss (S21) vs. Frequency (2.5 V DC Bias, VP = 3.3 V) http://onsemi.com 4

CM1293A−04SO APPLICATION INFORMATION Design Considerations In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic series inductances on the Supply/Ground rails as well as the signal trace segment between the signal input (typically a connector) and the ESD protection device. Refer to Figure 5, which illustrates an example of apositive ESD pulse striking an input channel. The parasitic series inductance back to the power supply is represented by L1 and L2. The voltage VCL on the line being protected is: VCL = Fwd voltage drop of D1 + VSUPPLY + L1 x d(IESD) / dt+ L2 x d(IESD) / dt where I is the ESD current pulse, and V is the positive supply voltage. ESD SUPPLY An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge per the IEC61000−4−2 standard results in a current pulse that rises from zero to 30 Amps in 1 ns. Here d(I )/dt can be ESD approximated by (cid:3)IESD/(cid:3)t, or 30/(1x10−9). So just 10 nH of series inductance (L1 and L2 combined) will lead to a 300V increment in V ! CL Similarly for negative ESD pulses, parasitic series inductance from the V pin to the ground rail will lead to drastically N increased negative voltage on the line being protected. The CM1293 has an integrated Zener diode between V and V . This greatly reduces the effect of supply rail inductance P N L on V by clamping V at the breakdown voltage of the Zener diode. However, for the lowest possible V , especially when 2 CL P CL VP is biased at a voltage significantly below the Zener breakdown voltage, it is recommended that a 0.22 F ceramic chip capacitor be connected between V and the ground plane. P As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the V pin of the Protection P Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the ESD device to minimize stray series inductance. L2 POSITIVE SUPPLY RAIL VCC VP PATH OF ESD CURRENT PULSE IESO ÇÇÇÇÇÇ ÇÇÇÇÇÇ ÇÇÇÇÇÇ LINE BEING ÇÇDÇ1 ÇÇÇ L1 PROTECTED ÇÇSYÇSTEMÇ ORÇÇ 0.22 (cid:2)F ÇÇÇÇÇÇ ÇÇCIRÇCUITÇRYÇÇ BEING ONE CHANNEL ÇÇÇCHÇANNÇEL Ç INPUT ÇÇPRÇOTEÇCTEÇD Ç D2 25 A VCL ÇÇÇÇÇÇ ÇÇÇÇÇÇ 0 A GROUND RAIL VN CHASSIS GROUND Figure 5. Application of Positive ESD Pulse between Input Channel and Ground http://onsemi.com 5

CM1293A−04SO PACKAGE DIMENSIONS SC−74 CASE 318F−05 ISSUE M NOTES: D 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD 6 5 4 THICKNESS IS THE MINIMUM THICKNESS HE E 4. 3O1F8 FB−A0S1E, −M0A2T, E−R03IA, −L.04 OBSOLETE. NEW 1 2 3 STANDARD 318F−05. MILLIMETERS INCHES b DIM MIN NOM MAX MIN NOM MAX A 0.90 1.00 1.10 0.035 0.039 0.043 e A1 0.01 0.06 0.10 0.001 0.002 0.004 b 0.25 0.37 0.50 0.010 0.015 0.020 c 0.10 0.18 0.26 0.004 0.007 0.010 (cid:4) D 2.90 3.00 3.10 0.114 0.118 0.122 C E 1.30 1.50 1.70 0.051 0.059 0.067 0.05 (0.002) A e 0.85 0.95 1.05 0.034 0.037 0.041 L 0.20 0.40 0.60 0.008 0.016 0.024 L HE 2.50 2.75 3.00 0.099 0.108 0.118 A1 (cid:4) 0 − 10 0 − 10 SOLDERING FOOTPRINT* 2.4 0.094 0.95 1.9 0.037 0.074 0.95 0.7 0.037 0.028 1.0 0.039 (cid:2) mm (cid:3) SCALE 10:1 inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. FireWire is a registered trademark of Apple Computer, Inc. i.LINK is a trademark of Sony Corporation. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative http://onsemi.com CM1293A−04SO/D 6

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