CLC007 www.ti.com SNLS016E–JULY1998–REVISEDAPRIL2013 CLC007 Serial Digital Cable Driver with Dual Complementary Outputs CheckforSamples:CLC007 FEATURES DESCRIPTION 1 • NoExternalPull-DownResistors The Texas Instruments Comlinear CLC007 is a 2 monolithic, high-speed cable driver designed for the • DifferentialInputandOutput SMPTE 259M serial digital video data transmission • LowPowerDissipation standard. The CLC007 drives 75Ω transmission lines • Single+5Vor−5.2VSupply (Belden 8281 or equivalent) at data rates up to 400 Mbps. Controlled output rise and fall times (750 ps • ReplacesGS9007inMostApplications typical) minimize transition-induced jitter. The output voltage swing, typically 1.65V, set by an accurate, APPLICATIONS low-drift internal bandgap reference, delivers an 800 • DigitalRoutersandDistributionAmplifiers mV swing to back-matched and terminated 75Ω cable. • CoaxialCableDriverforDigitalTransmission Line The CLC007’s class AB output stage consumes less power than other designs, 195 mW with all outputs • TwistedPairDriver terminated, and requires no external bias resistors. • DigitalDistributionAmplifiers The differential inputs accept a wide range of digital • SMPTE,Sonet/SDH,andATMCompatible signals from 200 mV to ECL levels within the P-P Driver specified common-mode limits. All this make the CLC007 an excellent general purpose high speed • BufferApplications driverfordigitalapplications. KEY SPECIFICATION The CLC007 is powered from a single +5V or −5.2V supplyandcomesinan8-pinSOICpackage. • 650psRiseandFallTimes • DataRatesto400Mbps • 2SetsofComplimentaryOutputs • 200mVDifferentialInput • LowResidualJitter(25ps ) pp 270 Mbps Eye Pattern Connection Diagram Q0 1 8 V CC Q0 2 7 V IN+ Q1 3 6 V IN- Q1 4 5 V EE 0 1 2 3 4 5 6 TIME (1 ns/Div) Figure2. 8-PinSOIC SeeDPackage Figure1. 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. Alltrademarksarethepropertyoftheirrespectiveowners. 2 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©1998–2013,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

CLC007 SNLS016E–JULY1998–REVISEDAPRIL2013 www.ti.com Typical Application VCC 75:(cid:3)Coax 75: 0.1 PF 80.6: 80.6: 8 75: 7 1 VIN+ + 2 75: 0.1 PF 75:(cid:3)Coax CLC007 75: 6 - 3 75:(cid:3)Coax VIN- 4 75: 0.1 PF 5 133: 133: 75: 75:(cid:3)Coax 75: 0.1 PF VEE 75: Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. ABSOLUTE MAXIMUM RATINGS (1)(2) SupplyVoltage 6V OutputCurrent 30mA MaximumJunctionTemperature +125°C StorageTemperatureRange −65°Cto+150°C LeadTemperature (Soldering10Second) +300°C ESDRating(HumanbodyModel) 1000V PackageThermalResistance θ 8–pinSOIC +160°C JA θ 8–pinSOIC +105°C/W JC ReliabilityInformation MTTF 254Mhr (1) AbsoluteMaximumRatingsarethosevaluesbeyondwhichthesafetyofthedevicecannotbeensured.Theyarenotmeanttoimplythat thedevicesshouldbeoperatedattheselimits.ThetableofELECTRICALCHARACTERISTICSspecifiesconditionsofdeviceoperation. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexasInstrumentsSalesOffice/Distributorsforavailabilityand specifications. RECOMMENDED OPERATING CONDITIONS SupplyVoltage(V –V ) +4.5Vto+5.5V CC EE 2 SubmitDocumentationFeedback Copyright©1998–2013,TexasInstrumentsIncorporated ProductFolderLinks:CLC007

CLC007 www.ti.com SNLS016E–JULY1998–REVISEDAPRIL2013 ELECTRICAL CHARACTERISTICS (V =0V,V =−5V;unlessotherwisespecified). CC EE Min/Max Min/Max Min/Max Parameter Conditions Typ+25°C 0°C −40°Cto Units +25°C to+70°C +85°C STATICPERFORMANCE SupplyCurrent,Loaded See (1) 39 — — — mA SupplyCurrent,Unloaded See (2) 34 28/45 26/47 26/47 mA OutputHIGHVoltage(V ) See (2) −1.7 −2.0/1.4 −2.0/1.4 −2.0/1.4 V OH OutputLowVoltage(V ) See (2) −3.3 −3.6/3.0 −3.6/3.0 −3.6/3.0 V OL InputBiasCurrent 10 30 50 50 μA OutputSwing See (2) 1.65 1.55/1.75 1.53/1.77 1.51/1.79 V CommonModeInputRangeUpperLimit −0.7 −0.8 −0.8 −0.8 V CommonModeInputRangeLowerLimit −2.6 −2.5 −2.5 −2.5 V MinimumDifferentialInputSwing 200 200 200 200 mV PowerSupplyRejectionRatio (2) 26 20 20 20 dB ACPERFORMANCE OutputRiseandFallTime See (1)(2)(3) 650 425/955 400/1100 400/1100 ps Overshoot 5 % PropagationDelay 1.0 ns DutyCycleDistortion 50 ps ResidualJitter 25 — — — ps pp MISCELLANEOUSPERFORMANCE InputCapacitance 1.0 pF OutputResistance 10 Ω OutputInductance 6 nH (1) Measuredwithbothoutputsdriving150Ω,ACcoupledat270Mbps. (2) Specis100%testedat+25°C (3) Measuredbetweenthe20%and80%levelsofthewaveform. Copyright©1998–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:CLC007

CLC007 SNLS016E–JULY1998–REVISEDAPRIL2013 www.ti.com OPERATION Input Interfacing The CLC007 has high impedance, emitter-follower buffered, differential inputs. Single-ended signals may also be input.TransmissionlinessupplyinginputsignalsmustbeproperlyterminatedclosetotheCLC007.EitherA.C.or D.C. coupling as in Figure 4 or Figure 5 may be used. Figure 4, Figure 6, and Figure 7 show how Thevenin- equivalent resistor networks are used to provide input termination and biasing. The input D.C. common-mode voltagerangeis0.8Vto2.5Vbelowthepositivepowersupply(V ).Inputsignalsplusbiasshouldbekeptwithin CC the specified common-mode range. For an 800 mV input signal, typical input bias levels range from 1.2V to P-P 2.1Vbelowthepositivesupply. LoadType ResistortoV (R1) ResistortoV (R2) CC EE ECL,50Ω,5V,V =2V 82.5Ω 124Ω T ECL,50Ω,5.2V,V =2V 80.6Ω 133Ω T ECL,75Ω,5V,V =2V 124Ω 187Ω T ECL,75Ω,5.2V,V =2V 121Ω 196Ω T 800mV ,50Ω,5V,V =1.6V 75.0Ω 154Ω P-P T 800mV ,75Ω,5V,V =1.6V 110Ω 232Ω P-P T 800mV ,2.2KΩ,5V,V =1.6V 3240Ω 6810Ω P-P T VCC VIN+ VIN- To next stage VEE Figure3. InputStage VCC VCC ECL Output R1 R1 Z0 8 0.1 PF 7 + 1 2 CLC007 VTT 6 - 3 4 0.1 PF Z0 5 R2 R2 VTT VEE VEE Figure4. ACCoupledInput 4 SubmitDocumentationFeedback Copyright©1998–2013,TexasInstrumentsIncorporated ProductFolderLinks:CLC007

CLC007 www.ti.com SNLS016E–JULY1998–REVISEDAPRIL2013 VCC ECL Output Z0 8 7 + 1 2 CLC007 6 - 3 4 Z0 5 = Z0 = Z0 VTT VEE Figure5. DCCoupledInput VCC R6 C1 J3 75: 0.1 PF R5 R4 75: 75: 8 7 4 R7 C2 + 3 75: 0.1 PF J4 CLC007 J2 6 - 2 R8 C3 J5 75: 0.1 PF VIN+ 1 5 R3 R1 154: 154: R9 C4 J6 75: 0.1 PF VEE Figure6. SingleEnded50Ω ECLInput Copyright©1998–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:CLC007

CLC007 SNLS016E–JULY1998–REVISEDAPRIL2013 www.ti.com VCC R6 C1 J3 75: 0.1 PF R5 R4 75: 75: 8 7 4 R7 C2 VJI1N- + 3 75: 0.1 PF J4 CLC007 J2 6 - 2 R8 C3 J5 75: 0.1 PF VIN+ 1 5 R3 R1 154: 154: R9 C4 J6 75: 0.1 PF VEE Figure7. Differential50Ω ECLInput Output Interfacing The CLC007’s class AB output stage, Figure 8, requires no standing current in the output transistors and therefore requires no biasing or pull-down resistors. Advantages of this arrangement are lower power dissipation and fewer external components. The output may be either D.C. or A.C. coupled to the load. A bandgap voltage reference sets output voltage levels which are compatible with F100K and 10K ECL when correctly terminated. The outputs do not have the same output voltage temperature coefficient as 10K. Therefore, noise margins will be reduced over the full temperature range when driving 10K ECL. Noise margins will not be affected when interfacingtoF100KsinceF100Kisfullyvoltageandtemperaturecompensated. VCC VEE VCC VEE Figure8. OutputStage 6 SubmitDocumentationFeedback Copyright©1998–2013,TexasInstrumentsIncorporated ProductFolderLinks:CLC007

CLC007 www.ti.com SNLS016E–JULY1998–REVISEDAPRIL2013 VCC for 75:(cid:3)input: R1 = R3 = 232: R4 = R5 = 110: R6 75:(cid:3)Coax 75: J3 R5 R4 75: 75: 8 75: VJIN1+ 7 + 1 2 7R57: J4 75:(cid:3)Coax CLC007 75: J2 6 - 3 R8 75:(cid:3)Coax 75: VIN- 4 J5 5 R3 R1 154: 154: 75: RIN = 50: 7R59: J6 75:(cid:3)Coax VBIAS = VCC - 1.62V VEE 75: VCC - VEE = +5V Figure9. DifferentialInputDCCoupledOutput Copyright©1998–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:CLC007

CLC007 SNLS016E–JULY1998–REVISEDAPRIL2013 www.ti.com Output Rise And Fall Times Output load capacitance can significantly affect output rise and fall times. The effect of load capacitance, stray or otherwise, may be reduced by placing the output back-match resistor close to the output pin and by minimizing all interconnecting trace lengths. Figure 10 shows the effect on risetime of parallel load capacitance across a 150Ω load. 50 Fd) 40 p E ( C N A 30 T CI A P A 20 C T U P UT 10 O 0 500 1000 1500 2000 2500 3000 RISE TIME (ps) Figure10. RiseTimevsC L PCB Layout Recommendations Printed circuit board layout affects the performance of the CLC007. The following guidelines will aid in achieving satisfactorydeviceperformance. • Useagroundplaneorpower/groundplanesandwichdesignforoptimumperformance. • Bypass device power with a 0.01 µF monolithic ceramic capacitor in parallel with a 6.8 µF tantalum electrolyticcapacitorlocatednomorethan0.1”(2.5mm)fromthedevicepowerpins. • Provideshort,symmetricalgroundreturnpathsfor: – Inputs, – Supplybypasscapacitorsand – Theoutputload. • Provideshort,groundedguardtraceslocated – Underthecenterlineofthepackage, – 0.1”(2.5mm)fromthepackagepins – Onbothtopandbottomoftheboardwithconnectingvias. 8 SubmitDocumentationFeedback Copyright©1998–2013,TexasInstrumentsIncorporated ProductFolderLinks:CLC007

CLC007 www.ti.com SNLS016E–JULY1998–REVISEDAPRIL2013 REVISION HISTORY ChangesfromRevisionD(April2013)toRevisionE Page • ChangedlayoutofNationalDataSheettoTIformat............................................................................................................ 8 Copyright©1998–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:CLC007

PACKAGE OPTION ADDENDUM www.ti.com 4-Nov-2016 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) CLC007BM/NOPB ACTIVE SOIC D 8 95 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 85 CLC00 & no Sb/Br) 7BM>D CLC007BMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 85 CLC00 & no Sb/Br) 7BM>D (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 4-Nov-2016 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) CLC007BMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CLC007BMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 PackMaterials-Page2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

IMPORTANTNOTICEANDDISCLAIMER TIPROVIDESTECHNICALANDRELIABILITYDATA(INCLUDINGDATASHEETS),DESIGNRESOURCES(INCLUDINGREFERENCE DESIGNS),APPLICATIONOROTHERDESIGNADVICE,WEBTOOLS,SAFETYINFORMATION,ANDOTHERRESOURCES“ASIS” ANDWITHALLFAULTS,ANDDISCLAIMSALLWARRANTIES,EXPRESSANDIMPLIED,INCLUDINGWITHOUTLIMITATIONANY IMPLIEDWARRANTIESOFMERCHANTABILITY,FITNESSFORAPARTICULARPURPOSEORNON-INFRINGEMENTOFTHIRD PARTYINTELLECTUALPROPERTYRIGHTS. TheseresourcesareintendedforskilleddevelopersdesigningwithTIproducts.Youaresolelyresponsiblefor(1)selectingtheappropriate TIproductsforyourapplication,(2)designing,validatingandtestingyourapplication,and(3)ensuringyourapplicationmeetsapplicable standards,andanyothersafety,security,orotherrequirements.Theseresourcesaresubjecttochangewithoutnotice.TIgrantsyou permissiontousetheseresourcesonlyfordevelopmentofanapplicationthatusestheTIproductsdescribedintheresource.Other reproductionanddisplayoftheseresourcesisprohibited.NolicenseisgrantedtoanyotherTIintellectualpropertyrightortoanythird partyintellectualpropertyright.TIdisclaimsresponsibilityfor,andyouwillfullyindemnifyTIanditsrepresentativesagainst,anyclaims, damages,costs,losses,andliabilitiesarisingoutofyouruseoftheseresources. TI’sproductsareprovidedsubjecttoTI’sTermsofSale(www.ti.com/legal/termsofsale.html)orotherapplicabletermsavailableeitheron ti.comorprovidedinconjunctionwithsuchTIproducts.TI’sprovisionoftheseresourcesdoesnotexpandorotherwisealterTI’sapplicable warrantiesorwarrantydisclaimersforTIproducts. MailingAddress:TexasInstruments,PostOfficeBox655303,Dallas,Texas75265 Copyright©2019,TexasInstrumentsIncorporated