Features n RoHS compliant* n Convex and concave terminals n 2, 4 or 8 isolated elements available n Resistance tolerance ±1 % and ±5 % n Resistance range: 10 ohms to 1 megohm CAT/CAY 16 Series - Chip Resistor Arrays Specifications Requirement Characteristics Test Method Short Time Overload ±2 % +0.1 ohm Rated Voltage X 2.5, 5 seconds Soldering Heat ±2 % +0.1 ohm 260 °C ±5 °C, 10 seconds ±1 second 125 °C (30 minutes) - normal (15 minutes) Temperature Cycling (5) ±1 % + 0.1 ohm -55 °C (30 minutes) - normal (15 minutes) Moisture Load Life ±3 % +0.1 ohm 1000 hours Load Life ±3 % +0.1 ohm 1000 hours Characteristics How To Order CA Y 16 - 103 J 4 LF Characteristics CAT16/CAY16 Chip Arrays Type Number of Elements 2 (J2), 4 (F4, J4), 8 (F8, J8) • CAT16 = Concave Terminations • CAY16 = Convex Terminations Power Rating Per Resistor @ 70 °C 0.0625 W Resistance Code 0.250 W • For 1 % Tolerance: P ackage Power Rating @ 70 °C (0.125 W for J2) <100 ohms - “R” represents decimal point (example: 24R3 = 24.3 ohms) Temperature Coefficient of Resistance ±200 PPM/°C ≥100 ohms - First three digits are significant, fourth digit represents Resistance Tolerance ±1 %, ±5 % number of zeros to follow (example: 8252 = 82.5k ohms) Resistance Range: E24 (J), E96 + E24 (F) • For 5 % Tolerance: 10 ohms - 1 megohm Zero-Ohm Jumper < 0.05 ohm <10 ohms - “R” represents decimal point (example: 4R7 = 4.7 ohms) Max. Working Voltage 50 V (25 V for CAY16-J8) ≥10 ohms - First two digits are signifi- cant, third digit represents number of Max. Overload Voltage 100 V (50 V for CAY16-J8) zeros to follow (example: 474 = 470k ohms) Operating Temp. Range -55 °C - 125 °C • 000 = Zero Ohm Jumper Resistance Tolerance • J = ±5 % (2, 4, 8 resistor pkg. and for Soldering Profile for RoHS Compliant Chip Resistors and Arrays Zero Ohm Jumper) 275 • F = ±1 % (4 resistor pkg. and CAT16-F8) <1>Maximum of 20 seconds between 260 °C peak Resistors +255 °C and +260 °C < 1 > 255 °C • 2 = 2 Isolated Resistors • 4 = 4 Isolated Resistors 225 • 8 = 8 Isolated Resistors 220 °C C) Terminations e (° 190 °C s6e0c o- n9d0s • LF = Tin-plated (RoHS compliant) ur175 at 150 °C Ramp Down er 6 °C/second p m Packaging Size Te125 60 - 120 seconds J2 ..........0606 Package Size 10 seconds minimum F4, J4 ....1206 Package Size 75 F8 ..........2406 Package Size for CAT16 Ramp Up 3 °C/second maximum J8 ..........2406 Package Size for CAT16; 1506 Package Size for CAY16 25 0 50 100 150 200 250 300 Time (Seconds) For Standard Values Used in Capacitors, Inductors, and Resistors, click here. WARNING Cancer and Reproductive Harm - www.P65Warnings.ca.gov *RoHS Directive 2002/95/EC Jan. 27, 2003 including annex and RoHS Recast 2011/65/EU June 8, 2011. Specifications are subject to change without notice. Users should verify actual device performance in their specific applications. The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.

CAT/CAY 16 Series - Chip Resistor Arrays Derating Curve Schematics %) CAT16-J2(cid:20) CAT16-F4, -J4(cid:20) ge ( 100 CAY16-J2 C(cid:20)AY16-F4, -J4(cid:20) a cent 80 R1 R2 R1 R2 R3 R4 per 60 n er i 40 w CAT16-F8, -J8(cid:20) d po 20 C(cid:20)AY16-J8(cid:20) e Rat 0 -55 0 70 125 R1 R2 R3 R4 R5 R6 R7 R8 Ambient Temperature (˚C) Dimensions Model A A’ B C D E F 0.40 ± 0.15 3.20 ± 0.20 0.80 ± 0.10 1.60 ± 0.20 0.50 ± 0.10 0.30 ± 0.15 CAT16-F4 — (.016 ± .006) (.126 ± .008) (.032 ± .004) (.063 ± .008) (.020 ± .004) (.012 ± .006) 0.40 ± 0.15 3.20 ± 0.20 0.80 ± 0.10 1.55 ± 0.25 0.50 ± 0.10 0.30 ± 0.20 CAT16-J4 — (.016 ± .006) (.126 ± .008) (.032 ± ± .004) (.061 ± .0098) (.020 ± .004) (.012 ± .008) CAY16-F4, -J4 0.50 ± 0.15 0.70 ± 0.10 3.20 ± 0.20 0.80 ± 0.05 1.60 ± 0.20 0.50 ± 0.10 0.30 ± 0.20 (.002 ± .006) (.027 ± .004) (.126 ± .008) (.032 ± .002) (.063 ± .008) (.020 ± .004) (.012 ± .008) 0.40 ± 0.15 1.60 ± 0.15 0.80 ± 0.05 1.60 ± 0.15 0.60 ± 0.15 0.30 ± 0.20 CAT16-J2 — (.016 ± .006) (.063 ± .006) (.032 ± .002) (.063 ± .006) (.024 ± .006) (.012 ± .008) 0.60 ± 0.15 1.60 ± 0.15 0.76 ± 0.10 1.60 ± 0.15 0.45 +0.15/-0.10 0.30 ± 0.20 CAY16-J2 — (.024 ± .006) (.063 ± .006) (.030 ± .004) (.063 ± .006) (.018 +0.006/-0.004) (.012 ± .008) 0.40 ± 0.15 6.40 ± 0.20 0.80 ± 0.15 1.60 ± 0.20 0.60 ± 0.15 0.30 ± 0.20 CAT16-F8, -J8 — (.016 ± .006) (.252 ± .008) (.032 ± .006) (.063 ± .008) (.024 ± .006) (.012 ± .008) 0.30 ± 0.15 0.30 ± 0.15 3.80 ± 0.20 0.50 ± 0.05 1.60 ± 0.20 0.50 ± 0.10 0.30 ± 0.15 CAY16-J8 (.012 ± .006) (.012 ± .006) (.15 ± .008) (.02 ± .002) (.063 ± .008) (.02 ± .004) (.012 ± .006) Configurations CAT16-F4, -J4 CAY16-F4, -J4 CAT16-J2 CAY16-J2 A A' A A A' CAT16-F4, -J4 CAY16-F4, -J4 CAT16-J2 CAY16-J2 A A' A A A' F F F F D F F F F D C C C C F DIMENSIONS: MM BC BC B C BC E F (INCHES) B B B B E CAT16-F8, -J8 CAY16-J8 A A' A CAT16-F8, -J8 CAY16-J8 A A' A F F D F F D C C F C B BC E F B B E Specifications are subject to change without notice. Users should verify actual device performance in their specific applications. The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.

CAT/CAY 16 Series - Chip Resistor Arrays Land Patterns CAT16-F4, -J4, -F8, -J8 CAY16-F4, -J4, -J8 CAT16-J2 CAY16-J2 p p Solder Solder Solder Solder resist resist resist resist f Land f Land f Land f Land Chip Chip Chip Chip resistor resistor resistor resistor array array array array a a a a b p b p b b Model a b p f 0.7 to 0.9 0.4 to 0.45 0.80 2.2 to 2.6 CAT16-F4, -J4, -F8, -J8 (.028 to .035) (.016 to .0178) (.032) (.087 to .102) 0.7 to 0.9 0.4 to 0.45 0.80 2.4 to 2.8 CAY16-F4, -J4 (.028 to .035) (.016 to .0178) (.032) (.094 to .11) 0.7 to 0.9 0.3 to 0.35 0.50 2.0 to 2.2 CAY16-J8 (.028 to .035) (.012 to .014) (.020) (.079 to .087) 0.7 to 0.9 0.4 to 0.45 0.80 2.2 to 2.6 CAT16-J2 (.028 to .035) (.016 to .0178) (.032) (.087 to .102) 0.7 to 0.9 0.4 to 0.5 0.80 2.0 to 2.6 CAY16-J2 (.028 to .035) (.016 to .020) (.032) (.079 to .102) Packaging Dimensions 1.0 MAX. 1.5 + 0.1 - 0 4.0 ± 0.1 2.0 ± 0.5 (.039) (.059 + .004 - 0) (.158 ± .004) (.079 ± .020) 13.0 ± 0.5 (.511 ± .020) b c 60 (2.362) a D IMENSIONS: (INMCHMES) (.028. 0+ +.0 00.41//--.00.028) (.145.70 ±± .00.014) 180 (.82217.0 ± ± . 003.81) de (7.087) Model a b c d e 3.60 ± 0.20 3.50 ± .005 8.0 ± 0.3 9.0 ± 0.3 11.4 ± 1.0 CAT16-F4, -J4 & CAY16-F4, J4 (.142 ± .008) (.138 ± .004) (.315 ± .012) (.354 ± .012) (.449 ± .040) MM DIMENSIONS: (INCHES) 1.80 ± 0.10 3.50 ± .005 8.0 ± 0.3 9.0 ± 0.3 11.4 ± 1.0 CAT16-J2 & CAY16-J2 (.070 ± .004) (.138 ± .004) (.315 ± .012) (.354 ± .012) (.449 ± .040) 6.90 ± 0.20 5.50 ± 0.10 12.0 ± 0.2 13.0 ± 0.2 15.4 ± 1.0 CAT16-F8, -J8 (.272 ± .008) (.217 ± .004) (.472 ± .008) (.512 ± .008) (.606 ± .040) 4.10 ± 0.15 3.50 ± 0.05 8.0 ± 0.3 9.0 ± 0.3 11.4 ± 1.0 CAY16-J8 (.161 ± .012) (.138 ± .002) (.315 ± .012) (.354 ± .012) (.449 ± .040) • 5,000 pcs. per reel (J2, J4, CAY16-J8) 4,000 pcs. per reel (CAT16-F8, -J8) • Paper tape REV. 05/19 Specifications are subject to change without notice. Users should verify actual device performance in their specific applications. The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.

Chip Resistor Arrays - Application Note Component Placement a. Reduce the mechanical stress to a minimum during and after placing of the unit in order not to damage the terminals and protective coating. b. Misplacement of components may cause solder bridges. Soldering a. Reflow soldering: Recommendation is shown in the following chart. b. Wave soldering: Recommendation according to IEC standards. c. Hand soldering: Don’t touch the protective coating of the part. Solder within 3 seconds when the temperature is over 280 ºC. C) Preheating Soldering Gradual Cooling ° e ( 250 ur 200 at 150 r e p 100 m 50 e T 0 60 sec. min. 10-30 sec. 120 sec. min. Specifications are subject to change without notice. Users should verify actual device performance in their specific applications. The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.

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