5 V, Slew Rate Limited, Half-Duplex and Full Duplex RS-485/RS-422 Transceivers Data Sheet ADM4850 to ADM4857 FEATURES FUNCTIONAL BLOCK DIAGRAMS Electronics industries alliance (EIA) RS-485/RS-422 compliant VCC Data rate options ADM4850/ADM4851/ ADM4850/ADM4854: 115 kbps ADM4852/ADM4853 ADM4851/ADM4855: 500 kbps RO R ADM4852/ADM4856: 2.5 Mbps A ADM4853/ADM4857: 10 Mbps RE Half-duplex and full duplex options DE B Reduced slew rates for low electromagnetic interference (EMI) True fail-safe receiver inputs DI D 5U pµ Ato ( m25a6x itmraunmsc)e siuveprpsl yo ncu ornreen btu ins shutdown mode GND 04931-001 Outputs high-Z when disabled or powered off Figure 1. ADM4850/ADM4851/ADM4852/ADM4853 Functional Block Diagram −7 V to +12 V bus common-mode range VCC Thermal shutdown and short-circuit protection ADM4854/ADM4855/ ADM4856/ADM4857 Pin-compatible with the MAX308x Specified over the −40°C to +85°C temperature range A Available in 8-lead SOIC, 8-lead LFCSP, and 8-lead MSOP RO R B Qualified for automotive applications APPLICATIONS Z DI D Y Low power RS-485 applications EDMTEI steon DsCitEiv ien tseyrsftaecmess GND 04931-028 Figure 2. ADM4854/ADM4855/ADM4856/ADM4857 Functional Block Diagram Industrial control Packet switching This guarantees that the receiver outputs are in a known state Local area networks before communication begins and when communication ends. Level translators The driver outputs are slew rate limited to reduce EMI and data errors caused by reflections from improperly terminated buses. GENERAL DESCRIPTION Excessive power dissipation caused by bus contention or by The ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ output shorting is prevented with a thermal shutdown circuit. ADM4855/ADM4856/ADM4857 are differential line transceivers The devices are fully specified over the commercial and industrial suitable for high speed, half-duplex and full duplex data temperature ranges and are available in 8-lead SOIC (ADM4850 communication on multipoint bus transmission lines. They through ADM4857), 8-lead LFCSP (ADM4850/ADM4852/ are designed for balanced data transmission and comply with ADM4853), and 8-lead MSOP (ADM4850 only) packages. EIA Standards RS-485 and RS-422. The ADM4850/ADM4851/ Table 1. Selection Table ADM4852/ADM4853 are half-duplex transceivers that share Device No. Half-Duplex/Full Duplex Data Rate differential lines and have separate enable inputs for the driver ADM4850 Half 115 kbps and receiver. The full duplex ADM4854/ADM4855/ADM4856/ ADM4851 Half 500 kbps ADM4857 transceivers have dedicated differential line driver ADM4852 Half 2.5 Mbps outputs and receiver inputs. ADM4853 Half 10 Mbps The devices have a 1/8-unit load receiver input impedance, ADM4854 Full 115 kbps which allows up to 256 transceivers on one bus. Because only one ADM4855 Full 500 kbps driver must be enabled at any time, the output of a disabled or ADM4856 Full 2.5 Mbps powered down driver is three-stated to avoid overloading the bus. ADM4857 Full 10 Mbps The receiver inputs have a true fail-safe feature, which ensures a logic high output level when the inputs are open or shorted. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2004–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADM4850 to ADM4857 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Test Circuits ..................................................................................... 11 Applications ....................................................................................... 1 Switching Characteristics .............................................................. 12 General Description ......................................................................... 1 Theory of Operation ...................................................................... 13 Functional Block Diagrams ............................................................. 1 Slew Rate Control ....................................................................... 13 Revision History ............................................................................... 2 Receiver Input Filtering ............................................................. 13 Specifications ..................................................................................... 3 Half-Duplex/Full Duplex Operation ....................................... 13 ADM4850/ADM4854 Timing Specifications ........................... 4 High Receiver Input Impedance .............................................. 14 ADM4851/ADM4855 Timing Specifications ........................... 4 Three-State Bus Connection ..................................................... 14 ADM4852/ADM4856 Timing Specifications ........................... 5 Shutdown Mode ......................................................................... 14 ADM4853/ADM4857 Timing Specifications ........................... 5 Fail-Safe Operation .................................................................... 14 Absolute Maximum Ratings ............................................................ 6 Current Limit and Thermal Shutdown ................................... 14 ESD Caution .................................................................................. 6 Outline Dimensions ....................................................................... 15 Pin Configurations and Function Descriptions ........................... 7 Ordering Guide .......................................................................... 16 Typical Performance Characteristics ............................................. 9 Automotive Product ................................................................... 16 REVISION HISTORY 5/16—Rev. E to Rev. F 1/12—Rev. C to Rev. D Changes to Figure 1 .......................................................................... 1 Change to Features Section .............................................................. 1 Reformatted and Changes to Pin Configuration and Function Changes to Ordering Guide .......................................................... 15 Descriptions Section ........................................................................ 7 Added Automotive Products Section .......................................... 15 Added Figure 6, Renumbered Sequentially .................................. 8 1/11—Rev. B to Rev. C Change to Table 8, Pin 3 Description ............................................. 7 2/16—Rev. D to Rev. E Changes to Figure 29...................................................................... 12 Changes to Figure 1 and General Description Section ............... 1 Changes to Ordering Guide .......................................................... 15 Changes to Table 2 ............................................................................ 3 Changes to Table 3 and Table 4 ....................................................... 4 7/09—Rev. A to Rev. B Changes to Table 5 and Table 6 ....................................................... 5 Added MSOP Package ....................................................... Universal Changes to Figure 3, Figure 4, and Table 8 Caption .................... 7 Changes to Table 2 ............................................................................. 3 Added Table 9; Renumbered Sequentially .................................... 7 Changes to Table 7 ............................................................................. 6 Changes to Figure 5 and Table 10 Caption ................................... 8 Inserted Figure 4; Renumbered Sequentially ................................ 7 Changes to Figure 6 Caption ........................................................... 9 Moved Typical Performance Characteristics Section ................... 8 Changes to Figure 14 Caption and Figure 15 Caption .............. 10 Changes to Figure 24 and Figure 27 ............................................ 11 Changes to Figure 21 Caption and Figure 23 Caption .............. 11 Changes to Figure 29...................................................................... 12 Changed Circuit Description Section to Theory of Operation Change to Shutdown Mode Section............................................. 13 Section .............................................................................................. 13 Updated Outline Dimensions ....................................................... 14 Changes to Figure 28 ...................................................................... 13 Changes to Ordering Guide .......................................................... 15 Changes to the Three-State Bus Connection Section and the Shutdown Mode Section ................................................................ 14 4/09—Rev. 0 to Rev. A Updated Outline Dimensions ....................................................... 15 Changes to Ordering Guide .......................................................... 15 Changes to Ordering Guide .......................................................... 16 10/04—Revision 0: Initial Version Rev. F | Page 2 of 16

Data Sheet ADM4850 to ADM4857 SPECIFICATIONS V = 5 V ± 5%, T = T to T , unless otherwise noted. CC A MIN MAX Table 2. Parameter Min Typ Max Unit Test Conditions/Comments DRIVER Differential Output Voltage V V V R = ∞, see Figure 191 OD CC 2.0 5 V R = 50 Ω (RS-422), see Figure 19 1.5 5 V R = 27 Ω (RS-485), see Figure 19 Differential Output Voltage over Common- |V | 1.5 5 V V = −7 V to +12 V, see Figure 20 OD3 TST Mode Range Δ|V | for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, see Figure 19 OD Common-Mode Output Voltage V 3 V R = 27 Ω or 50 Ω, see Figure 19 OC Δ|V | for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, see Figure 19 OC Output Short-Circuit Current −7 V < V < +12 V OUT V = High −200 +200 mA OUT V = Low −200 +200 mA OUT DRIVER INPUT LOGIC CMOS Input Logic Threshold Low 0.8 V High 2.0 V CMOS Logic Input Current (DI) ±1 µA DE Input Resistance to GND 220 kΩ RECEIVER Differential Input Threshold Voltage V −200 −125 −30 mV −7 V < V < +12 V TH OC Input Hysteresis 20 mV −7 V < V < +12 V OC Input Resistance (A, B) 96 150 kΩ −7 V < V < +12 V OC Input Current (A, B) 0.125 mA V = 12 V IN −0.1 mA V = −7 V IN CMOS Logic Input Current (RE) ±1 µA CMOS Output Voltage Low 0.4 V I = 4 mA OUT High 4.0 V I = −4 mA OUT Output Short-Circuit Current 7 85 mA V = GND or V OUT CC Three-State Output Leakage Current ±2 µA 0.4 V ≤ V ≤ 2.4 V OUT POWER SUPPLY CURRENT 115 kbps Options (ADM4850/ADM4854) 5 µA DE = 0 V, RE = V (shutdown) CC 36 60 µA DE = 0 V, RE = 0 V 100 160 µA DE = V CC 500 kbps Options (ADM4855) 5 µA DE = 0 V, RE = V (shutdown) CC 80 120 µA DE = 0 V, RE = 0 V 120 200 µA DE = V CC 2.5 Mbps Options (ADM4852/ADM4856) 5 µA DE = 0 V, RE = V (shutdown) CC 250 400 µA DE = 0 V, RE = 0 V 320 500 µA DE = V CC 10 Mbps Options (ADM4853/ADM4857) 5 µA DE = 0 V, RE = V (shutdown) CC 250 400 µA DE = 0 V, RE = 0 V 320 500 µA DE = V CC 1 Guaranteed by design. Rev. F | Page 3 of 16

ADM4850 to ADM4857 Data Sheet ADM4850/ADM4854 TIMING SPECIFICATIONS V = 5 V ± 5%, T = T to T , unless otherwise noted. CC A MIN MAX Table 3. Parameter Symbol Min Typ Max Unit Test Conditions/Comments DRIVER Maximum Data Rate 115 kbps Propagation Delay t , t 600 2500 ns R = 54 Ω, C = C = 100 pF, see Figure 21 and Figure 25 PLH PHL LDIFF L1 L2 Skew t 70 ns R = 54 Ω, C = C = 100 pF, see Figure 21 and Figure 25 SKEW LDIFF L1 L2 Rise/Fall Times t , t 600 2400 ns R = 54 Ω, C = C = 100 pF, see Figure 21 and Figure 25 R F LDIFF L1 L2 Enable Time t , t 2000 ns R = 500 Ω, C = 100 pF, see Figure 22 and Figure 27 (ADM4850 only) ZH ZL L L Disable Time t , t 2000 ns R = 500 Ω, C = 15 pF, see Figure 22 and Figure 27 (ADM4850 only) LZ HZ L L Enable Time from Shutdown 4000 ns R = 500 Ω, C = 100 pF, see Figure 22 (ADM4850 only) L L RECEIVER Propagation Delay t , t 400 1000 ns C = 15 pF, see Figure 23 and Figure 26 PLH PHL L Differential Skew t 255 ns C = 15 pF, see Figure 23 and Figure 26 SKEW L Enable Time t , t 5 50 ns R = 1 kΩ, C = 15 pF, see Figure 24 and Figure 28 (ADM4850 only) ZH ZL L L Disable Time t , t 20 50 ns R = 1 kΩ, C = 15 pF, see Figure 24 and Figure 28 (ADM4850 only) LZ HZ L L Enable Time from Shutdown 4000 ns R = 1 kΩ, C = 15 pF, see Figure 24 (ADM4850 only) L L Time to Shutdown 50 330 3000 ns ADM4850 only1 1 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode. ADM4851/ADM4855 TIMING SPECIFICATIONS V = 5 V ± 5%, T = T to T , unless otherwise noted. CC A MIN MAX Table 4. Parameter Symbol Min Typ Max Unit Test Conditions/Comments DRIVER Maximum Data Rate 500 kbps Propagation Delay t , t 250 600 ns R = 54 Ω, C = C = 100 pF, see Figure 21 and Figure 25 PLH PHL LDIFF L1 L2 Skew t 40 ns R = 54 Ω, C = C = 100 pF, see Figure 21 and Figure 25 SKEW LDIFF L1 L2 Rise/Fall Times t , t 200 600 ns R = 54 Ω, C = C = 100 pF, see Figure 21 and Figure 25 R F LDIFF L1 L2 Enable Time t , t 1000 ns R = 500 Ω, C = 100 pF, see Figure 22 and Figure 27 (ADM4851 only) ZH ZL L L Disable Time t , t 1000 ns R = 500 Ω, C = 100 pF, see Figure 22 and Figure 27 (ADM4851 only) LZ HZ L L Enable Time from Shutdown 4000 ns R = 500 Ω, C = 100 pF, see Figure 22 (ADM4851 only) L L RECEIVER Propagation Delay t , t 400 1000 ns C = 15 pF, see Figure 23 and Figure 26 PLH PHL L Differential Skew t 250 ns C = 15 pF, see Figure 23 and Figure 26 SKEW L Enable Time t , t 5 50 ns R = 1 kΩ, C = 15 pF, see Figure 24 and Figure 28 (ADM4851 only) ZH ZL L L Disable Time t , t 20 50 ns R = 1 kΩ, C = 15 pF, see Figure 24 and Figure 28 (ADM4851 only) LZ HZ L L Enable Time from Shutdown 4000 ns R = 1 kΩ, C = 15 pF, see Figure 24 (ADM4851 only) L L Time to Shutdown 50 330 3000 ns ADM4851 only1 1 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode. Rev. F | Page 4 of 16

Data Sheet ADM4850 to ADM4857 ADM4852/ADM4856 TIMING SPECIFICATIONS V = 5 V ± 5%, T = T to T , unless otherwise noted. CC A MIN MAX Table 5. Parameter Symbol Min Typ Max Unit Test Conditions/Comments DRIVER Maximum Data Rate 2.5 Mbps Propagation Delay t , t 50 180 ns R = 54 Ω, C = C = 100 pF, see Figure 21 and Figure 25 PLH PHL LDIFF L1 L2 Skew t 50 ns R = 54 Ω, C = C = 100 pF, see Figure 21 and Figure 25 SKEW LDIFF L1 L2 Rise/Fall Times t , t 140 ns R = 54 Ω, C = C = 100 pF, see Figure 21 and Figure 25 R F LDIFF L1 L2 Enable Time t , t 180 ns R = 500 Ω, C = 100 pF, see Figure 22 and Figure 27 (ADM4852 ZH ZL L L only) Disable Time t , t 180 ns R = 500 Ω, C = 100 pF, see Figure 22 and Figure 27 (ADM4852 LZ HZ L L only) Enable Time from Shutdown 4000 ns R = 500 Ω, C = 100 pF, see Figure 22 (ADM4852 only) L L RECEIVER Propagation Delay t , t 55 190 ns C = 15 pF, see Figure 23 and Figure 26 PLH PHL L Differential Skew t 50 ns C = 15 pF, see Figure 23 and Figure 26 SKEW L Enable Time t , t 5 50 ns R = 1 kΩ, C = 15 pF, see Figure 24 and Figure 28 (ADM4852 only) ZH ZL L L Disable Time t , t 20 50 ns R = 1 kΩ, C = 15 pF, see Figure 24 and Figure 28 (ADM4852 only) LZ HZ L L Enable Time from Shutdown 4000 ns R = 1 kΩ, C = 15 pF, see Figure 24 (ADM4852 only) L L Time to Shutdown 50 330 3000 ns ADM4852 only1 1 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode. ADM4853/ADM4857 TIMING SPECIFICATIONS V = 5 V ± 5%, T = T to T , unless otherwise noted. CC A MIN MAX Table 6. Parameter Symbol Min Typ Max Unit Test Conditions/Comments DRIVER Maximum Data Rate 10 Mbps Propagation Delay t , t 0 30 ns R = 54 Ω, C = C = 100 pF, see Figure 21 and Figure 25 PLH PHL LDIFF L1 L2 Skew t 10 ns R = 54 Ω, C = C = 100 pF, see Figure 21 and Figure 25 SKEW LDIFF L1 L2 Rise/Fall Times t , t 30 ns R = 54 Ω, C = C = 100 pF, see Figure 21 and Figure 25 R F LDIFF L1 L2 Enable Time t , t 35 ns R = 500 Ω, C = 100 pF, see Figure 22 and Figure 27 (ADM4853 only) ZH ZL L L Disable Time t , t 35 ns R = 500 Ω, C = 100 pF, see Figure 22 and Figure 27 (ADM4853 only) LZ HZ L L Enable Time from Shutdown 4000 ns R = 500 Ω, C = 100 pF, see Figure 22 (ADM4853 only) L L RECEIVER Propagation Delay t , t 55 190 ns C = 15 pF, see Figure 23 and Figure 26 PLH PHL L Differential Skew t 30 ns C = 15 pF, see Figure 23 and Figure 26 SKEW L Enable Time t , t 5 50 ns R = 1 kΩ, C = 15 pF, see Figure 24 and Figure 28 (ADM4853 only) ZH ZL L L Disable Time t , t 20 50 ns R = 1 kΩ, C = 15 pF, see Figure 24 and Figure 28 (ADM4853 only) LZ HZ L L Enable Time from Shutdown 4000 ns R = 1 kΩ, C = 15 pF, see Figure 24 (ADM4853 only) L L Time to Shutdown 50 330 3000 ns ADM4853 only1 1 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode. Rev. F | Page 5 of 16

ADM4850 to ADM4857 Data Sheet ABSOLUTE MAXIMUM RATINGS Stresses at or above those listed under Absolute Maximum Table 7. Ratings may cause permanent damage to the product. This is a Parameter Rating stress rating only; functional operation of the product at these V to GND 6 V CC or any other conditions above those indicated in the operational Digital Input/Output Voltage (DE, RE, DI, RO) −0.3 V to V + 0.3 V CC section of this specification is not implied. Operation beyond Driver Output/Receiver Input Voltage −9 V to +14 V the maximum operating conditions for extended periods may Operating Temperature Range −40°C to +85°C affect product reliability. Storage Temperature Range −65°C to +125°C θ Thermal Impedance JA ESD CAUTION 8-Lead SOIC 110°C/W 8-Lead LFCSP 62°C/W 8-Lead MSOP 133.1°C/W Lead Temperature Soldering (10 sec) 300°C Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C Rev. F | Page 6 of 16

Data Sheet ADM4850 to ADM4857 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ADM4850/ RO 1 8 VCC ADM4851/ RE 2 ADM4850 7 B ADM4852/ TOP VIEW ADM4853 DE 3 (Not to Scale) 6 A DI 4 5 GND 04931-002 RROE 21 TOP VIEW 78 VBCC DE 3 (Not to Scale) 6 A DI 4 5 GND 04931-104 Figure 3. ADM4850, 8-Lead MSOP, Pin Configuration Figure 4. ADM4850/ADM4851/ADM4852/ADM4853, 8-Lead SOIC, Pin Configuration Table 8. ADM4850/ADM4851/ADM4852/ADM4853, 8-Lead MSOP and 8-Lead SOIC, Pin Function Descriptions Pin No. Mnemonic Description 1 RO Receiver Output. When RO is enabled and (A − B) ≥ −30 mV, RO is high. When RO is enabled and (A − B) ≤ −200 mV, RO is low. 2 RE Receiver Output Enable. A low level on RE enables the receiver output (RO). A high level on RE places RO into a high impedance state. 3 DE Driver Output Enable. A high level on DE enables the driver differential outputs (A and B). A low level on DE places the driver differential outputs into a high impedance state. 4 DI Driver Input. When the driver is enabled, a logic low on DI forces A low and B high, whereas a logic high on DI forces A high and B low. 5 GND Ground. 6 A Noninverting Receiver Input A/Noninverting Driver Output A. 7 B Inverting Receiver Input B/Inverting Driver Output B. 8 V 5 V Power Supply. CC Rev. F | Page 7 of 16

ADM4850 to ADM4857 Data Sheet ADM4850/ADM4852/ADM4853 RO 1 8 VCC RE 2 TOPVIEW 7 B DE 3 (NottoScale) 6 A DI 4 5 GND NOTES 1.THEEXPOSEDPADDLE ONTHEUNDERSIDE OFTHEPACKAGESHOULDBESOLDERED TOTHE GROUNDPLANETO INCREASETHE TTRHOEELMIPAAABXCIILMKITIAZYGE OET.FHTEHTEHSEORMLDAELRCJAOPIANBTISLIATNYD OF 04931-029 Figure 5. ADM4850/ADM4852/ADM4853, 8-Lead LFCSP, Pin Configuration Table 9. ADM4850/ADM4852/ADM4853, 8-Lead LFCSP, Pin Function Descriptions Pin No. Mnemonic Description 1 RO Receiver Output. When RO is enabled and (A − B) ≥ −30 mV, RO is high. When RO is enabled and (A − B) ≤ −200 mV, RO is low. 2 RE Receiver Output Enable. A low level on RE enables the receiver output (RO). A high level on RE places RO into a high impedance state. 3 DE Driver Output Enable. A high level on DE enables the driver differential outputs (A and B). A low level places the driver differential outputs into a high impedance state. 4 DI Driver Input. When the driver is enabled, a logic low on DI forces A low and B high, whereas a logic high on DI forces A high and B low. 5 GND Ground. 6 A Noninverting Receiver Input A/Noninverting Driver Output A. 7 B Inverting Receiver Input B/Inverting Driver Output B. 8 V 5 V Power Supply. CC EPAD Exposed Pad. The exposed paddle on the underside of the package must be soldered to the ground plane to increase the reliability of the solder joints and to maximize the thermal capability of the package. ADM4854/ ADM4855/ ADM4856/ ADM4857 VCC 1 8 A RO 2 TOP VIEW 7 B GNDDI 43 (Not to Scale) 56 YZ 04931-106 Figure 6. ADM4854/ADM4855/ADM4856/ADM4857, 8-Lead SOIC, Pin Configuration Table 10. ADM4854/ADM4855/ADM4856/ADM4857, 8-Lead SOIC, Pin Function Descriptions Pin No. Mnemonic Description 1 V 5 V Power Supply. CC 2 RO Receiver Output. When RO is enabled and (A − B) ≥ −30 mV, RO is high. When RO is enabled and (A − B) ≤ −200 mV, RO is low. 3 DI Driver Input. When the driver is enabled, a logic low on DI forces Y low and Z high, whereas a logic high on DI forces Y high and Z low. 4 GND Ground. 5 Y Noninverting Driver Output. 6 Z Inverting Driver Output. 7 B Inverting Receiver Input. 8 A Noninverting Receiver Input. Rev. F | Page 8 of 16

Data Sheet ADM4850 to ADM4857 TYPICAL PERFORMANCE CHARACTERISTICS 400 0.40 ADM4853: DE = VCC 350 A) μ 0.35 T (300 V) REN ADM4853: DE = GND GE ( R250 A CU LT0.30 PLY 200 W VO OADED SUP110500 ADM4850: DE = VCC OUTPUT LO0.25 NL ADM4850: DE = GND 0.20 U 500 04931-014 0.15 04931-017 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 7. Unloaded Supply Current vs. Temperature (ADM4850/ADM4853) Figure 10. Receiver Output Low Voltage vs. Temperature 50 4.6 45 A) 4.5 m 40 NT ( 35 E (V) CURRE 30 OLTAG 4.4 UTPUT 2205 HIGH V 4.3 R O UT 4.2 E 15 P CEIV 10 OUT RE 4.1 05 04931-015 4.0 04931-018 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 –50 –25 0 25 50 75 100 125 RECEIVER OUTPUT LOW VOLTAGE (V) TEMPERATURE (°C) Figure 8. Receiver Output Current vs. Receiver Output Low Voltage Figure 11. Receiver Output High Voltage vs. Temperature 90 5 80 A) T CURRENT (m –50 CURRENT (mA) 567000 UTPU PUT 40 RECEIVER O––1105 DRIVER OUT 2300 –20 04931-016 100 04931-019 3.5 4.0 4.5 5.0 5.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 RECEIVER OUTPUT HIGH VOLTAGE (V) DIFFERENTIAL OUTPUT VOLTAGE (V) Figure 9. Receiver Output Current vs. Receiver Output High Voltage Figure 12. Driver Output Current vs. Differential Output Voltage Rev. F | Page 9 of 16

ADM4850 to ADM4857 Data Sheet 120 800 700 100 ADM4855 s) 600 mA) 80 Y (n T( LA 500 N E E D CURR 60 TION 400 UT GA 300 TP 40 PA U O O PR 200 ADM4853 20 0 04931-020 1000 04931-023 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 –50 –25 0 25 50 75 100 125 OUTPUT VOLTAGE (V) TEMPERATURE (°C) Figure 13. Output Current vs. Driver Output Low Voltage Figure 16. Receiver Propagation Delay vs. Temperature (ADM4853/ADM4855) –10 A) –30 3 m T ( N RE –50 R U C T PU –70 T U O –90 2 –110 04931-021 4 04931-024 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 CH1 1.00VΩBW CH2 1.00VΩBW M 400ns CH3 2.00V OUTPUT VOLTAGE (V) CH3 2.00VΩBW CH4 5.00VΩ Figure 14. Output Current vs. Driver Output High Voltage Figure 17. Driver/Receiver Propagation Delay (ADM4855, 500 kbps) 450 400 s) 350 1 n ADM4855 AY ( 300 L E D 250 N O TI 200 A G A P 150 O R P 100 2 500 ADM4853 04931-022 4 04931-025 –50 –25 0 25 50 75 100 125 CH1 2.00VΩBW CH2 1.00VΩ M 50.0ns CH1 480mV TEMPERATURE (°C) CH3 1.00VΩBW CH4 5.00VΩ Figure 15. Driver Propagation Delay vs. Temperature (ADM4853/ADM4855) Figure 18. Driver/Receiver Propagation Delay (ADM4857, 4 Mbps) Rev. F | Page 10 of 16

Data Sheet ADM4850 to ADM4857 TEST CIRCUITS VCC R A VOD 0V OR 3V S1 RL S2 R VOC 04931-004 DE IN DE B CL VOUT 04931-007 Figure 19. Driver Voltage Measurement Figure 22. Driver Enable/Disable (ADM4850/ADM4852/ADM4853) 375Ω A VOD3 6307Ω5Ω VTST 04931-005 B RE CL VOUT 04931-008 Figure 20. Driver Voltage Measurement over Common-Mode Voltage Range Figure 23. Receiver Propagation Delay +1.5V A CL1 VCC S1 RLDIFF RL B CL2 04931-006 –R1E.5 IVN RE CL VOUT S2 04931-009 Figure 21. Driver Propagation Delay Figure 24. Receiver Enable/Disable (ADM4850/ADM4852/ADM4853) Rev. F | Page 11 of 16

ADM4850 to ADM4857 Data Sheet SWITCHING CHARACTERISTICS 3V 3V 1.5V 1.5V DE 1.5V 1.5V 0V 0V tPLH tPHL tZL tLZ B 1/2VOD VOD A, B 2.3V VOL + 0.5V A VOL tSKEW=|tPLH–tPHL| tZH tHZ 5V 90%POINT 90%POINT VOH 0V 10%POINT tR tF 10%POINT 04931-010 A, B 2.3V VOH – 0.5V 0V 04931-012 Figure 25. Driver Propagation Delay, Rise/Fall Timing Figure 27. Driver Enable/Disable Timing 3V RE 1.5V 1.5V A,B 0V 0V 0V tZL tLZ tPLH tPHL VOH RO 1.5VOUTPUTLOW VOL + 0.5V RO 1.5V tSKEW=|tPLH–tPHL| 1.5V VOL 04931-011 R0OV tZH 1.5VOUTPUTHIGH tHZ VOH – 0.5V VVOOLH 04931-013 Figure 26. Receiver Propagation Delay Figure 28. Receiver Enable/Disable Timing Rev. F | Page 12 of 16

Data Sheet ADM4850 to ADM4857 THEORY OF OPERATION The ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ RECEIVER INPUT FILTERING ADM4855/ADM4856/ADM4857 are high speed RS-485/RS-422 The receivers of all the devices incorporate input hysteresis. In transceivers offering enhanced performance over industry- addition, the receivers of the 115 kbps ADM4850 and ADM4854 standard devices. All devices in the family contain one driver and the 500 kbps ADM4851 and ADM4855 incorporate input and one receiver but offer a choice of performance options. The filtering, which enhances noise immunity with differential devices feature true fail-safe operation, which guarantees a logic signals that have very slow rise and fall times. However, it high receiver output when the receiver inputs are open circuit causes the propagation delay to increase by 20%. or short-circuit, or when they are connected to a terminated HALF-DUPLEX/FULL DUPLEX OPERATION transmission line with all drivers disabled (see the Fail-Safe Operation section). Half-duplex operation implies that the transceiver can transmit and SLEW RATE CONTROL receive, but it can do only one of these at any given time. However, with full duplex operation, the transceiver can transmit and The ADM4850 and ADM4854 feature a controlled slew rate receive simultaneously. The ADM4850/ADM4851/ADM4852/ driver that minimizes EMI and reduces reflections caused by ADM4853 are half-duplex devices in which the driver and the incorrectly terminated cables, allowing error free data transmission receiver share differential bus terminals. The ADM4854/ rates up to 115 kbps. The ADM4851 and ADM4855 offer a higher ADM4855/ADM4856/ADM4857 are full duplex devices that limit on driver output slew rate, allowing data transmission have dedicated driver output and receiver input pins. Figure 29 rates up to 500 kbps. The driver slew rates of the ADM4852/ and Figure 30 show typical half-duplex and full duplex topologies. ADM4856 and the ADM4853/ADM4857 are not limited, offering data transmission rates up to 2.5 Mbps and 10 Mbps, respectively. ADM4850 ADM4850/ ADM4852/ADM4853 ADM4852/ADM4853 RO R A A R RO RE RE DE DE DI D B B D DI A B A B 3 3 5 5 8 8 4 4 0/M 0/M 5D 5D 8A 8A DM4852/ R D DM4852/ R D A4 A4 M M D D A A RO RE DE DI RO RE DE DI MAXIMUM NUMBER OF TRANSCEIVERS ON BUS: 256 N1.O TTHEES ADM4851 IS A HALF-DUPLEX RS-485 TRANSCEIVER, BUT IT DOES NOT HAVE THE DRIVER ENABLE (DE) AND THE RECEIVER ENABLE (RE) PINS. 04931-026 Figure 29. Typical Half-Duplex RS-485 Network Topology VCC VCC ADM4854/ADM4855/ ADM4854/ADM4855/ ADM4856/ADM4857 ADM4856/ADM4857 A Y RO R D DI B Z Z B DI D R RO GND Y A GND 04931-027 Figure 30. Typical Full Duplex Point-to-Point RS-485 Network Topology Rev. F | Page 13 of 16

ADM4850 to ADM4857 Data Sheet HIGH RECEIVER INPUT IMPEDANCE FAIL-SAFE OPERATION The input impedance of the ADM4850/ADM4851/ADM4852/ The ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ ADM4853/ADM4854/ADM4855/ADM4856/ADM4857 receivers ADM4855/ADM4856/ADM4857 offer true fail-safe operation is 96 kΩ, which is eight times higher than the standard RS-485 unit while remaining fully compliant with the ±200 mV EIA/TIA-485 load of 12 kΩ. This 96 kΩ impedance enables a standard driver standard. A logic high receiver output generates when the to drive 32 unit loads or to be connected to 256 ADM4850/ receiver inputs are shorted together or open circuit, or when ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ they are connected to a terminated transmission line with all ADM4856/ADM4857 receivers. An RS-485 bus, driven by a drivers disabled. This logic high is done by setting the receiver single standard driver, can be connected to a combination of threshold between −30 mV and −200 mV. If the differential ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ receiver input voltage (A − B) is greater than or equal to ADM4855/ADM4856/ADM4857 devices and standard unit −30 mV, RO is logic high. If (A − B) is less than or equal to load receivers, up to an equivalent of 32 standard unit loads. −200 mV, RO is logic low. In the case of a terminated bus THREE-STATE BUS CONNECTION with all transmitters disabled, the differential input voltage of the receiver is pulled to 0 V by the internal circuitry of The half-duplex devices (ADM4850/ADM4852/ADM4853) the ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ have a driver enable pin (DE) that enables the driver outputs ADM4855/ADM4856/ADM4857, which results in a logic high when taken high, or puts the driver outputs into a high with 30 mV minimum noise margin. impedance state when taken low. Similarly, the half-duplex devices CURRENT LIMIT AND THERMAL SHUTDOWN have an active low receiver enable pin (RE). Taking this pin low enables the receiver, whereas taking it high puts the receiver The ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ outputs into a high impedance state, which allows several driver ADM4855/ADM4856/ADM4857 incorporate two protection outputs to be connected to an RS-485 bus. Note that only one mechanisms to guard the drivers against short circuits, bus driver must be enabled at a time, but that many receivers can be contention, or other fault conditions. The first is a current limiting enabled. output stage, which protects the driver against short circuits over the entire common-mode voltage range by limiting the SHUTDOWN MODE output current to approximately 70 mA. Under extreme fault The ADM4850/ADM4852/ADM4853 have a low power conditions where the current limit is not effective, a thermal shutdown mode, which is enabled by taking RE high and DE shutdown circuit puts the driver outputs into a high impedance low. If shutdown mode is not used, the fact that DE is active state if the die temperature exceeds 150°C, and does not turn high and RE is active low offers a convenient way of switching the them back on until the temperature falls to 130°C. device between transmit and receive by tying DE and RE together. If DE is driven low and RE is driven high for less than 50 ns, the devices are guaranteed not to enter shutdown mode. If DE is driven low and RE is driven high for at least 3000 ns, the devices are guaranteed to enter shutdown mode. Rev. F | Page 14 of 16

Data Sheet ADM4850 to ADM4857 OUTLINE DIMENSIONS 5.00(0.1968) 3.20 4.80(0.1890) 3.00 2.80 8 5 4.00(0.1574) 6.20(0.2441) 3.80(0.1497) 1 4 5.80(0.2284) 3.20 8 5 54..1950 3.00 4.65 2.80 1 4 1.27(0.0500) 0.50(0.0196) BSC 1.75(0.0688) 0.25(0.0099) 45° PIN 1 0.25(0.0098) 1.35(0.0532) 8° IDENTIFIER 0.10(0.0040) 0° 0.65 BSC COPLANARITY 0.51(0.0201) 0.10 SEATING 0.31(0.0122) 0.25(0.0098) 10..2470((00..00510507)) 00..9855 1.10 MAX 15° MAX PLANE 0.17(0.0067) 0.75 0.80 COMPLIANTTOJEDECSTANDARDSMS-012-AA 0.15 0.40 6° 0.23 0.55 C(RINOEFNPEATRRREOENNLCLTEIHNEOGSNDELISYM)AEANNRDSEIAORRNOESUNANORDETEDAIN-POMPFRIFLOLMPIMIRLELIATIMTEEERTFSEO;RIRNECUQHSUEDIVIINMAELDENENSSTIIOGSNNFS.OR 012407-A CO0P.0L50A.1N0ARICTOYMPLIANT0. 2T5O JEDEC STA0°NDARDS 0M.0O9-187-AA 0.40 10-07-2009-B Figure 31. 8-Lead Standard Small Outline Package [SOIC_N] Figure 32. 8-Lead Mini Small Outline Package [MSOP] Narrow Body (RM-8) (R-8) Dimensions shown in millimeters Dimensions shown in millimeters and (inches) 1.84 3.10 1.74 3.00SQ 2.90 1.64 0.50BSC 5 8 PIN1INDEX EXPOSED 1.55 AREA PAD 1.45 0.50 1.35 0.40 0.30 4 1 PIN1 TOPVIEW BOTTOMVIEW INDICATOR (R0.15) 0.80 FORPROPERCONNECTIONOF 0.75 0.05MAX THEEXPOSEDPAD,REFERTO THEPINCONFIGURATIONAND 0.70 0.02NOM FUNCTIONDESCRIPTIONS COPLANARITY SECTIONOFTHISDATASHEET. SEATING 0.30 0.08 PLANE 0.25 0.203REF 0.C2O0MPLIANTTOJEDECSTANDARDSMO-229-WEED 12-07-2010-A Figure 33. 8-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.75 mm Package Height (CP-8-13) Dimensions shown in millimeters Rev. F | Page 15 of 16

ADM4850 to ADM4857 Data Sheet ORDERING GUIDE Model1, 2 Temperature Range Package Description Package Option Branding ADM4850ACPZ-REEL7 −40°C to +85°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-13 M8Q ADM4850ARZ −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADM4850ARZ-REEL7 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADM4850ARMZ −40°C to +85°C 8-Lead Mini Small Outline Package [MSOP] RM-8 M8Q ADM4850ARMZ-REEL7 −40°C to +85°C 8-Lead Mini Small Outline Package [MSOP] RM-8 M8Q ADM4851ARZ −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADM4851ARZ-REEL7 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADM4852ACPZ-REEL7 −40°C to +85°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-13 M9M ADM4852ARZ −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADM4852ARZ-REEL7 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADM4853ACPZ-REEL7 −40°C to +85°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-13 F0B ADM4853ARZ −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADM4853ARZ-REEL7 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADM4853WARZ-RL7 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADM4854ARZ −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADM4855ARZ −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADM4856ARZ −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADM4856ARZ-REEL7 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADM4857ARZ −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADM4857ARZ-REEL7 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 1 Z = RoHS Compliant Part. 2 W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCT The ADM4853WARZ-RL7 model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for this model. ©2004–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04931-0-5/16(F) Rev. F | Page 16 of 16

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: ADM4850ACPZ-REEL7 ADM4850ARMZ ADM4850ARMZ-REEL7 ADM4850ARZ ADM4850ARZ-REEL7 ADM4851ARZ ADM4851ARZ-REEL7 ADM4852ACPZ-REEL7 ADM4852ARZ ADM4852ARZ-REEL7 ADM4853ACPZ-REEL7 ADM4853ARZ ADM4853ARZ-REEL7 ADM4853WARZ-RL7 ADM4854ARZ ADM4855AR- REEL7 ADM4855ARZ ADM4856ARZ ADM4857ARZ ADM4857ARZ-REEL7 ADM4856AR-REEL ADM4856ARZ- REEL7