Low Power, Differential ADC Driver Data Sheet ADA4932-1/ADA4932-2 FEATURES FUNCTIONAL BLOCK DIAGRAM High performance at low power ADA4932-1 High speed S S S S V V V V – – – – −3 dB bandwidth of 560 MHz, G = 1 6 5 4 3 1 1 1 1 0.1 dB gain flatness to 300 MHz Slew rate: 2800 V/μs, 25% to 75% –FB 1 12 PD Fast 0.1% settling time of 9 ns +IN 2 11 –OUT Low power: 9.6 mA per amplifier –IN 3 10 +OUT Low harmonic distortion +FB 4 9 VOCM 19000 d dBB S FSDFDRR a ta t2 100 M MHHz z 5+VS 6+VS 7+VS 8+VS 07752-001 Low input voltage noise: 3.6 nV/√Hz Figure 1. ADA4932-1 ±0.5 mV typical input offset voltage ADA4932-2 Externally adjustable gain 1 CDaifnfe bree nutsieadl- twoi-tdhi fgfearinens tlieasls o trh sainn g1l e-ended-to-differential 421NI+ 321BF– 22V–1S12V–1S021DP 91TUO– operation –IN11 18+OUT1 Adjustable output common-mode voltage +FB12 17VOCM1 Input common-mode range shifted down by 1 VBE +VS13 16–VS2 Wide supply range: +3 V to ±5 V +VS14 15–VS2 Available in 16-lead and 24-lead LFCSP packages –FB25 14PD2 +IN26 13–OUT2 APPLICATIONS ADC drivers 7 8 9 01 11 21 SIFin agnlde -beansdeebda-ntod- gdaififne rbelnoctikasl converters 2NI– 2BF+ V+2SV+2SV2MCO2TUO+ 07752-002 Figure 2. ADA4932-2 Differential buffers Line drivers GENERAL DESCRIPTION The ADA4932-1/ADA4932-2 are the next generation AD8132 The ADA4932-1/ADA4932-2 were fabricated using the with higher performance and lower noise and power consumption. Analog Devices, Inc., proprietary silicon-germanium (SiGe) They are an ideal choice for driving high performance ADCs as complementary bipolar process, enabling it to achieve low levels a single-ended-to-differential or differential-to-differential of distortion and noise at low power consumption. amplifier. The output common-mode voltage is user adjustable The low offset and excellent dynamic performance of the by means of an internal common-mode feedback loop, allowing ADA4932-1/ADA4932-2 make them well suited for a wide the ADA4932-1/ADA4932-2 output to match the input of the variety of data acquisition and signal processing applications. ADC. The internal feedback loop also provides exceptional The ADA4932-1 is available in a 16-lead LFCSP, and the output balance as well as suppression of even-order harmonic ADA4932-2 is available in a 24-lead LFCSP. The pinouts are distortion products. optimized to facilitate the printed circuit board (PCB) layout With the ADA4932-1/ADA4932-2, differential gain configurations and minimize distortion. The ADA4932-1/ADA4932-2 are are easily realized with a simple external four-resistor feedback specified to operate over the −40°C to +105°C temperature network that determines the closed-loop gain of the amplifier. range; both operate on supplies between +3 V and ±5 V. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2008–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADA4932-1/ADA4932-2 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 19 Applications ....................................................................................... 1 Applications Information .............................................................. 20 Functional Block Diagram .............................................................. 1 Analyzing an Application Circuit ............................................ 20 General Description ......................................................................... 1 Setting the Closed-Loop Gain .................................................. 20 Revision History ............................................................................... 2 Estimating the Output Noise Voltage ...................................... 20 Specifications ..................................................................................... 3 Impact of Mismatches in the Feedback Networks ................. 21 ±5 V Operation ............................................................................. 3 Calculating the Input Impedance for an Application Circuit .... 21 5 V Operation ............................................................................... 5 Input Common-Mode Voltage Range ..................................... 23 Absolute Maximum Ratings ............................................................ 7 Input and Output Capacitive AC Coupling ............................ 23 Thermal Resistance ...................................................................... 7 Setting the Output Common-Mode Voltage .......................... 23 Maximum Power Dissipation ..................................................... 7 High Performance Precision ADC Driver .............................. 23 ESD Caution .................................................................................. 7 High Performance ADC Driving ................................................. 25 Pin Configurations and Function Descriptions ........................... 8 Layout, Grounding, and Bypassing .............................................. 26 Typical Performance Characteristics ............................................. 9 Outline Dimensions ....................................................................... 27 Test Circuits ..................................................................................... 17 Ordering Guide .......................................................................... 27 Terminology .................................................................................... 18 REVISION HISTORY 5/2016—Rev. D to Rev. E 1/2014—Rev. B to Rev. C Changed ADA4932 Family to ADA4932-1/ADA4932-2, Changes to Figure 51 ...................................................................... 16 ADA4932-x to ADA4932-1/ADA4932-2, and CP-16-2 to CP-16-21 ......................................................................... Throughout 3/2013—Rev. A to Rev. B Deleted Figure 2 and Figure 3; Renumbered Sequentially .......... 1 Updated Outline Dimensions ....................................................... 26 Added Figure 2 .................................................................................. 1 Changes to Ordering Guide .......................................................... 26 Updated Outline Dimensions ....................................................... 27 Changes to Ordering Guide .......................................................... 27 8/2009—Rev. 0 to Rev. A Changes to Features Section ............................................................ 1 Changes to Figure 11 ......................................................................... 9 4/2014—Rev. C to Rev. D Changes to Figure 43 and Figure 45 ............................................ 15 Changes to Features Section, Figure 2, and Figure 3 ................... 1 Changes to Figure 52, Figure 53, and Figure 54 ......................... 17 Changes to Setting the Output Common-Mode Voltage Section .. 23 Added High Performance Precision ADC Driver Section ....... 24 10/2008—Revision 0: Initial Version Moved Layout, Grounding, and Bypassing Section ................... 26 Rev. E | Page 2 of 27

Data Sheet ADA4932-1/ADA4932-2 SPECIFICATIONS ±5 V OPERATION T = 25°C, +V = 5 V, −V = −5 V, V = 0 V, R = 499 Ω, R = 499 Ω, R = 53.6 Ω (when used), R = 1 kΩ, unless otherwise noted. A S S OCM F G T L, dm All specifications refer to single-ended input and differential outputs, unless otherwise noted. Refer to Figure 54 for signal definitions. ±D to V Performance IN OUT, dm Table 1. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth V = 0.1 V p-p 560 MHz OUT, dm V = 0.1 V p-p, R = R = 205 Ω 1000 MHz OUT, dm F G −3 dB Large Signal Bandwidth V = 2.0 V p-p 360 MHz OUT, dm V = 2.0 V p-p, R = R = 205 Ω 360 MHz OUT, dm F G Bandwidth for 0.1 dB Flatness V = 2.0 V p-p, ADA4932-1, R = 200 Ω 300 MHz OUT, dm L V = 2.0 V p-p, ADA4932-2, R = 200 Ω 100 MHz OUT, dm L Slew Rate V = 2 V p-p, 25% to 75% 2800 V/μs OUT, dm Settling Time to 0.1% V = 2 V step 9 ns OUT, dm Overdrive Recovery Time V = 0 V to 5 V ramp, G = 2 20 ns IN NOISE/HARMONIC PERFORMANCE See Figure 53 for distortion test circuit Second Harmonic V = 2 V p-p, 1 MHz −110 dBc OUT, dm V = 2 V p-p, 10 MHz −100 dBc OUT, dm V = 2 V p-p, 20 MHz −90 dBc OUT, dm V = 2 V p-p, 50 MHz −72 dBc OUT, dm Third Harmonic V = 2 V p-p, 1 MHz −130 dBc OUT, dm V = 2 V p-p, 10 MHz −120 dBc OUT, dm V = 2 V p-p, 20 MHz −105 dBc OUT, dm V = 2 V p-p, 50 MHz −80 dBc OUT, dm IMD f = 30 MHz, f = 30.1 MHz, V = 2 V p-p −91 dBc 1 2 OUT, dm Voltage Noise (RTI) f = 1 MHz 3.6 nV/√Hz Input Current Noise f = 1 MHz 1.0 pA/√Hz Crosstalk f = 10 MHz, ADA4932-2 −100 dB INPUT CHARACTERISTICS Offset Voltage V = V = V = 0 V −2.2 ±0.5 +2.2 mV +DIN −DIN OCM T to T variation −3.7 μV/°C MIN MAX Input Bias Current −5.2 −2.5 −0.1 μA T to T variation −9.5 nA/°C MIN MAX Input Offset Current −0.2 ±0.025 +0.2 μA Input Resistance Differential 11 MΩ Common mode 16 MΩ Input Capacitance 0.5 pF Input Common-Mode Voltage Range −V + 0.2 to V S +V − 1.8 S CMRR ∆V /∆V , ∆V = ±1 V −100 −87 dB OUT, dm IN, cm IN, cm Open-Loop Gain 64 66 dB OUTPUT CHARACTERISTICS Output Voltage Swing Maximum ∆V , single-ended output, −V + 1.4 to −V + 1.2 to V OUT S S R = R = 10 kΩ, R = 1 kΩ +V − 1.4 +V − 1.2 F G L S S Linear Output Current 200 kHz, R = 10 Ω, SFDR = 68 dB 80 mA rms L, dm Output Balance Error ∆V /∆V , ∆V = 2 V p-p, 1 MHz, −64 −60 dB OUT, cm OUT, dm OUT, dm see Figure 52 for output balance test circuit Rev. E | Page 3 of 27

ADA4932-1/ADA4932-2 Data Sheet V to V Performance OCM OUT, cm Table 2. Parameter Test Conditions/Comments Min Typ Max Unit V DYNAMIC PERFORMANCE OCM −3 dB Small Signal Bandwidth V = 100 mV p-p 270 MHz OUT, cm −3 dB Large Signal Bandwidth V = 2 V p-p 105 MHz OUT, cm Slew Rate V = 1.5 V to 3.5 V, 25% to 75% 410 V/µs IN Input Voltage Noise (RTI) f = 1 MHz 9.6 nV/√Hz V INPUT CHARACTERISTICS OCM Input Voltage Range −V + 1.2 to +V − 1.2 V S S Input Resistance 22 25 29 kΩ Input Offset Voltage V = V = 0 V −5.1 ±1 +5.1 mV +DIN −DIN V CMRR ΔV /ΔV , ΔV = ±1 V −100 −86 dB OCM OUT, dm OCM OCM Gain ΔV /ΔV , ΔV = ±1 V 0.995 0.998 1.000 V/V OUT, cm OCM OCM General Performance Table 3. Parameter Test Conditions/Comments Min Typ Max Unit POWER SUPPLY Operating Range 3.0 11 V Quiescent Current per Amplifier 9.0 9.6 10.1 mA T to T variation 35 µA/°C MIN MAX Powered down 0.9 1.0 mA Power Supply Rejection Ratio ΔV /ΔV, ΔV = 1 V p-p −96 −84 dB OUT, dm S S POWER-DOWN (PD) PD Input Voltage Powered down ≤(+VS − 2.5) V Enabled ≥(+V − 1.8) V S Turn-Off Time 1100 ns Turn-On Time 16 ns PD Pin Bias Current per Amplifier Enabled PD = 5 V −10 +0.7 +10 µA Disabled PD = 0 V −240 −195 −140 µA OPERATING TEMPERATURE RANGE −40 +105 °C Rev. E | Page 4 of 27

Data Sheet ADA4932-1/ADA4932-2 5 V OPERATION T = 25°C, +V = 5 V, −V = 0 V, V = 2.5 V, R = 499 Ω, R = 499 Ω, R = 53.6 Ω (when used), R = 1 kΩ, unless otherwise noted. A S S OCM F G T L, dm All specifications refer to single-ended input and differential outputs, unless otherwise noted. Refer to Figure 54 for signal definitions. ±D to V Performance IN OUT, dm Table 4. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth V = 0.1 V p-p 560 MHz OUT, dm V = 0.1 V p-p, R = R = 205 Ω 990 MHz OUT, dm F G −3 dB Large Signal Bandwidth V = 2.0 V p-p 315 MHz OUT, dm V = 2.0 V p-p, R = R = 205 Ω 320 MHz OUT, dm F G Bandwidth for 0.1 dB Flatness V = 2.0 V p-p, ADA4932-1, R = 200 Ω 120 MHz OUT, dm L V = 2.0 V p-p, ADA4932-2, R = 200 Ω 200 MHz OUT, dm L Slew Rate V = 2 V p-p, 25% to 75% 2200 V/μs OUT, dm Settling Time to 0.1% V = 2 V step 10 ns OUT, dm Overdrive Recovery Time V = 0 V to 2.5 V ramp, G = 2 20 ns IN NOISE/HARMONIC PERFORMANCE See Figure 53 for distortion test circuit Second Harmonic V = 2 V p-p, 1 MHz −110 dBc OUT, dm V = 2 V p-p, 10 MHz −100 dBc OUT, dm V = 2 V p-p, 20 MHz −90 dBc OUT, dm V = 2 V p-p, 50 MHz −72 dBc OUT, dm Third Harmonic V = 2 V p-p, 1 MHz −120 dBc OUT, dm V = 2 V p-p, 10 MHz −100 dBc OUT, dm V = 2 V p-p, 20 MHz −87 dBc OUT, dm V = 2 V p-p, 50 MHz −70 dBc OUT, dm IMD f = 30 MHz, f = 30.1 MHz, V = 2 V p-p −91 dBc 1 2 OUT, dm Voltage Noise (RTI) f = 1 MHz 3.6 nV/√Hz Input Current Noise f = 1 MHz 1.0 pA/√Hz Crosstalk f = 10 MHz, ADA4932-2 −100 dB INPUT CHARACTERISTICS Offset Voltage V = V = V = 2.5 V −2.2 ±0.5 +2.2 mV +DIN −DIN OCM T to T variation −3.7 μV/°C MIN MAX Input Bias Current −5.3 −3.0 −0.23 μA T to T variation −9.5 nA/°C MIN MAX Input Offset Current −0.25 ±0.025 +0.25 μA Input Resistance Differential 11 MΩ Common mode 16 MΩ Input Capacitance 0.5 pF Input Common-Mode Voltage Range −V + 0.2 to V S +V − 1.8 S CMRR ∆V /∆V , ∆V = ±1 V −100 −87 dB OUT, dm IN, cm IN, cm Open-Loop Gain 64 66 dB OUTPUT CHARACTERISTICS Output Voltage Swing Maximum ∆V , single-ended output, −V + 1.15 to −V + 1.02 to V OUT S S R = R = 10 kΩ, R = 1 kΩ +V − 1.15 +V − 1.02 F G L S S Linear Output Current 200 kHz, R = 10 Ω, SFDR = 67 dB 53 mA rms L, dm Output Balance Error ∆V /∆V , ∆V = 1 V p-p, 1 MHz, −64 −60 dB OUT, cm OUT, dm OUT, dm see Figure 52 for output balance test circuit Rev. E | Page 5 of 27

ADA4932-1/ADA4932-2 Data Sheet V to V Performance OCM OUT, cm Table 5. Parameter Test Conditions/Comments Min Typ Max Unit V DYNAMIC PERFORMANCE OCM −3 dB Small Signal Bandwidth V = 100 mV p-p 260 MHz OUT, cm −3 dB Large Signal Bandwidth V = 2 V p-p 90 MHz OUT, cm Slew Rate V = 1.5 V to 3.5 V, 25% to 75% 360 V/µs IN Input Voltage Noise (RTI) f = 1 MHz 9.6 nV/√Hz V INPUT CHARACTERISTICS OCM Input Voltage Range −V + 1.2 to +V − 1.2 V S S Input Resistance 22 25 29 kΩ Input Offset Voltage V = V = 2.5 V −6.5 −3.0 +6.5 mV +DIN −DIN V CMRR ΔV /ΔV , ΔV = ±1 V −100 −86 dB OCM OUT, dm OCM OCM Gain ΔV /ΔV , ΔV = ±1 V 0.995 0.998 1.000 V/V OUT, cm OCM OCM General Performance Table 6. Parameter Test Conditions/Comments Min Typ Max Unit POWER SUPPLY Operating Range 3.0 11 V Quiescent Current per Amplifier 8.2 8.8 9.5 mA T to T variation 35 µA/°C MIN MAX Powered down 0.7 0.8 mA Power Supply Rejection Ratio ΔV /ΔV, ΔV = 1 V p-p −96 −84 dB OUT, dm S S POWER-DOWN (PD) PD Input Voltage Powered down ≤(+VS − 2.5) V Enabled ≥(+V − 1.8) V S Turn-Off Time 1100 ns Turn-On Time 16 ns PD Pin Bias Current per Amplifier Enabled PD = 5 V −10 +0.7 +10 µA Disabled PD = 0 V −100 −70 −40 µA OPERATING TEMPERATURE RANGE −40 +105 °C Rev. E | Page 6 of 27

Data Sheet ADA4932-1/ADA4932-2 ABSOLUTE MAXIMUM RATINGS The power dissipated in the package (P ) is the sum of the Table 7. D quiescent power dissipation and the power dissipated in the Parameter Rating package due to the load drive. The quiescent power is the voltage Supply Voltage 11 V between the supply pins (V) times the quiescent current (I). Power Dissipation See Figure 3 S S The power dissipated due to the load drive depends upon the Input Current, +IN, −IN, PD ±5 mA particular application. The power due to load drive is calculated Storage Temperature Range −65°C to +125°C by multiplying the load current by the associated voltage drop Operating Temperature Range across the device. RMS voltages and currents must be used in ADA4932-1 −40°C to +105°C these calculations. ADA4932-2 −40°C to +105°C Lead Temperature (Soldering, 10 sec) 300°C Airflow increases heat dissipation, effectively reducing θJA. In Junction Temperature 150°C addition, more metal directly in contact with the package leads/ exposed pad from metal traces, through holes, ground, and power Stresses at or above those listed under Absolute Maximum planes reduces θ . JA Ratings may cause permanent damage to the product. This is a Figure 3 shows the maximum safe power dissipation in the stress rating only; functional operation of the product at these package vs. the ambient temperature for the single 16-lead or any other conditions above those indicated in the operational LFCSP (91°C/W) and the dual 24-lead LFCSP (65°C/W) on a section of this specification is not implied. Operation beyond JEDEC standard 4-layer board with the exposed pad soldered to the maximum operating conditions for extended periods may a PCB pad that is connected to a solid plane. affect product reliability. 3.5 THERMAL RESISTANCE θJA is specified for the device (including exposed pad) soldered W) 3.0 to a high thermal conductivity 2s2p circuit board, as described N ( O in EIA/JESD 51-7. ATI 2.5 ADA4932-2 P SI S 2.0 Table 8. Thermal Resistance DI R Package Type θ Unit E JA W 1.5 ADA4932-1, 16-Lead LFCSP (Exposed Pad) 91 °C/W PO ADA4932-1 M ADA4932-2, 24-Lead LFCSP (Exposed Pad) 65 °C/W U 1.0 M XI A M 0.5 MAXIMUM POWER DISSIPATION The maximum safe power dissipation for the ADA4932-1/ 0 ADA4932-2 package is limited by the associated rise in junction –40 –20 A0MBIENT2 0TEMPE4R0ATURE6 (0°C) 80 100 07752-204 temperature (TJ) on the die. At approximately 150°C, which is Figure 3. Maximum Power Dissipation vs. Ambient Temperature for the glass transition temperature, the plastic changes its properties. a 4-Layer Board Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently ESD CAUTION shifting the parametric performance of the ADA4932-1/ ADA4932-2. Exceeding a junction temperature of 150°C for an extended period can result in changes in the silicon devices, potentially causing failure. Rev. E | Page 7 of 27

ADA4932-1/ADA4932-2 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1 1NI+ 1BF– V–1SV–1S1DP TUO– VS VS VS VS 42 32 22 12 02 91 – – – – 6 5 4 3 1 1 1 1 –IN11 18+OUT1 +FB12 17VOCM1 –FB 1 12PD +VS13 ADA4932-2 16–VS2 +IN 2 ADA4932-1 11 –OUT +VS14 (NToOt Pto V SIEcaWle) 15–VS2 –IN 3 TOP VIEW 10 +OUT –FB25 14PD2 (Not to Scale) +FB 4 9 VOCM +IN26 13–OUT2 5+VS 6+VS 7+VS 8+VS 2NI–7 2BF+8 V+92S01V+2S112MCO2TUO21 N1.OSTTOOE LSGDREORU ENXDP POLSAENDE P OARD DTLOE A O PNO BWAECRK POLFA PNAEC.KAGE 07752-005 N1.OSTTOOE LSGDREORU ENXDP POLSAENDE P OARD DTLOE A VO PNO +BWAECRK POLFA PNAEC.KAGE 07752-006 Figure 4. ADA4932-1 Pin Configuration Figure 5. ADA4932-2 Pin Configuration Table 9. ADA4932-1 Pin Function Descriptions Pin No. Mnemonic Description 1 −FB Negative Output for Feedback Component Connection. 2 +IN Positive Input Summing Node. 3 −IN Negative Input Summing Node. 4 +FB Positive Output for Feedback Component Connection. 5 to 8 +V Positive Supply Voltage. S 9 V Output Common-Mode Voltage. OCM 10 +OUT Positive Output for Load Connection. 11 −OUT Negative Output for Load Connection. 12 PD Power-Down Pin. 13 to 16 −V Negative Supply Voltage. S 17 Exposed Paddle (EPAD) Solder the exposed paddle on the back of the package to a ground plane or to a power plane. Table 10. ADA4932-2 Pin Function Descriptions Pin No. Mnemonic Description 1 −IN1 Negative Input Summing Node 1. 2 +FB1 Positive Output Feedback 1. 3, 4 +V Positive Supply Voltage 1. S1 5 −FB2 Negative Output Feedback 2. 6 +IN2 Positive Input Summing Node 2. 7 −IN2 Negative Input Summing Node 2. 8 +FB2 Positive Output Feedback 2. 9, 10 +V Positive Supply Voltage 2. S2 11 V Output Common-Mode Voltage 2. OCM2 12 +OUT2 Positive Output 2. 13 −OUT2 Negative Output 2. 14 PD2 Power-Down Pin 2. 15, 16 −V Negative Supply Voltage 2. S2 17 V Output Common-Mode Voltage 1. OCM1 18 +OUT1 Positive Output 1. 19 −OUT1 Negative Output 1. 20 PD1 Power-Down Pin 1. 21, 22 −V Negative Supply Voltage 1. S1 23 −FB1 Negative Output Feedback 1. 24 +IN1 Positive Input Summing Node 1. 25 Exposed Paddle (EPAD) Solder the exposed paddle on the back of the package to a ground plane or to a power plane. Rev. E | Page 8 of 27

Data Sheet ADA4932-1/ADA4932-2 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, +V = 5 V, −V = −5 V, V = 0 V, R = 499 Ω, R = 499 Ω, R = 53.6 Ω (when used), R = 1 kΩ, unless otherwise noted. A S S OCM G F T L, dm Refer to Figure 51 for test setup. Refer to Figure 54 for signal definitions. 2 2 VIN = 100mV p-p GAIN = 1 VIN = 2V p-p GAIN = 1 B) 1 RF=499Ω GAIN = 2 B) 1 RF=499Ω GAIN = 2 N(d 0 RG=499Ω, 249Ω N(d 0 RG=499Ω, 249Ω AI AI G G –1 –1 P P O O LO –2 LO –2 D- D- SE –3 SE –3 O O L L C –4 C –4 D D E E Z –5 Z –5 LI LI A A M –6 M –6 R R O O N ––87 07752-007 N ––87 07752-010 1M 10M 100M 1G 1M 10M 100M 1G FREQUENCY (Hz) FREQUENCY (Hz) Figure 6. Small Signal Frequency Response for Various Gains Figure 9. Large Signal Frequency Response for Various Gains 2 2 1 VOUT, dm = 100mV p-p RRFF==RRGG==429095ΩΩ 1 VOUT, dm = 2V p-p RF = RG = 499Ω 0 0 GAIN(dB) ––21 GAIN (dB) ––21 RF = RG = 205Ω OP –3 OP –3 O O CLOSED-L ––54 CLOSED-L ––54 –6 –6 ––87 07752-008 ––87 1M 10M FREQU1E00NMCY (Hz) 1G 10G 1 10FREQUENCY (MHz1)00 1k 07752-058 Figure 7. Small Signal Frequency Response for Various RF and RG Figure 10. Large Signal Frequency Response for Various RF and RG 2 2 VOUT, dm = 100mV p-p VOUT, dm = 2V p-p 1 1 0 0 dB) –1 VS = ±5V dB) –1 VS = ±5V N( VS = ±2.5V N( VS = ±2.5V AI –2 AI –2 G G P P O –3 O –3 O O L L D- –4 D- –4 E E S S O –5 O –5 L L C C –6 –6 ––87 07752-009 ––87 07752-012 1M 10M 100M 1G 1M 10M 100M 1G FREQUENCY (Hz) FREQUENCY (Hz) Figure 8. Small Signal Frequency Response for Various Supplies Figure 11. Large Signal Frequency Response for Various Supplies Rev. E | Page 9 of 27

ADA4932-1/ADA4932-2 Data Sheet 2 2 VOUT, dm = 100mV p-p VOUT, dm = 2V p-p 1 1 0 0 B) B) d –1 d –1 ( ( AIN –2 TA=–40°C AIN –2 TA=–40°C OP G –3 TTAA==++2150°5C°C OP G –3 TTAA==++2150°5C°C O O L L D- –4 D- –4 E E S S O –5 O –5 L L C C –6 –6 ––87 07752-013 ––87 07752-016 1M 10M 100M 1G 1M 10M 100M 1G FREQUENCY (Hz) FREQUENCY (Hz) Figure 12. Small Signal Frequency Response for Various Temperatures Figure 15. Large Signal Frequency Response for Various Temperatures 2 2 VOUT, dm = 100mV p-p RL = 1kΩ VOUT, dm = 2V p-p RL = 1kΩ 1 RL = 200Ω 1 RL = 200Ω 0 0 B) B) d –1 d –1 ( ( N N AI –2 AI –2 G G P P O –3 O –3 O O L L D- –4 D- –4 E E S S O –5 O –5 L L C C –6 –6 ––87 07752-014 ––87 07752-017 1M 10M 100M 1G 1M 10M 100M 1G FREQUENCY (Hz) FREQUENCY (Hz) Figure 13. Small Signal Frequency Response at Various Loads Figure 16. Large Signal Frequency Response at Various Loads 2 2 VOUT, dm = 100mV p-p VOUT, dm = 2V p-p 1 1 0 0 B) B) d –1 d –1 ( ( AIN –2 VOCM=0V AIN –2 VOCM=0V OP G –3 VVOOCCMM== –+22..55VV OPG –3 VVOOCCMM== –+22..55VV O O L L D- –4 D- –4 E E S S O –5 O –5 L L C C –6 –6 ––87 07752-015 ––87 07752-018 1M 10M 100M 1G 1M 10M 100M 1G FREQUENCY (Hz) FREQUENCY (Hz) Figure 14. Small Signal Frequency Response for Various VOCM Levels Figure 17. Large Signal Frequency Response for Various VOCM Levels Rev. E | Page 10 of 27

Data Sheet ADA4932-1/ADA4932-2 4 4 VOUT, dm = 100mV p-p VOUT, dm = 2V p-p 2 2 AIN(dB) 0 CCCLLL===001p..98FppFF AIN(dB) 0 CL=0pF G G –2 CL=0.9pF OP –2 OP CL=1.8pF O O D-L D-L –4 E E OS –4 OS CL CL –6 –6 –8 –8 07752-019 –10 07752-022 1M 10M 100M 1G 10G 10M 100M 1G FREQUENCY (Hz) FREQUENCY(Hz) Figure 18. Small Signal Frequency Response at Various Capacitive Loads Figure 21. Large Signal Frequency Response at Various Capacitive Loads 0.5 0.5 VOUT, dm = 100mV p-p VOUT, dm = 2V p-p 0.4 0.4 0.3 0.3 B) B) d 0.2 d 0.2 ( ( N N AI 0.1 AI 0.1 G G P P O 0 O 0 O O L L D-–0.1 D-–0.1 CLOSE––––0000....5432 AAAAAADDDDDDAAAAAA444444999999333333222222------112222,,,,,, RRCCCCHHHHLL ==1122 ,,,,12 RRRRk0Ω0LLLLΩ==== 1212k0k0ΩΩ00ΩΩ 07752-020 CLOSE––––0000....5432 AAAAAADDDDDDAAAAAA444444999999333333222222------112222,,,,,, RRCCCCHHHHLL ==1122 ,,,,12 RRRRk00ΩLLLLΩ==== 1212k0k000ΩΩΩΩ 07752-023 1M 10M 100M 1G 1M 10M 100M 1G FREQUENCY (Hz) FREQUENCY (Hz) Figure 19. 0.1 dB Flatness Small Signal Frequency Response for Various Loads Figure 22. 0.1 dB Flatness Large Signal Frequency Response for Various Loads 2 2 VOUT, cm = 100mV p-p VOUT, cm = 2V p-p 1 1 0 0 –1 –1 N(dB) –2 VVOOCCMM((DDCC))==+0V2.5V N (dB) –2 AI –3 VOCM(DC)=–2.5V AI –3 G G M M C–4 C –4 O O V V –5 –5 –6 –6 VOCM (DC) = 0V ––87 07752-021 ––87 VVOOCCMM ((DDCC)) == –+22..55VV 1M 10MFREQUENCY (Hz1)00M 1G 1M 10MFREQUENCY (Hz1)00M 1G 07752-224 Figure 20. VOCM Small Signal Frequency Response at Various DC Levels Figure 23. VOCM Large Signal Frequency Response at Various DC Levels Rev. E | Page 11 of 27

ADA4932-1/ADA4932-2 Data Sheet –40 –40 VOUT, dm = 2V p-p VOUT, dm = 2V p-p –50 –50 HD2, RL=1kΩ HD2, G = 1 c) –60 HD3, RL=1kΩ c) –60 HD3, G = 1 dB HD2, RL=200Ω dB HD2, G = 2 N ( –70 HD3, RL=200Ω N ( –70 HD3, G = 2 O O TI –80 TI –80 R R O O ST –90 ST –90 DI DI C –100 C –100 NI NI O O M–110 M–110 R R A A H–120 H–120 ––114300 07752-025 ––114300 07752-028 100k 1M 10M 100M 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 24. Harmonic Distortion vs. Frequency at Various Loads Figure 27. Harmonic Distortion vs. Frequency at Various Gains –40 –40 VOUT, dm = 2V p-p VOCM = 0V –50 VOCM = 0V –50 HD2, ±5.0V c) –60 c) –60 HD3, ±5.0V B B d HD2, ±5.0V d HD2, ±2.5V N ( –70 HD3, ±5.0V N ( –70 HD3, ±2.5V O O TI –80 HD2, ±2.5V TI –80 OR HD3, ±2.5V OR ST –90 ST –90 DI DI C –100 C –100 NI NI O O M–110 M–110 R R A A H–120 H–120 ––114300 07752-026 ––113400 07752-029 100k 1M 10M 100M 0 1 2 3 4 5 6 7 8 9 10 FREQUENCY (Hz) VOUT, dm (V p-p) Figure 25. Harmonic Distortion vs. Frequency at Various Supplies Figure 28. Harmonic Distortion vs. VOUT, dm and Supply Voltage, f = 10 MHz –30 –20 VOUT = 2V p-p VOUT = 2V p-p –40 –30 HD2 AT 10MHz Bc) –50 HD3 AT 10MHz Bc) –40 N (d –60 HHDD23 AATT 3300MMHHzz N (d –50 HHDD23 AATT 1100MMHHzz O O TI –70 TI –60 HD2 AT 30MHz OR OR HD3 AT 30MHz ST –80 ST –70 DI DI C –90 C –80 NI NI O O M–100 M –90 R R A A H–110 H–100 ––113200 07752-027 ––112100 07752-030 –4 –3 –2 –1 0 1 2 3 4 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 VOCM (V p-p) VOCM(V) Figure 26. Harmonic Distortion vs. VOCM at Various Frequencies, ±5 V Supplies Figure 29. Harmonic Distortion vs. VOCM at Various Frequencies, +5 V Supply Rev. E | Page 12 of 27

Data Sheet ADA4932-1/ADA4932-2 –40 –40 VOUT, dm = 2V p-p –50 –50 HD2, 2V p-p HD2, RF=RG=499Ω c) –60 HD3, 2V p-p c) –60 HD3, RF=RG=499Ω dB HD2, 4V p-p dB HD2, RF=RG=200Ω N ( –70 HD3, 4V p-p N ( –70 HD3, RF=RG=200Ω O O TI –80 TI –80 R R O O ST –90 ST –90 DI DI C –100 C –100 NI NI O O M–110 M–110 R R A A H–120 H–120 ––114300 07752-031 ––114300 07752-034 100k 1M 10M 100M 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 30. Harmonic Distortion vs. Frequency at Various VOUT, dm Figure 33. Harmonic Distortion vs. Frequency at Various RF and RG –40 10 VOUT, dm = 2V p-p VOUT, dm = 2V p-p c) –50 0 B d –10 GE ( –60 dBc) –20 RAN –70 UM ( –30 AMIC –80 RL = 200Ω ECTR –40 N –90 P –50 Y S E D–100 ED –60 E Z US-FR–110 RL = 1kΩ RMALI ––8700 RIO–120 NO –90 U SP––114300 07752-032 ––111000 100k 1MFREQUENCY (Hz)10M 100M 29.6 29.7 29.8 29.F9RE3Q0U.0ENC3Y0 .(1MHz3)0.2 30.3 30.4 30.5 07752-235 Figure 31. Spurious-Free Dynamic Range vs. Frequency at Various Loads Figure 34. 30 MHz Intermodulation Distortion –20 0 RL, dm = 200Ω –30 RL, dm= 200Ω –20 –40 –40 –50 CMMR (dB) ––6700 PSSR (dB) ––8600 –PSRR –100 –80 +PSRR –1–0900 07752-033 ––114200 07752-036 1M 10M 100M 1G 1M 10M 100M 1G FREQUENCY (Hz) FREQUENCY (Hz) Figure 32. CMRR vs. Frequency Figure 35. PSRR vs. Frequency Rev. E | Page 13 of 27

ADA4932-1/ADA4932-2 Data Sheet –10 80 90 RL, dm = 200Ω 60 45 –20 40 0 B) GAIN TPUT BALANCE (d –––543000 GAIN (dB) –22000 PHASE –––1943055 PHASE (Degrees) U O –40 –180 –60 –60 –225 –70 –80 –270 1M 10MFREQUENCY (Hz1)00M 1G 07752-237 1k 10k 100k FRE1MQUENC1Y0 M(Hz) 100M 1G 10G 07752-240 Figure 36. Output Balance vs. Frequency Figure 39. Open-Loop Gain and Phase vs. Frequency 0 100 INPUT SINGLE-ENDED, 50Ω LOAD TERMINATION OUTPUT DIFFERENTIAL, 100Ω SOURCE TERMINATION S11: COMMON-MODE-TO-COMMON-MODE –10 S22: DIFFERENTIAL-TO-DIFFERENTIAL Ω) RS (dB) –20 S22 ANCE ( 10 E D ET –30 PE ARAM RL= 200Ω S11 UT IM S-P –40 UTP 1 O –50 –60 07752-038 0.1 1M 10MFREQUENCY (Hz1)00M 1G 100k 1M FREQU1E0NMCY (Hz) 100M 1G 07752-241 Figure 37. Return Loss (S11, S22) vs. Frequency Figure 40. Closed-Loop Output Impedance Magnitude vs. Frequency, G = 1 100 10 2 × VIN 8 Hz) 6 nV/√ 4 VOUT, dm ( SE V) 2 ENOI 10 AGE ( 0 G T A L T O –2 L V O V –4 T U NP –6 I 1 07752-039 –1–08 10 100 FR1kEQUENCY1(H0kz) 100k 1M 0 100 200 300 400TIM5E0 0(ns)600 700 800 900 1000 07752-242 Figure 38. Voltage Noise Spectral Density, Referred to Input Figure 41.Overdrive Recovery, G = 2 Rev. E | Page 14 of 27

Data Sheet ADA4932-1/ADA4932-2 1.5 0.06 1.0 0.04 V) V) E ( 0.5 VOLTAGE ( 0.020 T VOLTAG 0 UTPUT –0.02 OUTPU –0.5 O –1.0 –0.04 –1.5 07752-146 –0.06 0 5 10 15 20 25 30 0 5 10 TIM1E5 (ns) 20 25 30 07752-059 TIME (ns) Figure 42. Small Signal Pulse Response Figure 45. Large Signal Pulse Response 0.08 1.5 0.06 1.0 0.04 V) V) GE ( 0.02 GE ( 0.5 A A T T OL 0 OL 0 V V PUT –0.02 PUT CL = 0pF OUT–0.04 CCLL == 00p.9FpF OUT –0.5 CCLL == 01..98ppFF CL = 1.8pF –1.0 –0.06 –0.08 –1.5 0 5 10 TIM1E5 (ns) 20 25 30 07752-244 0 5 10 TIM1E5 (ns) 20 25 30 07752-247 Figure 43. Small Signal Pulse Response for Various Capacitive Loads Figure 46. Large Signal Pulse Response for Various Capacitive Loads 0.06 1.5 0.04 1.0 V) V) E ( 0.02 E ( 0.5 G G A A T T OL 0 OL 0 V V UT UT P P UT–0.02 UT –0.5 O O –0.04 –1.0 –0.060 5 10 TIM1E5 (ns) 20 25 30 07752-060 –1.50 5 10 TIM1E5 (ns) 20 25 3007752-148 Figure 44. VOCM Small Signal Pulse Response Figure 47. VOCM Large Signal Pulse Response Rev. E | Page 15 of 27

ADA4932-1/ADA4932-2 Data Sheet 2.0 0.5 1.2 8 GAIN = 9 1.6 0.4 1.0 6 RL, dm = 200Ω PD 1.2 INPUT 0.3 0.8 4 AGE (V) 00..048 OUTPUT 000..12 OR (%) OLTAGE (V) 00..46 VOUT, dm 02 TAGE (V) VOLT–0.4 ERROR –0.1 ERR PUT V 0.2 –2 D VOL –0.8 –0.2 OUT 0 –4 P –0.2 –6 –1.2 –0.3 –1.6 –0.4 –0.4 –8 –2.0 0 2 4 6 8TIME1 (0ns) 12 14 16 18 20–0.507752-149 –0.60 0.5 1.0 1.5 TIM2E.0 (µs) 2.5 3.0 3.5 4.0–10 07752-252 Figure 48. Settling Time Figure 50. PD Response Time 0 VOUT, dm = 2V p-p –20 RL, dm= 200Ω CHANNEL 1 TO CHANNEL 2 –40 CHANNEL 2 TO CHANNEL 1 B) d –60 K ( L A –80 T S S RO–100 C –120 ––116400 07752-150 1M 10M 100M 1G FREQUENCY (Hz) Figure 49. Crosstalk vs. Frequency, ADA4932-2 Rev. E | Page 16 of 27

Data Sheet ADA4932-1/ADA4932-2 TEST CIRCUITS 499Ω DC-COUPLED +5V GENERATOR 50Ω 499Ω VIN 53.6Ω VOCM ADA4932-1/ 1kΩ ADA4932-2 499Ω 25.5Ω 499Ω–5V 07752-043 Figure 51. Equivalent Basic Test Circuit, G = 1 NETWORK ANALYZER INPUT NETWORK 499Ω 49.9Ω ANALYZER OUTPUT AC-COUPLED +5V 50Ω 50Ω 499Ω 53.6Ω VOCM ADA4932-1/ VIN ADA4932-2 499Ω NETWORK ANALYZER 25.5Ω –5V INPUT 0.1µF 499Ω 49.9Ω 50Ω 07752-044 Figure 52. Test Circuit for Output Balance, CMRR 499Ω DC-COUPLED +5V GENERATOR 50Ω LOW-PASS 499Ω 0.1µF442Ω 200Ω 2:1 50Ω DUAL HP FILTER FILTER LP VIN 53.6Ω VOCM ADA4932-1/ 261Ω CT ADA4932-2 499Ω 0.1µF442Ω 25.5Ω 499Ω–5V 07752-045 Figure 53. Test Circuit for Distortion Measurements Rev. E | Page 17 of 27

ADA4932-1/ADA4932-2 Data Sheet TERMINOLOGY –FB Common-Mode Voltage RF Common-mode voltage refers to the average of two node voltages +DIN RG +IN –OUT with respect to the local ground reference. The output common- VOCM AADDAA44993322--12/ RL, dm VOUT, dm mode voltage is defined as –+DFIBN RG RF –IN +OUT 07752-046 BalanVcOeU T , cm = (V+OUT + V−OUT)/2 Figure 54. Signal and Circuit Definitions Output balance is a measure of how close the output differential Differential Voltage signals are to being equal in amplitude and opposite in phase. Differential voltage refers to the difference between two node Output balance is most easily determined by placing a well- voltages. For example, the output differential voltage (or matched resistor divider between the differential voltage nodes equivalently, output differential mode voltage) is defined as and comparing the magnitude of the signal at the divider midpoint with the magnitude of the differential signal (see Figure 52). By V = (V − V ) OUT, dm +OUT −OUT this definition, output balance is the magnitude of the output where V+OUT and V−OUT refer to the voltages at the +OUT and common-mode voltage divided by the magnitude of the output −OUT terminals with respect to a common ground reference. differential mode voltage. Similarly, the differential input voltage is defined as V VIN, dm = (+DIN − (−DIN)) OutputBalanceError OUT,cm V OUT,dm Rev. E | Page 18 of 27

Data Sheet ADA4932-1/ADA4932-2 THEORY OF OPERATION The ADA4932-1/ADA4932-2 differ from conventional op amps with external resistors, controls only the differential output voltage. in that it has two outputs whose voltages move in opposite The common-mode feedback controls only the common-mode directions and an additional input, V . Like an op amp, it relies output voltage. This architecture makes it easy to set the output OCM on high open-loop gain and negative feedback to force these common-mode level to any arbitrary value within the specified outputs to the desired voltages. The ADA4932-1/ADA4932-2 limits. The output common-mode voltage is forced, by the internal behave much like standard voltage feedback op amps and common-mode feedback loop, to be equal to the voltage applied facilitates single-ended-to-differential conversions, common- to the V input. OCM mode level shifting, and amplifications of differential signals. The internal common-mode feedback loop produces outputs Like an op amp, the ADA4932-1/ADA4932-2 have high input that are highly balanced over a wide frequency range without impedance and low output impedance. Because they use voltage requiring tightly matched external components. This results in feedback, the ADA4932-1/ADA4932-2 manifest a nominally differential outputs that are very close to the ideal of being constant gain bandwidth product. identical in amplitude and are exactly 180° apart in phase. Two feedback loops are employed to control the differential and common-mode output voltages. The differential feedback, set Rev. E | Page 19 of 27

ADA4932-1/ADA4932-2 Data Sheet APPLICATIONS INFORMATION ANALYZING AN APPLICATION CIRCUIT input, and the noise currents, inIN− and inIN+, appear between each input and ground. The output voltage due to v is obtained nIN The ADA4932-1/ADA4932-2 use high open-loop gain and by multiplying v by the noise gain, G (defined in the G nIN N N negative feedback to force their differential and common-mode equation that follows). The noise currents are uncorrelated with output voltages in such a way as to minimize the differential the same mean-square value, and each produces an output voltage and common-mode error voltages. The differential error that is equal to the noise current multiplied by the associated voltage is defined as the voltage between the differential inputs feedback resistance. The noise voltage density at the V /V OCM OCMx labeled +IN and −IN (see Figure 54). For most purposes, this pin is v . When the feedback networks have the same feedback nCM voltage is zero. Similarly, the difference between the actual factor, as is true in most cases, the output noise due to v is nCM output common-mode voltage and the voltage applied to V OCM common mode. Each of the four resistors contributes (4kTRxx)1/2. is also zero. Starting from these principles, any application circuit The noise from the feedback resistors appears directly at the output, can be analyzed. and the noise from the gain resistors appears at the output multip- SETTING THE CLOSED-LOOP GAIN lied by R/R . Table 11 summarizes the input noise sources, the F G multiplication factors, and the output-referred noise density terms. Using the approach described in the Analyzing an Application Circuit section, the differential gain of the circuit in Figure 54 VnRG1 RG1 RF1 VnRF1 can be determined by i nIN+ VOUT,dm  RF + VIN,dm RG inIN– VnIN AADDAA44993322--12/ VnOD This presumes that the input resistors (RG) and feedback resistors VOCM (R) on each side are equal. ESFTIMATING THE OUTPUT NOISE VOLTAGE VnRG2 RG2 RF2 VnRF2 VnCM 07752-047 Figure 55. Noise Model The differential output noise of the ADA4932-1/ADA4932-2 can be estimated using the noise model in Figure 55. The input- referred noise voltage density, v , is modeled as a differential nIN Table 11. Output Noise Voltage Density Calculations for Matched Feedback Networks Input Noise Output Differential Output Noise Input Noise Contribution Input Noise Term Voltage Density Multiplication Factor Voltage Density Term Differential Input v v G v = G (v ) nIN nIN N nO1 N nIN Inverting Input i i × (R ) 1 v = (i )(R ) nIN− nIN− F2 nO2 nIN− F2 Noninverting Input i i × (R ) 1 v = (i )(R ) nIN+ nIN+ F1 nO3 nIN+ F1 V Input v v 0 v = 0 V OCM nCM nCM nO4 Gain Resistor, R v (4kTR )1/2 R /R v = (R /R )(4kTR )1/2 G1 nRG1 G1 F1 G1 nO5 F1 G1 G1 Gain Resistor, R v (4kTR )1/2 R /R v = (R /R )(4kTR )1/2 G2 nRG2 G2 F2 G2 nO6 F2 G2 G2 Feedback Resistor, R v (4kTR )1/2 1 v = (4kTR )1/2 F1 nRF1 F1 nO7 F1 Feedback Resistor, R v (4kTR )1/2 1 v = (4kTR )1/2 F2 nRF2 F2 nO8 F2 Table 12. Differential Input, DC-Coupled Nominal Gain (dB) R (Ω) R (Ω) R (Ω) Differential Output Noise Density (nV/√Hz) F G IN, dm 0 499 499 998 9.25 6 499 249 498 12.9 10 768 243 486 18.2 Table 13. Single-Ended Ground-Referenced Input, DC-Coupled, R = 50 Ω S Nominal Gain (dB) R (Ω) R (Ω) R (Ω) (Std 1%) R (Ω) R (Ω)1 Differential Output Noise Density (nV/√Hz) F G1 T IN, cm G2 0 511 499 53.6 665 525 9.19 6 523 249 57.6 374 276 12.6 10 806 243 57.6 392 270 17.7 1 RG2 = RG1 + (RS||RT). Rev. E | Page 20 of 27

Data Sheet ADA4932-1/ADA4932-2 Similar to the case of a conventional op amp, the output noise much the same as for a four-resistor difference amplifier made voltage densities can be estimated by multiplying the input- from a conventional op amp. referred terms at +IN and −IN by the appropriate output factor, As a practical summarization of the above issues, resistors of 1% where: tolerance produce a worst-case input CMRR of approximately 2 40 dB, a worst-case differential-mode output offset of 25 mV G  is the circuit noise gain. N β β  due to a 2.5 V VOCM input, negligible VOCM noise contribution, 1 2 R R and no significant degradation in output balance error. β  G1 and β  G2 are the feedback factors. 1 R R 2 R R CALCULATING THE INPUT IMPEDANCE FOR AN F1 G1 F2 G2 APPLICATION CIRCUIT When the feedback factors are matched, R /R = R /R , β1 = F1 G1 F2 G2 β2 = β, and the noise gain becomes The effective input impedance of a circuit depends on whether the amplifier is being driven by a single-ended or differential 1 R G  1 F signal source. For balanced differential input signals, as shown N β R G in Figure 56, the input impedance (R ) between the inputs IN, dm Note that the output noise from VOCM goes to zero in this case. (+DIN and −DIN) is RIN, dm = RG + RG = 2 × RG. The total differential output noise density, vnOD, is the root-sum- RF square of the individual output noise terms. +VS 8 RG +IN v  v2 +DIN nOD i1 nOi VOCM AADDAA44993322--12/ VOUT, dm Table 12 and Table 13 list several common gain settings, –DIN RG –IN adsesnoscitiya tfeodr breostihs tboarl avnacluedes a, nindp uunt bimalpanedceadn cien,p auntd c oonuftipguutr natoioisnes . –RVSF 07752-048 IMPACT OF MISMATCHES IN THE FEEDBACK Figure 56. ADA4932-1/ADA4932-2 Configured for Balanced (Differential) Inputs NETWORKS For an unbalanced, single-ended input signal (see Figure 57), As previously mentioned, even if the external feedback networks the input impedance is (R/R ) are mismatched, the internal common-mode feedback F G   loop still forces the outputs to remain balanced. The amplitudes   of the signals at each output remain equal and 180° out of phase. R  RG  IN,se  R  The input-to-output differential mode gain varies proportionately 1  F  to the feedback mismatch, but the output balance is unaffected.  2 RG RF  The gain from the VOCM/VOCMx pin to VOUT, dm is equal to RF 2(β1 − β2)/(β1 + β2) RIN, se +VS When β1 = β2, this term goes to zero and there is no differential RG output voltage due to the voltage on the V input (including OCM noise). The extreme case occurs when one loop is open and the VOCM AADDAA44993322--12/ RL VOUT, dm other has 100% feedback; in this case, the gain from V input OCM RG to V is either +2 or −2, depending on which loop is closed. OUT, dm The feedback loops are nominally matched to within 1% in mVOoCsMt ianpppultic aartei onnesg,l iagnibdl et.h Ief tohuet plouotp ns oairsee i nantedn toioffnseatllsy d muies mtoa tthchee d RF–VS 07752-049 Figure 57. The ADA4932-1/ADA4932-2 with Unbalanced (Single-Ended) Input by a large amount, it is necessary to include the gain term from V to V and account for the extra noise. For example, if The input impedance of the circuit is effectively higher than it is OCM OUT, dm β1 = 0.5 and β2 = 0.25, the gain from V to V is 0.67. If for a conventional op amp connected as an inverter because a OCM OUT, dm the V /V pin is set to 2.5 V, a differential offset voltage is fraction of the differential output voltage appears at the inputs OCM OCMx present at the output of (2.5 V)(0.67) = 1.67 V. The differential as a common-mode signal, partially bootstrapping the voltage output noise contribution is (9.6 nV/√Hz)(0.67) = 6.4 nV/√Hz. across the input resistor, R . The common-mode voltage at the G Both of these results are undesirable in most applications; amplifier input terminals can be easily determined by noting that therefore, it is best to use nominally matched feedback factors. the voltage at the inverting input is equal to the noninverting output voltage divided down by the voltage divider that is formed Mismatched feedback networks also result in a degradation of by R and R in the lower loop. This voltage is present at both the ability of the circuit to reject input common-mode signals, F G input terminals due to negative voltage feedback and is in phase Rev. E | Page 21 of 27

ADA4932-1/ADA4932-2 Data Sheet with the input signal, thus reducing the effective voltage across 3. Figure 59 shows that the effective RG in the upper feedback R in the upper loop and partially bootstrapping R . loop is now greater than the R in the lower loop due to the G G G addition of the termination resistors. To compensate for the Terminating a Single-Ended Input imbalance of the gain resistors, add a correction resistor (R ) TS This section describes how to properly terminate a single-ended in series with R in the lower loop. R is the Thevenin G TS input to the ADA4932-1/ADA4932-2 with a gain of 1, R = 499 Ω, F equivalent of the source resistance, R, and the termination S and R = 499 Ω. An example using an input source with a G resistance, R , and is equal to R||R . T S T terminated output voltage of 1 V p-p and source resistance of 50 Ω illustrates the four steps that must be followed. Note that RS RTH because the terminated output voltage of the source is 1 V p-p, VS 50Ω R53T.6Ω VTH 25.9Ω tshoue rocpe esnh-ocwirnc uinit F oiugutprue t5 v8o ilntadgicea otefs t thhei ss ooupercne- ciisr c2u Vit vpo-lpt.a gTeh. e 2V p-p 1.03V p-p 07752-052 Figure 60. Calculating the Thevenin Equivalent 1. Calculate the input impedance by using the following formula: R = R = R||R = 25.9 Ω. Note that V is greater than TS TH S T TH 1 V p-p, which was obtained with R = 50 Ω. The modified T         circuit with the Thevenin equivalent (closest 1% value used for R  RG  499  665Ω RTH) of the terminated source and RTS in the lower feedback IN,se 1 RF  1 499  loop is shown in Figure 61.  2(RG RF)  2( 499  499) RF 499Ω RF +VS RIN, se 499Ω RTH RG 665Ω +VS 25.5Ω 499Ω RS RG 1.03V VpT-pH VOCM AADDAA44993322--12/ RL VOUT, dm 50Ω 499Ω RG 2V pV-pS VOCM AADDAA44993322--12/ RL VOUT, dm RTS 499Ω 25.5Ω RG –VS 499Ω –VS 49R9FΩ 07752-053 49R9FΩ 07752-050 FigFuigruer e6 161 p. Trehseevnentsin a E qtruaivcatlaebnlte a cnidr cMuaittc hweidth G amina Rtcehsiestdo rs Figure 58. Calculating Single-Ended Input Impedance, RIN feedback loops that can be easily evaluated. 2. To match the 50 Ω source resistance, calculate the It is useful to point out two effects that occur with a termination resistor, R , using R ||665 Ω = 50 Ω. The T T terminated input. The first is that the value of R is increased G closest standard 1% value for R is 53.6 Ω. T in both loops, lowering the overall closed-loop gain. The RF second is that VTH is a little larger than 1 V p-p, as it would RIN, se 499Ω be if RT = 50 Ω. These two effects have opposite impacts on 50Ω +VS the output voltage, and for large resistor values in the feedback RS RG loops (~1 kΩ), the effects essentially cancel each other out. 2V pV-pS 50Ω 53.6RΩT 4V9O9CΩM AADDAA44993322--12/ RL VOUT, dm Fcloors esmd-alollo RpF g aanind iRs Gn, ootr chaingche gleadin cso, mhopwleetveleyr ,b tyh eth dei minicnriesahseedd RG VTH. This can be seen by evaluating Figure 61. 499Ω The desired differential output in this example is 1 V p-p –VS because the terminated input signal was 1 V p-p and the 49R9FΩ 07752-051 chloowseedv-elro, oisp e gqauinal =to 1 (. 1T.0h3e Vac ptu-apl) (d4if9f9e/r5e2n4ti.a5l) o=u 0tp.9u8t vVo plt-apg.e , Figure 59. Adding Termination Resistor, RT To obtain the desired output voltage of 1 V p-p, a final gain adjustment can be made by increasing R without modifying F any of the input circuitry (see Step 4). Rev. E | Page 22 of 27

Data Sheet ADA4932-1/ADA4932-2 4. The feedback resistor value is modified as a final gain SETTING THE OUTPUT COMMON-MODE VOLTAGE adjustment to obtain the desired output voltage. The V /V pin of the ADA4932-1/ADA4932-2 is internally OCM OCMx To make the output voltage V = 1 V p-p, calculate R by biased with a voltage divider comprised of two 50 kΩ resistors OUT F using the following formula: across the supplies, with a tap at a voltage approximately equal DesiredV R R  to the midsupply point, [(+VS) + (−VS)]/2. Because of this R  OUT,dm G TS  internal divider, the VOCM/VOCMx pin sources and sinks current, F V   TH  depending on the externally applied voltage and its associated 1Vpp 524.5 source resistance. Relying on the internal bias results in an 509  1.03Vpp output common-mode voltage that is within about 100 mV of the expected value. The closest standard 1% value to 509 Ω is 511 Ω, which In cases where more accurate control of the output common- gives a differential output voltage of 1.00 V p-p. mode level is required, it is recommended that an external The final circuit is shown in Figure 62. source or resistor divider be used with source resistance less RF than 100 Ω. If an external voltage divider consisting of equal 511Ω resistor values is used to set V to midsupply with greater OCM 1V p-p +VS accuracy than produced internally, higher values can be used RS RG because the external resistors are placed in parallel with the 2V pV-pS 50Ω 53.6RΩT 4V9O9CΩM AADDAA44993322--12/ RL V1.O0U0TV, pdm-p iSnpteecrinfiacla rteiosinstso sresc. tTiohne aosusutpmuet sc othmatm thoen -VmOoCMd ein opfufste its l disrtievde nin b tyh ea RG low impedance voltage source. RTS 499Ω 25.5Ω It is also possible to connect the VOCM input to a common-mode –VS level (CML) output of an ADC; however, care must be taken to 51R1FΩ 07752-054 eimnspuerdea tnhcaet othf et hoeu Vtput h/Vas suff piciine nist adprpivreo xciampaabteilliyt y2. 5T khΩe .i nIfp ut OCM OCMx Figure 62. Terminated Single-Ended-to-Differential System with G = 2 multiple ADA4932-1/ADA4932-2 devices share one ADC INPUT COMMON-MODE VOLTAGE RANGE reference output, a buffer may be necessary to drive the parallel The ADA4932-1/ADA4932-2 input common-mode range is inputs. shifted down by approximately one VBE, in contrast to other HIGH PERFORMANCE PRECISION ADC DRIVER ADC drivers with centered input ranges such as the ADA4939-1/ Using a differential amplifier to drive an ADC successfully is ADA4939-2. The downward-shifted input common-mode linked to balancing each side of the differential amplifier range is especially suited to dc-coupled, single-ended-to- correctly. Figure 64 shows the schematic for the ADA4932-1, differential, and single-supply applications. AD7626, and associated circuitry. In the test circuit used, a For ±5 V operation, the input common-mode range at the 2.4 MHz band-pass filter follows the signal source. The band- summing nodes of the amplifier is specified as −4.8 V to +3.2 V, pass filter eliminates harmonics of the 2.4 MHz signal and and is specified as +0.2 V to +3.2 V with a +5 V supply. To ensures that only the frequency of interest is passed and avoid nonlinearities, the voltage swing at the +IN and −IN processed by the ADA4932-1 and AD7626. terminals must be confined to these ranges. The ADA4932-1 is particularly useful when driving higher fre- INPUT AND OUTPUT CAPACITIVE AC COUPLING quency inputs to the AD7626, a 10 MSPS ADC with a switched While the ADA4932-1/ADA4932-2 is best suited to dc-coupled capacitor input. The resistor (R8, R9) and capacitor (C5, C6) applications, it is nonetheless possible to use it in ac-coupled circuit between the ADA4932-1 and AD7626 IN+ and IN− pins circuits. Input ac coupling capacitors can be inserted between acts as a low-pass filter to noise. The filter limits the input band- the source and R . This ac coupling blocks the flow of the dc width to the AD7626, but its main function is to optimize the G common-mode feedback current and causes the ADA4932-1/ interface between the driving amplifier and the AD7626. The ADA4932-2 dc input common-mode voltage to equal the dc series resistor isolates the driver amplifier from high frequency output common-mode voltage. These ac coupling capacitors must switching spikes from the ADC switched capacitor front end. be placed in both loops to keep the feedback factors matched. The AD7626 data sheet shows values of 20 Ω and 56 pF. In Output ac coupling capacitors can be placed in series between Figure 64, these values were empirically optimized to 33 Ω and each output and its respective load. 56 pF. The resistor-capacitor combination can be optimized slightly for the circuit and input frequency being converted by simply varying the R-C combination; however, keep in mind that having the incorrect combination limits the THD and linearity performance of the AD7626. In addition, increasing the bandwidth as seen by the ADC introduces more noise. Rev. E | Page 23 of 27

ADA4932-1/ADA4932-2 Data Sheet Another aspect of optimization is the selection of the power supply voltages for the ADA4932-1. In the circuit, the output common-mode voltage (VCM pin) of the AD7626 is 2.048 V for the internal reference voltage of 4.096 V, and each input (IN+, IN−) swings between 0 V and 4.096 V, 180° out of phase. This provides an 8.2 V full-scale differential input to the ADC. The ADA4932-1 output stage requires about 1.4 V headroom with respect to each supply voltage for linear operation. Optimum distortion performance is obtained when the supply voltages are approximately symmetrical about the common-mode voltage. If a negative supply of −2.5 V is chosen, then a positive supply of at least +6.5 V is needed for symmetry about the common-mode voltage of 2.048 V. FREQUENCY (MHz) 07752-064 Experiments performed indicate that a positive supply of 7.25 V Figure 63. AD7626 Output, 64,000 Point, FFT Plot −1 dBFS Amplitude gives the best overall distortion for a 2.4 MHz tone. Using a low 2.40173 MHz Input Ton, 10.000 MSPS Sampling Rate jitter clock source and a single tone −1 dBFS amplitude, 2.402 MHz The nonharmonic noise admitted through the pass band of the input to the AD7626 yielded the results shown in Figure 63 of band-pass filter used in the circuit is replaced by the average 88.49 dB SNR and −86.17 dBc THD. At this input level, the ADC noise across the Nyquist bandwidth when calculating the SNR limits the SFDR to 83.8 dB. As can be seen from the plot, the and THD. The performance of this or any high speed circuit is harmonics of the fundamental alias back into the pass band. highly dependent on proper PCB layout. This includes, but is For example, when sampling at 10 MSPS, the third harmonic not limited to, power supply bypassing, controlled impedance (7.206 MHz) is aliased into the pass band at 10.000 MHz – lines (where required), component placement, signal routing, 7.206 MHz = 2.794 MHz. and power and ground planes. For a more detailed analysis of this circuit, refer to Circuit Note CN-0105. +5V 0.1µF 0.1µF +2.048V AD8031 +7.25V 0.1µF 5 6 7 8 +5V +2.5V +2.5V R6 FROM 499Ω 1 –FB +VS 0.1µF 0.1µF 0.1µF 50Ω +4.096V SIGNAL R3 R8 TO 0V SOURCE 2.4MHz 499Ω 2 +IN 11 33Ω VCM VDD1 VDD2 VIO BPF IN– R2 –OUT C5 53.6Ω 9 VOCM 56pF 0.1µF ADA4932-1 AD7626 R5 499Ω 3 –IN R9 +OUT 10 33Ω C1 IN+ GND R1 2.2nF R7 C6 53.6Ω R394Ω 499Ω 4 +FB 56pF 0V TO –VS +4.096V PAD 16 15 14 13 –2.5V 0.1µF 07752-065 Figure 64. ADA4932-1 Driving the AD7626 (All Connections and Decoupling Not Shown) Rev. E | Page 24 of 27

Data Sheet ADA4932-1/ADA4932-2 HIGH PERFORMANCE ADC DRIVING The ADA4932-1/ADA4932-2 are ideally suited for broadband Because the inputs are dc-coupled, dc common-mode current dc-coupled applications. The circuit in Figure 65 shows a front- flows in the feedback loops, and a nominal dc level of 0.84 V is end connection for an ADA4932-1 driving an AD9245, a 14-bit, present at the amplifier input terminals. A fraction of the output 20 MSPS/40 MSPS/65 MSPS/80 MSPS ADC, with dc coupling signal is also present at the input terminals as a common-mode on the ADA4932-1 input and output. (The AD9245 achieves signal; its level is equal to the ac output swing at the noninverting its optimum performance when driven differentially.) The output, divided down by the feedback factor of the lower loop. ADA4932-1 eliminates the need for a transformer to drive the In this example, this ripple is 0.5 V p-p × [524.5/(524.5 + 511)] = ADC and performs a single-ended-to-differential conversion and 0.25 V p-p. This ac signal is riding on the 0.84 V dc level, produc- buffering of the driving signal. ing a voltage swing between 0.72 V and 0.97 V at the input terminals. This is well within the specified limits of 0.2 V to 1.5 V. The ADA4932-1 is configured with a single 3.3 V supply and a gain of 1 for a single-ended input to differential output. The With an output common-mode voltage of 1.65 V, each ADA4932-1 53.6 Ω termination resistor, in parallel with the single-ended output swings between 1.4 V and 1.9 V, opposite in phase, input impedance of approximately 665 Ω, provides a 50 Ω providing a gain of 1 and a 1 V p-p differential signal to the termination for the source. The additional 25.5 Ω (524.5 Ω ADC input. The differential RC section between the ADA4932-1 total) at the inverting input balances the parallel impedance output and the ADC provides single-pole low-pass filtering and of the 50 Ω source and the termination resistor driving the extra buffering for the current spikes that are output from the noninverting input. ADC input when its SHA capacitors are discharged. In this example, the signal generator has a 1 V p-p symmetric, The AD9245 is configured for a 1 V p-p full-scale input by ground-referenced bipolar output when terminated in 50 Ω. connecting its SENSE pin to VREF, as shown in Figure 65. The V input is bypassed for noise reduction, and set externally OCM with 1% resistors to maximize output dynamic range on the tight 3.3 V supply. 511Ω VOUT, dm = 1V p-p 3.3V VOUT, cm = 1.65V 1V p-p CENTERED AT GROUND 0.1µF 0.1µF 10kΩ 50Ω 1% 499Ω 33Ω VIN– AVDD 2V p-p 53.6Ω VOCM ADA4932-1 20pF AD9245 SIGNAL 0.1µF 10kΩ GENERATOR 1% 499Ω VIN+ VREF SENSE AGND 33Ω 25.5Ω + 511Ω 0.1µF 10µF 07752-270 Figure 65. ADA4932-1 Driving an AD9245 ADC with DC-Coupled Input and Output Rev. E | Page 25 of 27

ADA4932-1/ADA4932-2 Data Sheet LAYOUT, GROUNDING, AND BYPASSING As a high speed device, the ADA4932-1/ADA4932-2 are Bypass the power supply pins as close to the device as possible sensitive to the PCB environment in which it operates. and directly to a nearby ground plane. Use high frequency ceramic Realizing its superior performance requires attention to the chip capacitors. It is recommended to use two parallel bypass details of high speed PCB design. capacitors (1000 pF and 0.1 μF) for each supply. Place the 1000 pF capacitor closer to the device. Further away, provide low The first requirement is a solid ground plane that covers as much frequency bulk bypassing using 10 μF tantalum capacitors from of the board area around the ADA4932-1/ADA4932-2 as each supply to ground. possible. However, the area near the feedback resistors (R), gain F resistors (R ), and clear the input summing nodes (Pin 2 and Ensure that signal routing is short and direct to avoid parasitic G Pin 3) of all ground and power planes (see Figure 66). Clearing the effects. Wherever complementary signals exist, provide a ground and power planes minimizes any stray capacitance at symmetrical layout to maximize balanced performance. When these nodes and thus minimizes peaking of the response of the routing differential signals over a long distance, keep PCB amplifier at high frequencies. traces close together, and twist any differential wiring to minimize loop area. Doing this reduces radiated energy and The thermal resistance, θ , is specified for the device, including JA makes the circuit less susceptible to interference. the exposed pad, soldered to a high thermal conductivity 4-layer circuit board, as described in EIA/JESD51-7. 1.30 0.80 1.300.80 07752-055 07752-056 Figure 66. Ground and Power Plane Voiding in Vicinity of RF and RG Figure 67. Recommended PCB Thermal Attach Pad Dimensions (Millimeters) 1.30 TOP METAL GROUND PLANE 0.30 PLATED VIA HOLE POWER PLANE BOTTOM METAL 07752-057 Figure 68. Cross-Section of 4-Layer PCB Showing Thermal Via Connection to Buried Ground Plane (Dimensions in Millimeters) Rev. E | Page 26 of 27

Data Sheet ADA4932-1/ADA4932-2 OUTLINE DIMENSIONS 3.10 0.30 3.00 SQ 0.23 PIN 1 2.90 0.18 INDICATOR PIN 1 0.50 13 16 INDICATOR BSC 12 1 EXPOSED 1.45 PAD 1.30 SQ 1.15 9 4 0.50 8 5 0.25 MIN TOP VIEW 0.40 BOTTOM VIEW 0.30 0.80 FOR PROPER CONNECTION OF 0.75 THE EXPOSED PAD, REFER TO 0.05 MAX THE PIN CONFIGURATION AND 0.70 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.08 PLANE 0.20 REF COMPLIANTTOJEDEC STANDARDS MO-220-WEED. 111808-A Figure 69. 16-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.75 mm Package Height (CP-16-21) Dimensions shown in millimeters 4.10 4.00 SQ PIN 1 3.90 INDICATOR PIN 1 0.50 19 24 INDICATOR BSC 18 1 2.40 EXPPAODSED 2.30 SQ 2.20 6 13 0.50 12 7 0.20 MIN TOP VIEW 0.40 BOTTOM VIEW 0.30 FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO 0.75 THE PIN CONFIGURATION AND 0.70 0.05 MAX FUNCTION DESCRIPTIONS 0.02 NOM SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.30 0.08 PLANE 0.25 0.203 REF 0.20COMPLIANTTOJEDEC STANDARDS MO-220-WGGD-8. 01-18-2012-A Figure 70. 24-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body and 0.75 mm Package Height (CP-24-14) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option Ordering Quantity Branding ADA4932-1YCPZ-R2 −40°C to +105°C 16-Lead LFCSP CP-16-21 250 H1K ADA4932-1YCPZ-RL −40°C to +105°C 16-Lead LFCSP CP-16-21 5,000 H1K ADA4932-1YCPZ-R7 −40°C to +105°C 16-Lead LFCSP CP-16-21 1,500 H1K ADA4932-2YCPZ-R2 −40°C to +105°C 24-Lead LFCSP CP-24-14 250 ADA4932-2YCPZ-RL −40°C to +105°C 24-Lead LFCSP CP-24-14 5,000 ADA4932-2YCPZ-R7 −40°C to +105°C 24-Lead LFCSP CP-24-14 1,500 1 Z = RoHS Compliant Part. ©2008–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07752-0-5/16(E) Rev. E | Page 27 of 27

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: ADA4932-1YCPZ-R7 ADA4932-1YCPZ-RL ADA4932-2YCPZ-R7 ADA4932-2YCPZ-RL ADA4932-2YCPZ-R2 ADA4932-1YCPZ-R2