1.8 V, Micropower, Zero-Drift, Rail-to-Rail Input/Output Op Amps Data Sheet ADA4051-1/ADA4051-2 FEATURES PIN CONFIGURATIONS Very low supply current: 13 μA typical Low offset voltage: 15 μV maximum OUT 1 ADA4051-1 5 V+ Offset voltage drift: 20 nV/°C V– 2 TOP VIEW (Not to Scale) SHiingghl eP-SsRuRp:p 1ly1 0o pdeBr matiinoinm: 1u.m8 V to 5.5 V +IN 3 4 –IN 08056-064 High CMRR: 110 dB minimum Figure 1. 5-Lead SOT-23 (RJ-5) Rail-to-rail input/output Unity-gain stable +IN 1 5 V+ ADA4051-1 Extended industrial temperature range V– 2 TOP VIEW (Not to Scale) APrPesPsLuIrCe AanTdIO pNosSit ion sensors –IN 3 4 OUT 08056-066 Figure 2. 5-Lead SC-70 (KS-5) Temperature measurements Electronic scales OUT A 1 8 V+ Medical instrumentation –IN A 2 ADA4051-2 7 OUT B BHaatntderhye-lpdo twesetr eedq ueiqpumipemnte nt +INV A– 34 (NToOt Pto V SIEcWale) 65 –+IINN BB 08056-001 Figure 3. 8-Lead MSOP (RM-8) OUT A1 8 V+ –IN A 2 ADA4051-2 7 OUT B TOP VIEW +IN A 3 (Not to Scale) 6–IN B V– 4 5+IN B N1.O IETTX EIPSSO RSEECDO PMAMDE BNED ECDO NTHNAECT TTEHDE TO V–. 08056-065 Figure 4. 8-Lead LFCSP (CP-8-13) GENERAL DESCRIPTION The ADA4051-1/ADA4051-2 are specified for the extended industrial temperature range of −40°C to +125°C. The ADA4051-1 The ADA4051-1/ADA4051-2 are CMOS, micropower, zero- amplifier is available in 5-lead SOT-23 and 5-lead SC-70 packages. drift operational amplifiers utilizing an innovative chopping The ADA4051-2 amplifier is available in an 8-lead MSOP and an technique. These amplifiers feature rail-to-rail input/output 8-lead LFCSP. swing and extremely low offset voltage while operating from a 1.8 V to 5.5 V power supply. In addition, these amplifiers offer The ADA4051-1/ADA4051-2 are members of a growing series high power supply rejection ratio (PSRR) and common-mode of zero-drift op amps offered by Analog Devices, Inc. Refer to rejection ratio (CMRR) while operating with a typical supply Table 1 for a list of these devices. current of 13 μA per amplifier. This combination of features Table 1. Op Amps makes the ADA4051-1/ADA4051-2 amplifiers ideal choices for Supply Low Power, 5 V 5 V 16 V battery-powered applications where high precision and low Single AD8538 AD8628 AD8638 power consumption are important. Dual AD8539 AD8629 AD8639 Quad AD8630 Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2009–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADA4051-1/ADA4051-2 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Thermal Resistance .......................................................................7 Applications ....................................................................................... 1 Power Sequencing .........................................................................7 Pin Configurations ........................................................................... 1 ESD Caution...................................................................................7 General Description ......................................................................... 1 Typical Performance Characteristics ..............................................8 Revision History ............................................................................... 2 Theory of Operation ...................................................................... 17 Specifications ..................................................................................... 3 Input Voltage Range ................................................................... 18 Electrical Characteristics—1.8 V Operation ............................ 3 Output Phase Reversal ............................................................... 18 Electrical Characteristics—5 V Operation................................ 5 Outline Dimensions ....................................................................... 19 Absolute Maximum Ratings ............................................................ 7 Ordering Guide .......................................................................... 20 REVISION HISTORY 3/16—Rev. B to Rev. C 10/09—Rev. 0 to Rev. A Changed CP-8-2 to CP-8-13 ........................................ Throughout Added ADA4051-1, 5-Lead SOT-23 Package ................. Universal Changes to Figure 4 .......................................................................... 1 Added ADA4051-2, 8-Lead LFCSP Package .................. Universal Changes to Offset Voltage Parameter and Input Resistance Changes to the Features and General Description Section, Parameter, Table 2 ............................................................................. 3 Added Figure 1 and Figure 3 ............................................................ 1 Changes to Offset Voltage Parameter and Input Resistance Moved Electrical Characteristics—1.8 V Operation Section ..... 3 Parameter, Table 3 ............................................................................. 5 Changes to Offset Voltage Parameter and Supply Current per Changes to Table 5 ............................................................................ 7 Amplifier Parameter, Table 2 ........................................................... 3 Updated Outline Dimensions ....................................................... 19 Moved Electrical Characteristics—5 V Operation Section ......... 4 Changes to Ordering Guide .......................................................... 20 Changes to Offset Voltage Parameter and Supply Current per Amplifier Parameter, Table 2 ........................................................... 4 1/10—Rev. A to Rev. B Changes to Thermal Resistance Section and Table 5 ................... 5 Added ADA4051-1, 5-Lead SC-70 Package .................... Universal Changes to Figure 22 and Figure 25................................................ 9 Added Figure 2; Renumbered Sequentially .................................. 1 Changes to Theory of Operation Section.................................... 15 Changes to Figure 4 and General Description Section ............... 1 Updated Outline Dimensions ....................................................... 17 Changes to Electrical Characteristics—1.8 V Operation Section Changes to Ordering Guide .......................................................... 18 and Table 2 ......................................................................................... 3 Changes to Electrical Characteristics—5 V Operation Section 7/09—Revision 0: Initial Version and Table 3 ......................................................................................... 4 Changes to Table 5 ............................................................................ 5 Updated Outline Dimensions ....................................................... 17 Changes to Ordering Guide .......................................................... 18 Rev. C | Page 2 of 22

Data Sheet ADA4051-1/ADA4051-2 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—1.8 V OPERATION V = 1.8 V, V = V /2 V, T = 25°C, R = 100 kΩ to GND, unless otherwise noted. SY CM SY A L Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage V OS ADA4051-2 0 V ≤ V ≤ 1.8 V 2 15 µV CM ADA4051-1 0 V ≤ V ≤ 1.8 V 2 17 µV CM −40°C ≤ T ≤ +125°C 27 µV A Offset Voltage Drift ∆V /∆T −40°C ≤ T ≤ +125°C 0.02 0.1 µV/°C OS A Input Bias Current I 5 50 pA B −40°C ≤ T ≤ +125°C 200 pA A Input Offset Current I 10 100 pA OS −40°C ≤ T ≤ +125°C 150 pA A Input Voltage Range −40°C ≤ T ≤ +125°C 0 1.8 V A Common-Mode Rejection Ratio CMRR 0 V ≤ V ≤ 1.8 V 105 125 dB CM −40°C ≤ T ≤ +125°C 100 dB A Large-Signal Voltage Gain A R = 10 kΩ to V , 106 130 dB VO L CM 0.1 V ≤ V ≤ V − 0.1 V OUT SY −40°C ≤ T ≤ +125°C 100 dB A Input Resistance Differential Mode R 8 MΩ INDM Common Mode R 250 GΩ INCM Input Capacitance, Differential Mode C 2 pF INDM Input Capacitance, Common Mode C 5 pF INCM OUTPUT CHARACTERISTICS Output Voltage High V R = 100 kΩ to V 1.796 1.799 V OH L CM −40°C ≤ T ≤ +125°C 1.79 V A R = 10 kΩ to V 1.76 1.796 V L CM −40°C ≤ T ≤ +125°C 1.7 V A Output Voltage Low V R = 100 kΩ to V 1 3 mV OL L CM −40°C ≤ T ≤ +125°C 9 mV A R = 10 kΩ to V 3 20 mV L CM −40°C ≤ T ≤ +125°C 40 mV A Short-Circuit Current I V = V or GND 13 mA SC OUT SY Closed-Loop Output Impedance Z f = 1 kHz, G = 10 1 Ω OUT POWER SUPPLY Power Supply Rejection Ratio PSRR 1.8 V ≤ V ≤ 5.5 V 110 135 dB SY −40°C ≤ T ≤ +125°C 106 dB A Supply Current per Amplifier I SY ADA4051-2 V = V /2 13 17 µA OUT SY ADA4051-1 V = V /2 15 18 µA OUT SY −40°C ≤ T ≤ +125°C 20 µA A DYNAMIC PERFORMANCE Slew Rate SR+ R = 10 kΩ, C = 100 pF, G = 1 0.04 V/µs L L SR− R = 10 kΩ, C = 100 pF, G = 1 0.03 V/µs L L Settling Time t To 0.1%, V = 1 V p-p, 120 µs S IN R = 10 kΩ, C = 100 pF L L Gain Bandwidth Product GBP C = 100 pF, G = 1 115 kHz L Phase Margin Φ C = 100 pF, G = 1 40 Degrees M L Channel Separation CS V = 1.7 V, f = 100 Hz 140 dB IN Rev. C | Page 3 of 22

ADA4051-1/ADA4051-2 Data Sheet Parameter Symbol Test Conditions/Comments Min Typ Max Unit NOISE PERFORMANCE Voltage Noise e p-p f = 0.1 Hz to 10 Hz 1.96 µV p-p n Voltage Noise Density e f = 1 kHz 95 nV/√Hz n Current Noise Density i f = 1 kHz 100 fA/√Hz n Rev. C | Page 4 of 22

Data Sheet ADA4051-1/ADA4051-2 ELECTRICAL CHARACTERISTICS—5 V OPERATION V = 5.0 V, V = V /2 V, T = 25°C, R = 100 kΩ to GND, unless otherwise noted. SY CM SY A L Table 3. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage V OS ADA4051-2 0 V ≤ V ≤ 5 V 2 15 µV CM ADA4051-1 0 V ≤ V ≤ 5 V 2 17 µV CM −40°C ≤ T ≤ +125°C 27 µV A Offset Voltage Drift ∆V /∆T −40°C ≤ T ≤ +125°C 0.02 0.1 µV/°C OS A Input Bias Current I 20 70 pA B −40°C ≤ T ≤ +125°C 200 pA A Input Offset Current I 40 100 pA OS −40°C ≤ T ≤ +125°C 150 pA A Input Voltage Range −40°C ≤ T ≤ +125°C 0 5 V A Common-Mode Rejection Ratio CMRR 0 V ≤ V ≤ 5 V 110 135 dB CM −40°C ≤ T ≤ +125°C 106 dB A Large-Signal Voltage Gain A R = 10 kΩ to V , 115 135 dB VO L CM 0.1 V ≤ V ≤ V − 0.1 V OUT SY −40°C ≤ T ≤ +125°C 106 dB A Input Resistance Differential Mode R 8 MΩ INDM Common Mode R 250 GΩ INCM Input Capacitance, Differential Mode C 2 pF INDM Input Capacitance, Common Mode C 5 pF INCM OUTPUT CHARACTERISTICS Output Voltage High V R = 100 kΩ to V 4.996 4.998 V OH L CM −40°C ≤ T ≤ +125°C 4.985 V A R = 10 kΩ to V 4.96 4.99 V L CM −40°C ≤ T ≤ +125°C 4.9 V A Output Voltage Low V R = 100 kΩ to V 1 4 mV OL L CM −40°C ≤ T ≤ +125°C 13 mV A R = 10 kΩ to V 9 30 mV L CM −40°C ≤ T ≤ +125°C 90 mV A Short-Circuit Current I V = V or GND 15 mA SC OUT SY Closed-Loop Output Impedance Z f = 1 kHz, G = 10 1 Ω OUT POWER SUPPLY Power Supply Rejection Ratio PSRR 1.8 V ≤ V ≤ 5.5 V 110 135 dB SY −40°C ≤ T ≤ +125°C 106 dB A Supply Current per Amplifier I SY ADA4051-2 V = V /2 13 17 µA OUT SY ADA4051-1 V = V /2 15 18 µA OUT SY −40°C ≤ T ≤ +125°C 20 µA A DYNAMIC PERFORMANCE Slew Rate SR+ R = 10 kΩ, C = 100 pF, G = 1 0.06 V/µs L L SR− R = 10 kΩ, C = 100 pF, G = 1 0.04 V/µs L L Settling Time t To 0.1%, V = 1 V p-p, 110 µs S IN R = 10 kΩ, C = 100 pF L L Gain Bandwidth Product GBP C = 100 pF, G = 1 125 kHz L Phase Margin Φ C = 100 pF, G = 1 40 Degrees M L Channel Separation CS V = 4.99 V, f = 100 Hz 140 dB IN Rev. C | Page 5 of 22

ADA4051-1/ADA4051-2 Data Sheet Parameter Symbol Test Conditions/Comments Min Typ Max Unit NOISE PERFORMANCE Voltage Noise e p-p f = 0.1 Hz to 10 Hz 1.96 µV p-p n Voltage Noise Density e f = 1 kHz 95 nV/√Hz n Current Noise Density i f = 1 kHz 100 fA/√Hz n Rev. C | Page 6 of 22

Data Sheet ADA4051-1/ADA4051-2 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. θ is specified for the worst-case conditions, that is, a device Parameter Rating JA soldered on a circuit board for surface-mount packages with its Supply Voltage 6 V exposed paddle soldered to a pad, if applicable. Table 5 shows Input Voltage ±V ± 0.3 V SY simulated thermal values for a 4-layer (2S2P) JEDEC standard Input Current1 ±10 mA thermal test board, unless otherwise specified. Differential Input Voltage2 ±V SY Output Short-Circuit Duration to GND Indefinite Table 5. Thermal Resistance Storage Temperature Range −65°C to +150°C Package Type θ Unit JA Operating Temperature Range −40°C to +125°C 5-Lead SOT-23 (RJ-5) 190 °C/W Junction Temperature Range −65°C to +150°C 5-Lead SC-70 (KS-5) 534 °C/W Lead Temperature (Soldering, 60 sec) 300°C 8-Lead MSOP (RM-8) 142 °C/W 8-Lead LFCSP (CP-8-13) 1 The input pins have clamp diodes to the power supply pins. Limit the input current to 10 mA or less whenever input signals exceed the power supply 1-Layer JEDEC Board 272 °C/W rail by 0.3 V. 2-Layer JEDEC Board 145 °C/W 2 Inputs are protected against high differential voltages by internal series 1.33 kΩ resistors and back-to-back diode-connected N-MOSFETs (with a 2-Layer JEDEC Board with 2 × 2 Vias 55 °C/W typical VT of 0.7 V for VCM of 0 V). POWER SEQUENCING Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a The op amp supplies must be established simultaneously with stress rating only; functional operation of the product at these or before any input signals are applied. If this is not possible, the or any other conditions above those indicated in the operational input current must be limited to 10 mA. section of this specification is not implied. Operation beyond ESD CAUTION the maximum operating conditions for extended periods may affect product reliability. Rev. C | Page 7 of 22

ADA4051-1/ADA4051-2 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, unless otherwise noted. A 300 300 VSY = 1.8V VSY = 5V VCM = VSY/2 VCM = VSY/2 250 250 S S R R FIE 200 FIE 200 LI LI P P M M FA 150 FA 150 O O R R E E MB 100 MB 100 U U N N 50 50 0 0 –10 –8 –6 –4 –2 VO0S (µV)2 4 6 8 10 08056-002 –10 –8 –6 –4 –2 VO0S (µV2) 4 6 8 10 08056-005 Figure 5. Input Offset Voltage Distribution Figure 8. Input Offset Voltage Distribution 10 8 VSY = 1.8V VSY = 5V –40°C ≤ TA ≤ +125°C –40°C ≤ TA ≤ 125°C 8 S S 6 R R E E FI FI PLI 6 PLI M M FA FA 4 O O ER 4 ER B B M M U U N N 2 2 0 0 0 0.01 0.02 0.03 0.T0C4VO0S.0 (5µV/0°.C0)6 0.07 0.08 0.09 0.10 08056-003 0 0.01 0.02 0.03 0.T0C4VO0S.0 (5µV/0°.C0)6 0.07 0.08 0.09 0.10 08056-006 Figure 6. Input Offset Voltage Drift Distribution with Temperature Figure 9. Input Offset Voltage Drift Distribution with Temperature 15 15 VSY = 1.8V VSY = 5V 10 10 5 5 V) V) µ µ (S 0 (S 0 O O V V DEVICE 1 DEVICE 1 –5 DEVICE 2 –5 DEVICE 2 DEVICE 3 DEVICE 3 DEVICE 4 DEVICE 4 DEVICE 5 DEVICE 5 –10 DDEEVVIICCEE 67 –10 DDEEVVIICCEE 76 DEVICE 8 DEVICE 8 DEVICE 9 DEVICE 9 DEVICE 10 DEVICE 10 –15 –15 0 0.3 0.6 VC0M.9 (V) 1.2 1.5 1.8 08056-004 0 1 2 VCM (V) 3 4 5 08056-007 Figure 7. Input Offset Voltage vs. Input Common-Mode Voltage Figure 10. Input Offset Voltage vs. Input Common-Mode Voltage Rev. C | Page 8 of 22

Data Sheet ADA4051-1/ADA4051-2 T = 25°C, unless otherwise noted. A 100 100 VSY = 1.8V IB+ VSY = 5V IB+ 80 IB– 80 IB– 60 60 A) A) (pB 40 (pB 40 I I 20 20 0 0 –20 –20 25 50 TEMPERA75TURE (°C) 100 125 08056-008 25 50 TEMPERA75TURE (°C) 100 125 08056-011 Figure 11. Input Bias Current vs. Temperature Figure 14. Input Bias Current vs. Temperature 200 400 VSY = 1.8V VSY = 5V 150 300 100 200 50 100 A) A) I (pB 0 I (pB 0 –50 –100 –100 IIBB+–,, 2255°°CC –200 IIBB+–,, 2255°°CC IB+, 85°C IB+, 85°C –150 IIBB–+,, 8152°5C°C –300 IIBB–+,, 8152°5C°C IB–, 125°C IB–, 125°C –200 –400 0 0.3 0.6 VC0M.9 (V) 1.2 1.5 1.8 08056-009 0 0.5 1.0 1.5 2.0VC2M. 5(V) 3.0 3.5 4.0 4.5 5.0 08056-012 Figure 12. Input Bias Current vs. Common-Mode Voltage and Temperature Figure 15. Input Bias Current vs. Common-Mode Voltage and Temperature 10,000 10,000 mV) VSY = 1.8V mV) VSY = 5V L ( L ( AI 1000 AI 1000 R R Y Y L L P P UP 100 UP 100 S S O O T T )H 10 ) H 10 O O V V E ( E ( AG 1 AG 1 OLT OLT UTPUT V 0.1 –++428055°°°CCC UTPUT V 0.1 –++428055°°°CCC O +125°C O +125°C 0.01 0.01 0.001 0.01 LOAD CUR0.R1ENT (mA) 1 10 08056-010 0.001 0.01 LOA0D.1 CURRENT 1(mA) 10 100 08056-013 Figure 13. Output Voltage (VOH) to Supply Rail vs. Load Current Figure 16. Output Voltage (VOH) to Supply Rail vs. Load Current and Temperature and Temperature Rev. C | Page 9 of 22

ADA4051-1/ADA4051-2 Data Sheet T = 25°C, unless otherwise noted. A 10,000 10,000 mV) VSY = 1.8V mV) VSY= 5V L ( L ( AI 1000 AI1000 R R Y Y L L P P UP 100 UP 100 S S O O T T ) OL 10 )OL 10 V V E ( E ( AG 1 AG 1 OLT OLT OUTPUT V 0.1 ++–+42810552°°°5CCC°C OUTPUT V 0.1 –+++42810552°5°°CCC°C 0.01 0.01 0.001 0.01 LOA0D.1 CURRENT 1(mA) 10 100 08056-014 0.001 0.01 LOA0D.1 CURRENT 1(mA) 10 100 08056-017 Figure 17. Output Voltage (VOL) to Supply Rail vs. Load Current Figure 20. Output Voltage (VOL) to Supply Rail vs. Load Current and Temperature and Temperature 1800 5000 RL = 100kΩ 4998 RL = 100kΩ 1799 V) V)4996 m m ] (H1798 ] (H4994 O O V V E [ E [4992 G G A1797 A OLT RL = 10kΩ OLT4990 RL = 10kΩ V V T T U1796 U4988 P P T T U U O O4986 1795 VSY = 1.8V 4984 VSY = 5V VCM = VSY/2 VCM = VSY/2 1794 4982 –40 –25 –10 5 T2E0MPE35RATU50RE (°6C5) 80 95 110 125 08056-015 –40 –25 –10 5 T2E0MPE35RATU50RE (°6C5) 80 95 110 125 08056-018 Figure 18. Output Voltage (VOH) vs. Temperature Figure 21. Output Voltage (VOH) vs. Temperature 14 14 VVSCYM == 1V.S8YV/2 VVSCYM == 5VVSY/2 12 12 V) V) m m ] (L 10 ] (L 10 O O E [V 8 E [V 8 RL = 10kΩ G G A A T T L L O 6 O 6 V V T T U U TP 4 TP 4 OU RL = 10kΩ OU 2 2 RL = 100kΩ RL = 100kΩ 0 0 –40 –25 –10 5 T2E0MPE35RATU50RE (°6C5) 80 95 110 125 08056-016 –40 –25 –10 5 T2E0MPE35RATU50RE (°6C5) 80 95 110 125 08056-019 Figure 19. Output Voltage (VOL) vs. Temperature Figure 22. Output Voltage (VOL) vs. Temperature Rev. C | Page 10 of 22

Data Sheet ADA4051-1/ADA4051-2 T = 25°C, unless otherwise noted. A 30 30 ADA4051-2 VCM = VSY/2 ADA4051-1 25 25 A) A) µ µ T ( T ( N 20 N 20 E E R R R R U U C C Y 15 Y 15 L L P P P P U U L S 10 L S 10 A A T T ADA4051-2, 1.8V O O T T ADA4051-2, 5V 5 5 ADA4051-1, 1.8V VCM = VSY/2 ADA4051-1, 5V 0 0 0 0.5 1.0 1.5SUP2P.0LY V2O.5LTAG3.E0 (V)3.5 4.0 4.5 5.0 08056-020 –40 –25 –10 5 T2E0MPE35RATU5R0E (°6C5) 80 95 110 125 08056-023 Figure 23. Total Supply Current vs. Supply Voltage Figure 26. Total Supply Current vs. Temperature 80 180 80 180 VSY = 1.8V VSY = 5V CL= 100pF CL= 100pF 60 135 60 135 B) 40 90 B) 40 90 N-LOOP GAIN (d 200 GAIN PHASE 045 HASE (Degrees) N-LOOP GAIN (d 200 GAIN PHASE 405 HASE (Degrees) E P E P P P O –20 –45 O –20 –45 –40 –90 –40 –90 –60 –135 –60 –135 100 1k FREQ1U0kENCY (Hz) 100k 1M 08056-022 100 1k FREQ1U0kENCY (Hz) 100k 1M 08056-025 Figure 24. Open-Loop Gain and Phase vs. Frequency Figure 27. Open-Loop Gain and Phase vs. Frequency 50 50 40 VRCSLLY == = 15 001kp.8ΩFV 40 RVCSLLY == = 15 005kpVΩF 30 30 B) B) N (d 20 N (d 20 GAI 10 GAI 10 OOP 0 OOP 0 CLOSED-L ––2100 CLOSED-L ––2100 –30 –30 –40 GG == 110 –40 GG == 110 G = 100 G = 100 –50100 1k FREQ1U0kENCY (Hz) 100k 1M 08056-061 –50100 1k FREQ1U0kENCY (Hz) 100k 1M 08056-062 Figure 25. Closed-Loop Gain vs. Frequency Figure 28. Closed-Loop Gain vs. Frequency Rev. C | Page 11 of 22

ADA4051-1/ADA4051-2 Data Sheet T = 25°C, unless otherwise noted. A 10k 10k VSY = 1.8V VSY = 5V 1k 1k 100 100 Ω) Ω) (UT (UT O O Z Z 10 10 1 1 G = −1 G = −1 G = −10 G = −10 G = −100 G = −100 0.1 0.1 1k 10kFREQUENCY (Hz)100k 1M 08056-026 1k 10kFREQUENCY (Hz)100k 1M 08056-029 Figure 29. Output Impedance vs. Frequency Figure 32. Output Impedance vs. Frequency 110 110 VSY = 1.8V VSY = 5V 100 100 90 90 dB) 80 dB) 80 R ( R ( R R M 70 M 70 C C 60 60 50 50 40 40 10 100 FR1kEQUENCY 1(H0kz) 100k 1M 08056-027 10 100 FR1kEQUENCY 1(H0kz) 100k 1M 08056-030 Figure 30. CMRR vs. Frequency Figure 33. CMRR vs. Frequency 120 120 VSY = 1.8V VSY = 5V 100 100 80 80 B) B) d d R ( 60 R ( 60 R R S PSRR+ S PSRR+ P P 40 40 20 20 PSRR– PSRR– 0 0 100 1k FREQU1E0NkCY (Hz) 100k 1M 08056-028 100 1k FREQU1E0NkCY (Hz) 100k 1M 08056-031 Figure 31. PSRR vs. Frequency Figure 34. PSRR vs. Frequency Rev. C | Page 12 of 22

Data Sheet ADA4051-1/ADA4051-2 T = 25°C, unless otherwise noted. A 60 60 50 VVRCSILLNY = = = = 5 10 50±p0k0mF.Ω9VV p-p 50 VCVRSILLNY = = = = 5 10 50±p0k2mF.Ω5VV p-p %) 40 %) 40 T ( T ( O O −OVERSHOOT HO 30 HO 30 S S R R E E V V O 20 O 20 −OVERSHOOT +OVERSHOOT +OVERSHOOT 10 10 0 0 10 LOAD CAPACITANCE (1p0F0) 08056-032 10 LOAD CAPACITANCE (1p0F0) 08056-035 Figure 35. Small-Signal Overshoot vs. Load Capacitance Figure 38. Small-Signal Overshoot vs. Load Capacitance VSY = 1.8V VSY = 5V RL = 10kΩ RL = 10kΩ CL = 100pF CL = 100pF G = 1 G = 1 VIN = 1.5V p-p VIN = 4V p-p V) DI V) V/ DI m V/ GE (500 AGE (1 OLTA VOLT V TIME (100µs/DIV) 08056-033 TIME (100µs/DIV) 08056-036 Figure 36. Large-Signal Transient Response Figure 39. Large-Signal Transient Response VSY = 1.8V VSY = 5V RL = 10kΩ RL = 10kΩ CL = 100pF CL = 100pF G = 1 G = 1 VIN = 50mV p-p VIN = 50mV p-p V) V) DI DI V/ V/ m m 0 0 1 1 E ( E ( G G A A T T L L O O V V TIME (100µs/DIV) 08056-034 TIME (100µs/DIV) 08056-037 Figure 37. Small-Signal Transient Response Figure 40. Small-Signal Transient Response Rev. C | Page 13 of 22

ADA4051-1/ADA4051-2 Data Sheet T = 25°C, unless otherwise noted. A VSY = 1.8V VSY = 5V V) V) DI DI E (0.5µV/ 1.94µV p-p E (0.5µV/ 1.96µV p-p S S OI OI N N E E G G A A T T L L O O V V UT UT P P N N I I TIME (4s/DIV) 08056-038 TIME (4s/DIV) 08056-041 Figure 41. Input Voltage Noise, 0.1 Hz to 10 Hz Figure 44. Input Voltage Noise, 0.1 Hz to 10 Hz 1k 1k VSY = 1.8V VSY = 5V Hz) Hz) √ √ V/ V/ n n Y ( 100 Y ( 100 T T SI SI N N E E D D E E S S OI OI N N E 10 E 10 G G A A T T L L O O V V 1 1 10 100FREQUENCY (Hz)1k 10k 08056-039 10 100FREQUENCY (Hz)1k 10k 08056-042 Figure 42. Voltage Noise Density vs. Frequency Figure 45. Voltage Noise Density vs. Frequency 0.15 0.4 VSY = ±0.9V VSY = ±2.5V G = –10 G = –10 0.10 0.3 V) INPUT VOLTAGE (50mV/DIV)–00..00550 OIUNTPPUUTT V VOOLLTTAAGGEE 00–.05.5 OUTPUT VOLTAGE (500mV/DI INPUT VOLTAGE (100mV/DIV) –000...1210 OIUNTPPUUTT V VOOLLTTAAGGEE 01–1 OUTPUT VOLTAGE (1V/DIV) –1.0 –2 TIME (40µs/DIV) –1.5 08056-040 TIME (40µs/DIV) –3 08056-043 Figure 43. Positive Overload Recovery Figure 46. Positive Overload Recovery Rev. C | Page 14 of 22

Data Sheet ADA4051-1/ADA4051-2 T = 25°C, unless otherwise noted. A 0.05 0.1 INPUT VOLTAGE 0 0 INPUT VOLTAGE INPUT VOLTAGE (50mV/DIV)–––000...101550 101...550 OUTPUT VOLTAGE (500mV/DIV) INPUT VOLTAGE (100mV/DIV) ––––0000....1234 3412 OUTPUT VOLTAGE (1V/DIV) OUTPUT VOLTAGE OUTPUT VOLTAGE 0 0 VGS =Y –=1 ±00.9V TIME (40µs/DIV) –0.5 08056-044 GVS =Y –=1 ±02.5V TIME (40µs/DIV) –1 08056-047 Figure 47. Negative Overload Recovery Figure 50. Negative Overload Recovery INPUT VOLTAGE INPUT VOLTAGE V) V) V) V) DI DI DI DI V/ V/ V/ V/ m m m m 0 5 0 5 50 E ( 50 E ( AGE ( 5 LTAG AGE ( 5 LTAG INPUT VOLT EBRARNODR OUTPUTV SVYO =L ±T0A.G9VE –05 OUTPUT VO INPUT VOLT EBRARNODR OUTPUTV SVYO =L ±T2A.G5VE –05 OUTPUT VO VIN = 1Vp-p VIN = 1Vp-p RL = 10kΩ RL = 10kΩ TIME (40µs/DIV) CL = 100pF 08056-045 TIME (40µs/DIV) CL = 100pF 08056-048 Figure 48. Positive Settling Time to 0.1% Figure 51. Positive Settling Time to 0.1% V) V) V) V) DI DI DI DI mV/ INPUT VOLTAGE mV/ mV/ INPUT VOLTAGE mV/ INPUT VOLTAGE (500 EBRARNODR OUTPUTV VSOYL =T ±A0G.9EV –505 OUTPUT VOLTAGE (5 INPUT VOLTAGE (500 EBRARNODR OUTPUTV SVYO =L T±A2.G5VE –505 OUTPUT VOLTAGE (5 VIN = 1Vp-p VIN = 1Vp-p TIME (40µs/DIV) RCLL == 1100k0ΩpF 08056-046 TIME (40µs/DIV) CRLL == 1100k0ΩpF 08056-049 Figure 49. Negative Settling Time to 0.1% Figure 52. Negative Settling Time to 0.1% Rev. C | Page 15 of 22

ADA4051-1/ADA4051-2 Data Sheet T = 25°C, unless otherwise noted. A –100 –100 100kΩ 1kΩ VVVIIINNN === 011.V.57VV 100kΩ 1kΩ VVVIIINNN === 134VV.99V –110 –110 B) B) d d N ( N ( O O ATI–120 ATI–120 R R A A P P E E S S L –130 L –130 E E N N N N A A H H C–140 VGS =Y –=1 10.08V C–140 GVS =Y –=1 50V0 CRLL== 1500kpΩF CRLL= = 1 500kpΩF –150 –150 20 200 FREQUENC2kY (Hz) 20k 08056-050 20 200 FREQUEN2CkY (Hz) 20k 08056-053 Figure 53. Channel Separation vs. Frequency Figure 56. Channel Separation vs. Frequency 1.8 6 1.5 5 V) 1.2 V) 4 G ( G ( N N WI WI S 0.9 S 3 T T U U P P T T OU 0.6 OU 2 0.3 VVGSI N=Y =1= 11..78VV 1 VVGSI N=Y =1= 45.V9V CRLL= = 1 500kpΩF RCLL= = 1 500kpΩF 0 0 100 1k FREQUENCY 1(H0zk) 100k 08056-051 100 1k FREQUENCY (1H0zk) 100k 08056-054 Figure 54. Output Swing vs. Frequency Figure 57. Output Swing vs. Frequency VSY = ±0.9V VSY = ±2.5V G = 1 G = 1 RL= NO LOAD RL= NO LOAD CL = NO LOAD CL = NO LOAD V) DI V) V/ DI m V/ GE (500 AGE (1 VOLTA VOUT VOLT VOUT VIN VIN TIME (200µs/DIV) 08056-052 TIME (200µs/DIV) 08056-055 Figure 55. No Phase Reversal Figure 58. No Phase Reversal Rev. C | Page 16 of 22

Data Sheet ADA4051-1/ADA4051-2 THEORY OF OPERATION The ADA4051-1/ADA4051-2 micropower chopper operational pole-zero doublets. This design prevents any instability introduced amplifiers feature a novel, patent-pending technique that sup- by the ACFB in the overall feedback loop. presses offset-related ripple in a chopper amplifier. Instead of filtering the ripple in the ac domain, this technique nulls the CHOP1 Gm1 CHOP2 Gm2 C2 initial offset of the amplifier in the dc domain, thus preventing +IN Gm3 OUT ripple at the overall output. –IN Auto-zeroing and chopping are two techniques widely used in C1 high precision CMOS amplifiers to achieve low offset, low offset C3 drift, and no 1/f noise. Each of these techniques has pros and cons. Auto-zeroing results in more in-band noise due to aliasing Gm5 NF CHOP3 Gm4 introduced by sampling. On the other hand, chopping produces Gm6 (= Gm1) oasfsfsoecti-arteeldat wedit rhi pthpele a bmepcaliufiseer iut pm tood iutsla ctheso pthpei ning iftriaelq oufefnsecty . 08056-060 Figure 59. ADA4051-1/ADA4051-2 Chopper Amplifiers Block Diagram To accomplish the best noise vs. power trade-off, the chopping The voltage noise density, which is equal to the thermal noise technique is the better approach when designing a low offset floor dominated by the Gm1, is essentially flat from dc to the amplifier because there is no increased in-band noise. It is chopping frequency because CHOP1 and CHOP2 eliminate the preferable to suppress the offset-related ripple inside a chopper 1/f noise generated in Gm1 and the ACFB does not contribute amplifier because the offset-related ripple would otherwise need any additional noise. Although the ACFB suppresses the ripple to be eliminated by an extra off-chip postfilter. related to the chopping, there is a remaining voltage ripple. To Figure 59 shows the block diagram design of the ADA4051-1/ further suppress the remaining ripple down to a desired level, it ADA4051-2 chopper amplifiers employing a local feedback loop is recommended to have a postfilter at the output of the amplifier. called autocorrection feedback (ACFB). The main signal path The remaining voltage ripple originates from two sources. The contains an input chopping switch network (CHOP1), a first first type of ripple is due to the residual ripple associated with transconductance amplifier (Gm1), an output chopping switch the initial offset of the Gm1. It is proportional to the magnitude network (CHOP2), a second transconductance amplifier (Gm2), of the initial offset and creates a spectrum at the chopping and a third transconductance amplifier (Gm3). CHOP1 and frequency (f ). When the amplifier is configured as a unity- CHOP CHOP2 operate at 40 kHz of chopping frequency to modulate gain buffer, this ripple has a typical value of 4.9 μV rms and a the initial offset and 1/f noise from Gm1 up to the chopping maximum of 34.7 μV rms. The second type of ripple is due to frequency. A fourth transconductance amplifier (Gm4) in the the intermodulation between the high frequency input signal ACFB senses the modulated ripple at the output of CHOP2, and the chopping frequency. This ripple depends on the input caused by the initial offset voltage of Gm1. Then, the ripple is frequency (f ) and creates a spectrum at frequencies equal to IN demodulated down to a dc domain through a third chopping the difference between the chopping frequency and the input switch network (CHOP3), operating with the same chopping frequency (f − f ), as well as at frequencies equal to the CHOP IN clock as CHOP1 and CHOP2. Finally, a null transconductance summation of the chopping frequency and the input frequency amplifier (Gm5) tries to null any dc component at the output of (f + f ). The magnitude of the ripple for different input CHOP IN Gm1 that would otherwise appear in the overall output as ripple. frequencies is shown in Figure 60. A switched-capacitor notch filter (NF) functions to selectively 500 suppress the undesired offset-related ripple without disturbing the desired input signal from the overall input. The desired input ms) dc signal appears as a dc signal at the output of CHOP2. Then, V r 400 µ the initial offset is modulated up to the chopping frequency by LE ( P CHOP3 and filtered out by the NF. Therefore, initial offset does RIP 300 not create any feedback and does not disturb the desired input UT P signal. The NF is synchronized with the chopping clock to filter UT O 200 out the modulated component. In the same manner, the offset D E T of Gm5 is filtered out by the combination of CHOP3 and the A L NF, enabling accurate ripple sensing at the output of CHOP2. DU 100 O M In parallel with the high dc gain path, a feedforward transcon- dinutcrotadnuccee adm bpyl tifhiee rA (CGFmB6 a) ti sth aed cdheodp tpoi nbygp faressq utheen cpyh. aGsem s6h iifst 00 1 2 3INPUT4 FREQ5UENC6Y (kHz7) 8 9 10 08056-063 designed to have the same transconductance as Gm1 to avoid Figure 60. ADA4051-1/ADA4051-2 Modulated Output Ripple vs. Input Frequency Rev. C | Page 17 of 22

ADA4051-1/ADA4051-2 Data Sheet The design architecture of the ADA4051-1/ADA4051-2 The ADA4051-1/ADA4051-2 also have internal circuitry that specifically targets precision signal conditioning applications protects the input stage from high differential voltages. This requiring accurate and stable performance from dc to 10 Hz circuitry is composed of internal 1.33 kΩ resistors in series with bandwidth. In summary, the main features of the ADA4051-1/ each input and back-to-back diode-connected N-MOSFET (with a ADA4051-2 chopper amplifiers are typical V of 0.7 V for a V of 0 V) after these series resistors. With T CM normal negative feedback operating conditions, the ADA4051-1/ • Considerable suppression of the offset-related ripple ADA4051-2 amplifiers correct their output to ensure that the two • No effect on the desired input signal as long as its inputs are at the same voltage. However, if the device is configured frequency is much lower than the chopping frequency as a comparator or there are unusual operating conditions, the shown in Figure 60 input voltages can be forced to different potentials, which may • Achievement of low offset similar to a conventional cause excessive current to flow through the internal diode- chopper amplifier connected N-MOSFETs. • No introduction of excess noise Although the ADA4051-1/ADA4051-2 are rail-to-rail input The ADA4051-1/ADA4051-2 chopper amplifiers provide a rail- amplifiers, take care to ensure that the potential difference to-rail input range with a 1.8 V to 5.5 V supply voltage range and between the inputs does not exceed ±V to avert permanent SY 20 µA supply current consumption over the −40°C to +125°C damage to the device. extended industrial temperature range. The gain bandwidth is OUTPUT PHASE REVERSAL 125 kHz as a unity-gain stable amplifier up to 100 pF load capacitance. Although output phase reversal can occur with other amplifiers when the input common-mode voltage range is exceeded, the INPUT VOLTAGE RANGE ADA4051-1/ADA4051-2 amplifiers are designed to prevent The ADA4051-1/ADA4051-2 have internal ESD protection any output phase reversal, provided both inputs are maintained diodes. These diodes are connected between the inputs and each approximately within 0.3 V above and below the supply voltages supply rail to protect the input MOSFETs from an electrical (±V ± 0.3 V). SY discharge event and are reversed-biased during normal operation. With other amplifiers, the outputs may jump in the opposite This protection scheme allows voltages as high as approximately direction to the supply rail when a common-mode voltage 0.3 V beyond the supplies (±V ± 0.3 V) to be applied at the SY moves outside the common-mode range. This usually occurs input of either terminal without causing permanent damage. when one of the internal stages of the amplifier no longer has If either input exceeds one of the supply rails by more than 0.3 V, sufficient bias voltage across it and subsequently turns off. these ESD diodes become forward-biased and large amounts of However, with the ADA4051-1/ADA4051-2 amplifiers, if one current begin to flow through them. Without current limiting, this or both inputs exceed the input voltage range but remain within excessive current would cause permanent damage to the device. the ±V ± 0.3 V range, an internal loop opens and the output If the inputs are expected to be subject to overvoltage conditions, SY remains in saturation mode, without phase reversal, until the install a resistor in series with each input to limit the input current input voltage is brought back to within the input voltage range to 10 mA maximum. limits as shown in Figure 55 and Figure 58. Rev. C | Page 18 of 22

Data Sheet ADA4051-1/ADA4051-2 OUTLINE DIMENSIONS 3.00 2.90 2.80 1.70 5 4 3.00 1.60 2.80 1.50 2.60 1 2 3 0.95BSC 1.90 BSC 1.30 1.15 0.90 1.45MAX 0.20MAX 0.95MIN 0.08MIN 0.55 0.15MAX 10° 0.45 0.05MIN 0.50MAX SPELAATNIENG 5° B0S.6C0 0.35 0.35MIN 0° COMPLIANTTOJEDECSTANDARDSMO-178-AA 11-01-2010-A Figure 61. 5-Lead Small Outline Transistor Package [SOT-23] (RJ-5) Dimensions shown in millimeters 2.20 2.00 1.80 1.35 5 4 2.40 1.25 2.10 1.15 1 2 3 1.80 0.65BSC 1.00 1.10 0.40 0.90 0.80 0.10 0.70 0.46 0.10MAX 0.30 SPELAATNIENG 00..0282 0.36 COPLANARITY 0.15 0.26 0.10 COMPLIANTTOJEDECSTANDARDSMO-203-AA 072809-A Figure 62. 5-Lead Thin Shrink Small Outline Transistor Package [SC-70] (KS-5) Dimensions shown in millimeters Rev. C | Page 19 of 22

ADA4051-1/ADA4051-2 Data Sheet 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 2.80 1 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.80 CO00P..10L550A.1N0ARICTOYMPLIANT00.. 42T05O JEDEC STA60°°NDARDS 00M..20O39-187-AA 00..5450 10-07-2009-B Figure 63. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 1.84 3.10 1.74 3.00SQ 2.90 1.64 0.50BSC 5 8 PIN1INDEX EXPOSED 1.55 AREA PAD 1.45 0.50 1.35 0.40 0.30 4 1 PIN1 TOPVIEW BOTTOMVIEW INDICATOR (R0.15) 0.80 FORPROPERCONNECTIONOF 0.75 0.05MAX TTHHEEEPXINPCOOSNEDFIGPAUDR,ARTEIOFNERANTOD 0.70 0.02NOM FUNCTIONDESCRIPTIONS COPLANARITY SECTIONOFTHISDATASHEET. SEATING 0.30 0.08 PLANE 00..C22O50MPLIANTTOJEDEC0.2S0T3ARNEDFARDSMO-229-WEED 12-07-2010-A Figure 64. 8-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.75 mm Package Height (CP-8-13) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option Branding ADA4051-1ARJZ-R2 −40°C to +125°C 5-Lead Small Outline Transistor Package [SOT-23] RJ-5 A0U ADA4051-1ARJZ-R7 −40°C to +125°C 5-Lead Small Outline Transistor Package [SOT-23] RJ-5 A0U ADA4051-1ARJZ-RL −40°C to +125°C 5-Lead Small Outline Transistor Package [SOT-23] RJ-5 A0U ADA4051-1AKSZ-R2 −40°C to +125°C 5-Lead Thin Shrink Small Outline Transistor Package [SC-70] KS-5 A0U ADA4051-1AKSZ-R7 −40°C to +125°C 5-Lead Thin Shrink Small Outline Transistor Package [SC-70] KS-5 A0U ADA4051-1AKSZ-RL −40°C to +125°C 5-Lead Thin Shrink Small Outline Transistor Package [SC-70] KS-5 A0U ADA4051-2ACPZ-R2 −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-13 A2M ADA4051-2ACPZ-R7 −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-13 A2M ADA4051-2ACPZ-RL −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-13 A2M ADA4051-2ARMZ −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A2M ADA4051-2ARMZ-R7 −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A2M ADA4051-2ARMZ-RL −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A2M 1 Z = RoHS Compliant Part. Rev. C | Page 20 of 22

Data Sheet ADA4051-1/ADA4051-2 NOTES Rev. C | Page 21 of 22

ADA4051-1/ADA4051-2 Data Sheet NOTES ©2009–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08056-0-3/16(C) Rev. C | Page 22 of 22

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: ADA4051-1ARJZ-R2 ADA4051-2ARMZ ADA4051-1AKSZ-R2 ADA4051-1AKSZ-R7 ADA4051-1AKSZ-RL ADA4051-1ARJZ-R7 ADA4051-1ARJZ-RL ADA4051-2ACPZ-R2 ADA4051-2ACPZ-R7 ADA4051-2ACPZ-RL ADA4051-2ARMZ-R7 ADA4051-2ARMZ-RL