Quad 7 ns Single Supply Comparator AD8564 FEATURES PIN CONFIGURATIONS 5 V single-supply operation –IN A 1 16 –IN D 7 ns propagation delay +IN A +IN D Low power GND V+ANA OUT A AD8564 OUT D Separate input and output sections OUT B OUT C V–ANA V+DIG TWTiLd/eC oMuOtpSu lot gswici-ncgo mpatible outputs +–IINN BB 8 9 +–IINN CC 01103-003 TSSOP, SOIC, and PDIP packages Figure 1. 16-Lead TSSOP (RU-16) APPLICATIONS –IN A –IN D High speed timing +IN A +IN D Line receivers GND V+ANA OUT A OUT D Data communications OUT B OUT C High speed V-to-F converters V–ANA V+DIG Battery operated instrumentation +IN B +IN C HWiignhd ospwe ceodm sapmarpaltionrgs systems –IN B AD8564 –IN C 01103-001 Figure 2. 16-Lead Narrow Body SOIC PCMCIA cards (R-16) Upgrade for MAX901 designs –IN A 1 16 –IN D +IN A 2 15 +IN D + – – + GND 3 14 V+ANA OUT A 4 13 OUT D AD8564 OUT B 5 12 OUT C V–ANA 6 11 V+DIG + – – + +IN B 7 10 +IN C –IN B 8 9 –IN C 01103-002 Figure 3. 16-Lead PDIP (N-16) GENERAL DESCRIPTION The AD8564 is a quad 7 ns comparator with separate input and All four comparators have similar propagation delays. The output supplies, thus enabling the input stage to be operated propagation delay for rising and falling signals is similar, and from ±5 V dual supplies or a 5 V single supply while maintaining a tracks over temperature and voltage. These characteristics make CMOS-/TTL-compatible output. the AD8564 a good choice for high speed timing and data communications circuits. For a similar single comparator with Fast 7 ns propagation delay makes the AD8564 a good choice latch function, refer to the AD8561 data sheet. for timing circuits and line receivers. Independent analog and digital supplies provide excellent protection from supply pin The AD8564 is specified over the industrial temperature range interaction. The AD8564 is pin compatible with the MAX901 (−40°C to +125°C). The quad AD8564 is available in the 16-lead and has lower supply currents. TSSOP, 16-lead narrow body SOIC, and 16-lead plastic DIP packages. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©1999–2007 Analog Devices, Inc. All rights reserved.

AD8564 TABLE OF CONTENTS Features..............................................................................................1 ESD Caution...................................................................................5 Applications.......................................................................................1 Typical Performance Characteristics..............................................6 Pin Configurations...........................................................................1 Applications Information.................................................................9 General Description.........................................................................1 Optimizing High Speed Performance........................................9 Revision History...............................................................................2 Output Loading Considerations..................................................9 Specifications.....................................................................................3 Input Stage and Bias Currents.....................................................9 Electrical Specifications...............................................................3 Using Hysteresis.........................................................................10 Absolute Maximum Ratings............................................................5 Outline Dimensions.......................................................................11 Thermal Resistance......................................................................5 Ordering Guide..........................................................................12 REVISION HISTORY 8/07—Rev. A to Rev. B Updated Format..................................................................Universal Changes to Applications..................................................................1 Changes to General Description....................................................1 Changes to Specifications................................................................3 Changes to the Absolute Maximum Ratings Section..................5 Changes to the Applications Information Section.......................9 Deleted Spice Model Section.........................................................11 Updated Outline Dimensions.......................................................12 Changes to Ordering Guide..........................................................13 6/99—Rev. 0 to Rev. A Rev. B | Page 2 of 12

AD8564 SPECIFICATIONS ELECTRICAL SPECIFICATIONS V = V = 5.0 V, V = 0 V, T = 25°C, unless otherwise noted. +ANA +DIG −ANA A Table 1. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage V 2.3 7 mV OS −40°C ≤ T ≤ +125°C1 8 mV A Offset Voltage Drift ΔV /ΔT 4 μV/°C OS Input Bias Current I V = 0 V ±4 μA B CM −40°C ≤ T ≤ +125°C1 ±9 μA A Input Offset Current I V = 0 V ±3 μA OS CM Input Common-Mode Voltage Range V 0 2.75 V CM Common-Mode Rejection Ratio CMRR 0 V ≤ V ≤ 3.0 V 65 85 dB CM Large Signal Voltage Gain A R = 10 kΩ 3000 V/V VO L Input Capacitance C 3.0 pF IN DIGITAL OUTPUTS Logic 1 Voltage V I = −3.2 mA, ΔV > 250 mV 2.4 3.5 V OH OH IN Logic 0 Voltage V I = 3.2 mA, V > 250 mV 0.3 0.4 V OL OL IN DYNAMIC PERFORMANCE2 Propagation Delay t 200 mV step with 100 mV overdrive 6.75 9.8 ns P −40°C ≤ T ≤ +125°C1 13 ns A 100 mV step with 5 mV overdrive 8 ns Differential Propagation Delay (Rising Propagation Delay vs. Δt 100 mV step with 20 mV overdrive 0.5 2.0 ns P Falling Propagation Delay) Rise Time 20% to 80% 3.8 ns Fall Time 20% to 80% 1.5 ns POWER SUPPLY Power Supply Rejection Ratio PSRR 4.5 V ≤ V and V ≤ 5.5 V 80 dB +ANA +DIG Analog Supply Current I 10.5 14.0 mA +ANA −40°C ≤ T ≤ +85°C1 15.6 mA A −40°C ≤ T ≤ +125°C1 17 mA A Digital Supply Current I V = 0 V, R = ∞ 6.0 7.0 mA DIG O L −40°C ≤ T ≤ +125°C1 8.0 mA A Analog Supply Current I –7.0 +14.0 mA −ANA −40°C ≤ T ≤ +85°C1 15.6 mA A −40°C ≤ T ≤ +125°C1 17 mA A 1 Full electrical specifications to −55°C, but these package types are guaranteed for operation from −40°C to +125°C only. Package reliability below −40°C is not guaranteed. 2 Guaranteed by design. Rev. B | Page 3 of 12

AD8564 V = V = 5.0 V, V = −5 V, T = 25°C, unless otherwise noted. +ANA +DIG −ANA A Table 2. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage V 2.3 7 mV OS −40°C ≤ T ≤ +125°C1 10 mV A Offset Voltage Drift ΔV /ΔT 4 μV/°C OS Input Bias Current I V = 0 V ±4 μA B CM −40°C ≤ T ≤ +125°C1 ±9 μA A Input Offset Current I V = 0 V ±3 μA OS CM Input Common-Mode Voltage Range V −4.9 +3.5 V CM Common-Mode Rejection Ratio CMRR 0 V ≤ V ≤ 3.0 V 65 85 dB CM Large Signal Voltage Gain A R = 10 kΩ 3000 V/V VO L Input Capacitance C 3.0 pF IN DIGITAL OUTPUTS Logic 1 Voltage V I = –3.2 mA, ΔV > +250 mV 2.6 3.6 V OH OH IN Logic 0 Voltage V I = 3.2 mA, ΔV > 250 mV 0.2 0.3 V OL OL IN DYNAMIC PERFORMANCE2 Propagation Delay t 200 mV step with 100 mV overdrive 6.75 9.8 ns P −40°C ≤ T ≤ +85°C1 8 13 ns A 100 mV step with 5 mV overdrive 8 ns Differential Propagation Delay (Rising Propagation Delay Δt 100 mV step with 20 mV overdrive 0.5 2.0 ns P vs. Falling Propagation Delay) Rise Time 20% to 80% 3 ns Fall Time 20% to 80% 3 ns POWER SUPPLY Power Supply Rejection Ratio PSRR 4.5 V ≤ V and V ≤ 5.5 V 50 70 dB +ANA +DIG Analog Supply Current I 10.8 14.0 mA +ANA −40°C ≤ T ≤ +85°C1 15.6 mA A −40°C ≤ T ≤ +125°C1 17 mA A Digital Supply Current I V = 0 V, R = ∞ 3.6 4.4 mA DIG O L −40°C ≤ T ≤ +125°C1 5.6 mA A Analog Supply Current I −8.2 +14.0 mA −ANA −40°C ≤ T ≤ +85°C1 15.6 mA A −40°C ≤ T ≤ +125°C1 17 mA A 1 Full electrical specifications to −55°C, but these package types are guaranteed for operation from −40°C to +125°C only. Package reliability below −40°C is not guaranteed. 2 Guaranteed by design. Rev. B | Page 4 of 12

AD8564 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 3. Parameter Rating θJA is specified for the worst-case conditions, that is, a device Total Analog Supply Voltage 14 V soldered in a circuit board for surface-mount packages (SOIC Digital Supply Voltage 17 V and TSSOP). θJA is specified for device in socket for PDIP. Analog Positive Supply to Digital Positive Supply −600 mV Input Voltage1 ±7 V Table 4. Thermal Resistance Differential Input Voltage ±8 V Package Type θJA θJC Unit Output Short-Circuit Duration to GND Indefinite 16-Lead PDIP (N) 90 47 °C/W Storage Temperature Range −65°C to +150°C 16-Lead Narrow Body SOIC (R) 113 37 °C/W Operating Temperature Range −55°C to +125°C 16-Lead TSSOP (RU) 180 37 °C/W Junction Temperature Range −65°C to +150°C Lead Temperature Range (Soldering, 10 sec) 300°C ESD CAUTION 1 The analog input voltage is equal to ±7 V or the analog supply voltage, whichever is less. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. B | Page 5 of 12

AD8564 TYPICAL PERFORMANCE CHARACTERISTICS V = V = 5 V, V = 0 V, T = 25°C, unless otherwise noted. +ANA +DIG –ANA A 1.0 500 V) 0.8 400 m S E ( ER LTAG 0.6 PLIFI300 O M V A T F E O FS 0.4 R 200 F E O B PUT NUM IN 0.2 100 0–75 –50 –25 0TEMP2E5RATU5R0E (°C7)5 100 125 150 01103-004 0 –5 –4 –3INP–U2T O–F1FSET0 VOLT1AGE 2(mV)3 4 5 01103-007 Figure 4. Input Offset Voltage vs. Temperature Figure 7. Input Offset Voltage Distribution 0 10 STEPSIZE = 100mV OVERDRIVE = 5mV –1 8 A) s) T (µ Y (n tPDHL N A URRE –2 N DEL 6 tPDLH C O BIAS –3 GATI 4 INPUT –4 PROPA 2 –5–75 –50 –25 0TEMP2E5RATU5R0E (°C7)5 100 125 150 01103-005 0–50 –25 0 TEM2P5ERATUR50E (°C) 75 100 125 01103-008 Figure 5. Input Bias Current vs. Temperature Figure 8. Propagation Delay, tPDHL/tPDLH vs. Temperature 0 5.0 V+ANA = V+DIG = +5V V–ANA = –5V INPUT BIAS CURRENT (µA) ––––1234 OUTPUT HIGH VOLTAGE (mV)4332....4826 TTAA == +–4805°°CC TA = +25°C –5–7.5 –5.I0NPUT COM–2M.5ON-MODE V0OLTAGE (V2).5 5.0 01103-006 2.00 3 SOUR6CE CURREN9T (mA) 12 15 01103-009 Figure 6. Input Bias Current vs. Input Common-Mode Voltage Figure 9. Output High Voltage, VOH vs. Source Current Rev. B | Page 6 of 12

AD8564 0.5 3.0 2.5 0.4 OLTAGE (V) 0.3 TA = +25°C TA = –40°C RRENT (mA)2.0 TA = +25°C TA = +85°C V U T LOW 0.2 PPLY C1.5 U U1.0 OUTP 0.1 TA = +85°C I S+DIG TA = –40°C 0.5 00 3 SINK6 CURRENT 9(mA) 12 15 01103-010 02 4 V+DIG S6UPPLY VOLT8AGE (V) 10 12 01103-013 Figure 10. Output Low Voltage, VOL vs. Sink Current Figure 13. I+DIG Supply Current/Comparator vs. V+DIG Supply Voltage 5 5 A) 4 A) 4 m m NT ( TA = +85°C NT ( V+ANA = ±5V RE 3 RE 3 R R CU TA = +25°C CU V+ANA = +5V Y Y L L UPP 2 TA = –40°C UPP 2 S S A A N N A A I+ 1 I+ 1 02 4 V+ANA S6UPPLY VOLT8AGE (V) 10 12 01103-011 0–75 –50 –25 0TEMP2E5RATU5R0E (°C7)5 100 125 150 01103-014 Figure 11. I+ANA Supply Current/Comparator vs. V+ANA Supply Voltage Figure 14. I+ANA Supply Current/Comparator vs. Temperature 0 0 mA) –1 TA = –40°C mA) –1 NT ( TA = +25°C NT ( V+ANA = +5V RE –2 RE –2 R R U U LY C TA = +85°C LY C V+ANA = ±5V PP –3 PP –3 U U S S ANA ANA I––4 I– –4 –52 4 V–ANA S6UPPLY VOLT8AGE (V) 10 12 01103-012 –5–75 –50 –25 0TEMP2E5RATU5R0E (°C7)5 100 125 150 01103-015 Figure 12. I−ANA Supply Current/Comparator vs. V−ANA Supply Voltage Figure 15. I−ANA Supply Current/Comparator vs. Temperature Rev. B | Page 7 of 12

AD8564 2.0 mA) 1.5 T ( N RE R U C 1.0 Y L P P U S G DI0.5 I+ 0 –75 –50 –25 0TEMP2E5RATU5R0E (°C7)5 100 125 150 01103-016 Figure 16. I+DIG Supply Current/Comparator vs. Temperature Rev. B | Page 8 of 12

AD8564 APPLICATIONS INFORMATION OPTIMIZING HIGH SPEED PERFORMANCE OUTPUT LOADING CONSIDERATIONS As with any high speed comparator or amplifier, proper design The AD8564 output can deliver up to 40 mA of output current and layout techniques should be used to ensure optimal perform- without any significant increase in propagation delay. The ance from the AD8564. The performance limits of high speed output of the device should not be connected to more than 20 circuitry can easily be a result of stray capacitance, improper TTL input logic gates or drive a load resistance less than 100 Ω. ground impedance, or other layout issues. To ensure the best performance from the AD8564, it is important Minimizing resistance from the source to the input is an important to minimize capacitive loading of the output of the device. consideration in maximizing the high speed operation of the Capacitive loads greater than 50 pF cause ringing on the output AD8564. Source resistance, in combination with equivalent waveform and reduce the operating bandwidth of the comparator. input capacitance, may cause a lagged response at the input, Propagation delay also increases with capacitive loads above 100 pF. thus delaying the output. The input capacitance of the AD8564, INPUT STAGE AND BIAS CURRENTS in combination with stray capacitance from an input pin to ground, may result in several picofarads of equivalent capaci- The AD8564 uses a PNP differential input stage that enables the tance. A combination of 3 kΩ source resistance and 5 pF of input common-mode range to extend all the way from the input capacitance yields a time constant of 15 ns, which is slower negative supply rail to within 2.2 V of the positive supply rail. than the 5 ns capability of the AD8564. Source impedances The input common-mode voltage can be found as the average should be less than 1 kΩ for the best performance. of the voltage at the two inputs of the device. To ensure the fastest response time, care should be taken to not allow the It is also important to provide bypass capacitors for the power input common-mode voltage to exceed this voltage. supply in a high speed application. A 1 μF electrolytic bypass capacitor should be placed within 0.5 inches of each power The input bias current for the AD8564 is 4 μA. As with any supply pin to ground. These capacitors reduce any potential PNP differential input stage, this bias current goes to 0 on an voltage ripples from the power supply. In addition, a 10 nF input that is high and doubles on an input that is low. Care should ceramic capacitor should be placed as close as possible to the be taken in choosing resistor values to be connected to the power supply pins to ground. These capacitors act as a charge inputs because large resistors could cause significant voltage reservoir for the device during high frequency switching. drops due to the input bias current. A ground plane is recommended for proper high speed perform- The input capacitance for the AD8564 is typically 3 pF. This can ance. This can be created by using a continuous conductive plane be measured by inserting a large source resistance to the input over the surface of the circuit board, only allowing breaks in the and measuring the change in propagation delay. plane for necessary current paths. The ground plane provides a low inductance ground, eliminating any potential differences at different ground points throughout the circuit board caused from ground bounce. A proper ground plane also minimizes the effects of stray capacitance on the circuit board. Rev. B | Page 9 of 12

AD8564 USING HYSTERESIS voltage is greater than VHI and does not switch low again until the input voltage is less than V , as given in Equation 2. LO Hysteresis can easily be added to a comparator through the addition of positive feedback. Adding hysteresis to a comparator V =(V −1−V ) R1 V (1) offers an advantage in noisy environments where it is not desirable HI + REF R1+R2 REF for the output to toggle between states when the input signal is ⎛ R1 ⎞ near the switching threshold. Figure 17 shows a method for V =V ⎜1− ⎟ (2) configuring the AD8564 with hysteresis. LO REF ⎜⎝ R1+R2⎟⎠ COMPARATOR where V is the positive supply voltage. + SIGNAL The C capacitor may also be added to introduce a pole into F R1 R2 the feedback network. This has the effect of increasing the VREF amount of hysteresis at high frequencies. This can be useful CF 01103-017 wnohiesne ecnovmirpoanrminegn at .r elatively slow signal in a high frequency Figure 17. Configuring the AD8564 with Hysteresis 1 The input signal is connected directly to the inverting input of At frequencies greater than f = , the hysteresis P 2πC R2 the comparator. The output is fed back to the noninverting F window approaches V = V – 1 V and V = 0 V. input through R2 and R1. The ratio of R1 to R1 + R2 and the HI + LO output swing establishes the width of the hysteresis window, At frequencies less than f , the threshold voltages remain as it is P with V setting the center of the window or the average REF in Equation 1. switching voltage. The output switches high when the input Rev. B | Page 10 of 12

AD8564 OUTLINE DIMENSIONS 0.800 (20.32) 0.790 (20.07) 0.780 (19.81) 16 9 0.280 (7.11) 0.250 (6.35) 1 8 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.100 (2.54) 0.300 (7.62) BSC 0.060 (1.52) 0.195 (4.95) 0.210 (5.33) MAX 0.130 (3.30) MAX 0.115 (2.92) 0.015 0.150 (3.81) (0.38) 0.015 (0.38) 0.130 (3.30) MIN GAUGE 0.115 (2.92) SEATING PLANE 0.014 (0.36) PLANE 0.010 (0.25) 0.022 (0.56) 0.008 (0.20) 0.005 (0.13) 0.430 (10.92) 0.018 (0.46) MIN MAX 0.014 (0.36) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) COMPLIANTTO JEDEC STANDARDS MS-001-AB CONTROLLING DIMENSIONSARE IN INCHES; MILLIMETER DIMENSIONS (RCINEOFRPENARREEREN NLCTEEHA EODSNSEL MSY)AAAYNR BDEE AR CROOEU NNNFODIGETUDAR-POEPFDRFOA INSPC RWHIAH ETOEQL UFEIO VORAR LU EHSNAETL ISFN FLDOEEARSDIGSN.. 073106-B Figure 18. 16-Lead Plastic Dual In-Line Package [PDIP] (N-16) Dimensions shown in inches and (millimeters) 10.00 (0.3937) 9.80 (0.3858) 4.00 (0.1575) 16 9 6.20 (0.2441) 3.80 (0.1496) 1 8 5.80 (0.2283) 1.27 (0.0500) 0.50 (0.0197) BSC 45° 1.75 (0.0689) 0.25 (0.0098) 0.25 (0.0098) 1.35 (0.0531) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 0.10 0.51 (0.0201) PLANE 0.25 (0.0098) 1.27 (0.0500) 0.31 (0.0122) 0.17 (0.0067) 0.40 (0.0157) COMPLIANTTO JEDEC STANDARDS MS-012-AC C(RINOEFNPEATRRREOENNLCLTEIHN EOGSN EDLSIYM)AEANNRDSEI AORRNOESU NANORDEET DAIN-PO MPFRIFLO LMPIIMRLELIATIMTEEER TFSEO; RIRN ECUQHSU EDI VIINMA LEDENENSSTIIOGSN NFS.OR 060606-A Figure 19. 16-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-16) Dimensions shown in millimeters and (inches) Rev. B | Page 11 of 12

AD8564 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.09 0.75 0.30 8° 0.60 B0S.6C5 0.19 SEATING 0° 0.45 PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 20. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD8564AN −40°C to +125°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16 AD8564ANZ1 −40°C to +125°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16 AD8564AR −40°C to +125°C 16-Lead Standard Small Outline Package [SOIC_N] R-16 AD8564AR-REEL −40°C to +125°C 16-Lead Standard Small Outline Package [SOIC_N] R-16 AD8564AR-REEL7 −40°C to +125°C 16-Lead Standard Small Outline Package [SOIC_N] R-16 AD8564ARZ1 −40°C to +125°C 16-Lead Standard Small Outline Package [SOIC_N] R-16 AD8564ARZ-REEL1 −40°C to +125°C 16-Lead Standard Small Outline Package [SOIC_N] R-16 AD8564ARZ-REEL71 −40°C to +125°C 16-Lead Standard Small Outline Package [SOIC_N] R-16 AD8564ARU-REEL −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 AD8564ARUZ-REEL1 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 1 Z = RoHS Compliant Part. ©1999–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C01103-0-8/07(B) Rev. B | Page 12 of 12

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD8564ARZ AD8564AR AD8564AR-REEL AD8564AR-REEL7 AD8564ARUZ-REEL AD8564ARZ-REEL AD8564ARZ-REEL7