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  • 型号: AD8561AR
  • 制造商: Analog
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AD8561AR产品简介:

ICGOO电子元器件商城为您提供AD8561AR由Analog设计生产,在icgoo商城现货销售,并且可以通过原厂、代理商等渠道进行代购。 AD8561AR价格参考。AnalogAD8561AR封装/规格:线性 - 比较器, 通用 比较器 CMOS,补充型,TTL 8-SOIC。您可以下载AD8561AR参考资料、Datasheet数据手册功能说明书,资料中有AD8561AR 详细功能的应用电路图电压和使用方法及教程。

产品参数 图文手册 常见问题
参数 数值
产品目录

集成电路 (IC)半导体

CMRR,PSRR(典型值)

85dB CMRR,65dB PSRR

描述

IC COMPARATOR SNGL 7NS 8-SOIC模拟比较器 Ultra fast 7ns SGL Supply

产品分类

线性 - 比较器

品牌

Analog Devices Inc

产品手册

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产品图片

rohs

否不符合限制有害物质指令(RoHS)规范要求

产品系列

校验器 IC,Analog Devices AD8561AR-

数据手册

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产品型号

AD8561AR

产品种类

模拟比较器

传播延迟时间

7 ns

传播延迟(最大值)

9.8ns

供应商器件封装

8-SOIC

偏转电压—最大值

3 mV

元件数

1

包装

管件

商标

Analog Devices

安装类型

表面贴装

安装风格

SMD/SMT

封装

Tube

封装/外壳

8-SOIC(0.154",3.90mm 宽)

封装/箱体

SOIC-8

工作温度

-40°C ~ 85°C

工厂包装数量

98

最大功率耗散

65 mW

最大工作温度

+ 85 C

最小工作温度

- 40 C

标准包装

98

滞后

-

电压-电源,单/双 (±)

3 V ~ 10 V, ±1.5 V ~ 5 V

电压-输入失调(最大值)

7mV @ 5V

电压增益dB

69.54 dB

电流-输入偏置(最大值)

6µA @ 5V

电流-输出(典型值)

-

电流-静态(最大值)

6mA,3.3mA,5.5mA

电源电压-最大

5 V

电源电压-最小

- 5 V

电源电流

6 mA at 5 V

电源电流—最大值

6 mA at 5 V

类型

通用

系列

AD8561

输入偏压电流—最大

6 uA (Min) at 5 V

输出类型

CMOS,补充型,TTL

通道数量

1 Channel

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PDF Datasheet 数据手册内容提取

a Ultrafast 7 ns Single Supply Comparator AD8561 FEATURES PIN CONFIGURATIONS 7 ns Propagation Delay at 5 V Single Supply Operation: 3 V to 10 V Low Power 8-Lead Narrow Body 8-Lead Plastic DIP Latch Function SOIC (R-8) (N-8) TSSOP Packages APPLICATIONS High Speed Timing V(cid:2) OUT V(cid:2) 1 8 OUT Clock Recovery and Clock Distribution (cid:2)(cid:3)IINN OGUNTD (cid:2)IN 2 7 OUT Line Receivers V(cid:3) LATCH (cid:3)IN 3 6 GND Digital Communications AD8561 V(cid:3) 4 AD8561 5 LATCH Phase Detectors High Speed Sampling Read Channel Detection 8-Lead TSSOP PCMCIA Cards (RU-8) Upgrade for LT1016 Designs V(cid:2) 1 8 OUT (cid:2)IN OUT (cid:3)IN AD8561 GND GENERAL DESCRIPTION V(cid:3) 4 5 LATCH The AD8561 is a single 7 ns comparator with separate input and output sections. Separate supplies enable the input stage to be operated from ±5 V dual supplies and +5 V single supplies. Fast 7 ns propagation delay makes the AD8561 a good choice for timing circuits and line receivers. Propagation delays for rising and falling signals are closely matched and track over temperature. This matched delay makes the AD8561 a good choice for clock recovery, since the duty cycle of the output will match the duty cycle of the input. The AD8561 has the same pinout as the LT1016, with lower supply current and a wider common-mode input range, which includes the negative supply rail. The AD8561 is specified over the industrial (–40°C to +85°C) temperature range. The AD8561 is available in the 8-lead plastic DIP, 8-lead TSSOP, and 8-lead narrow SOIC surface- mount packages. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©1998–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD8561–SPECIFICATIONS ELECTRICAL SPECIFICATIONS (@ V+ = +5.0 V, V– = V = 0 V, T = +25(cid:4)C unless otherwise noted) GND A Parameter Symbol Conditions Min Typ Max Units INPUT CHARACTERISTICS Offset Voltage V 2.3 7 mV OS –40°C ≤ T ≤ +85°C 8 mV A Offset Voltage Drift ΔV /ΔT 4 μV/°C OS Input Bias Current I V = 0 V –6 –3 μA B CM I –40°C ≤ T ≤ +85°C –7 –3.5 μA B A Input Offset Current I V = 0 V ±4 μA OS CM Input Common-Mode Voltage Range V 0.0 +3.0 V CM Common-Mode Rejection Ratio CMRR 0 V ≤ V ≤ +3.0 V 65 85 dB CM Large Signal Voltage Gain A R = 10 kΩ 3000 V/V VO L Input Capacitance C 3.0 pF IN LATCH ENABLE INPUT Logic “1” Voltage Threshold V 2.0 1.65 V IH Logic “0” Voltage Threshold V 1.60 0.8 V IL Logic “1” Current I V = 3.0 V –1.0 –0.3 μA IH LH Logic “0” Current I V = 0.3 V –4 –2 μA IL LL Latch Enable Pulsewidth t 6 ns PW(E) Setup Time t 1 ns S Hold Time t 1.2 ns H DIGITAL OUTPUTS Logic “1” Voltage V I = –50 μA, ΔV > 250 mV 3.5 V OH OH IN Logic “1” Voltage V I = –3.2 mA, ΔV > 250 mV 2.4 3.5 V OH OH IN Logic “0” Voltage V I = 3.2 mA, ΔV > 250 mV 0.25 0.4 V OL OL IN DYNAMIC PERFORMANCE Propagation Delay t 200 mV Step with 100 mV Overdrive 6.75 9.8 ns P –40°C ≤ T ≤ +85°C 8 13 ns A Propagation Delay t 100 mV Step with 5 mV Overdrive 8 ns P Differential Propagation Delay (Rising Propagation Delay vs. Falling Propagation Delay) Δt 100 mV Step with 100 mV Overdrive1 0.5 2.0 ns P Rise Time 20% to 80% 3.8 ns Fall Time 80% to 20% 1.5 ns POWER SUPPLY Power Supply Rejection Ratio PSRR +4.5 V ≤ V+ ≤ +5.5 V 50 65 dB Positive Supply Current I+ 4.5 6.0 mA –40°C ≤ T ≤ +85°C 7.5 mA A ∞ Ground Supply Current I V = 0 V, R = 2.2 3.3 mA GND O L –40°C ≤ T ≤ +85°C 3.8 mA A Analog Supply Current I– 2.3 4.5 mA –40°C ≤ T ≤ +85°C 5.5 mA A NOTES 1 Guaranteed by design. Specifications subject to change without notice. –2– Rev. D

AD8561 ELECTRICAL SPECIFICATIONS (@ V+= +5.0 V, V– = V = 0 V, V– = –5 V, T = +25(cid:4)C unless otherwise noted) GND A Parameter Symbol Conditions Min Typ Max Units INPUT CHARACTERISTICS Offset Voltage V 1 7 mV OS –40°C ≤ T ≤ +85°C 8 mV A Offset Voltage Drift ΔV /ΔT 4 μV/°C OS Input Bias Current I V = 0 V –6 –3 μA B CM I –40°C ≤ T ≤ +85°C –7 –2.5 μA B A Input Offset Current I V = 0 V ±4 μA OS CM Input Common-Mode Voltage Range V –5.0 +3.0 V CM Common-Mode Rejection Ratio CMRR –5.0 V ≤ V ≤ +3.0 V 65 85 dB CM Large Signal Voltage Gain A R = 10 kΩ 3000 V/V VO L Input Capacitance C 3.0 pF IN LATCH ENABLE INPUT Logic “1” Voltage Threshold V 2.0 1.65 V IH Logic “0” Voltage Threshold V 1.60 0.8 V IL Logic “1” Current I V = 3.0 V –1 –0.5 20 μA IH LH Logic “0” Current I V = 0.3 V –4 –2 20 μA IL LL Latch Enable Pulsewidth t 6 ns PW(E) Setup Time t 1.0 ns S Hold Time t 1.2 ns H DIGITAL OUTPUTS Logic “1” Voltage V I = –3.2 mA 2.6 3.5 V OH OH Logic “0” Voltage V I = 3.2 mA 0.2 0.3 V OL OL DYNAMIC PERFORMANCE Propagation Delay t 200 mV Step with 100 mV Overdrive 6.5 9.8 ns P –40°C ≤ T ≤ +85°C 8 13 ns A Propagation Delay t 100 mV Step with 5 mV Overdrive 7 ns P Differential Propagation Delay (Rising Propagation Delay vs. Falling Propagation Delay) Δt 100 mV Step with 100 mV Overdrive1 0.5 2 ns P Rise Time 20% to 80% 3.8 ns Fall Time 80% to 20% 1.5 ns Dispersion 1 ns POWER SUPPLY Power Supply Rejection Ratio PSRR ±4.5 V ≤ V and V ≤ ±5.5 V 55 70 dB CC ∞ EE Supply Current V = 0 V, R = O L Positive Supply Current I+ 4.7 6.5 mA –40°C ≤ T ≤ +85°C 7.5 mA A ∞ Ground Supply Current I V = 0 V, R = 2.2 3.3 mA GND O L –40°C ≤ T ≤ +85°C 3.8 mA A Negative Supply Current I– 2.4 4.5 mA –40°C ≤ T ≤ +85°C 5.5 mA A NOTES 1 Guaranteed by design. Specifications subject to change without notice. Rev. D –3–

AD8561–SPECIFICATIONS ELECTRICAL SPECIFICATIONS (@ V+= +3.0 V, V– = V = 0 V, T = +25(cid:4)C unless otherwise noted) GND A Parameter Symbol Conditions Min Typ Max Units INPUT CHARACTERISTICS Offset Voltage V 7 mV OS Input Bias Current I V = 0 V –6 –3.0 μA B CM I –40°C ≤ T ≤ +85°C –7 –4 μA B A Input Common-Mode Voltage Range V 0 +1.5 V CM Common-Mode Rejection Ratio CMRR 0.1 V ≤ V ≤ 1.5 V 60 dB CM OUTPUT CHARACTERISTICS Output High Voltage V I = –3.2 mA, V > 250 mV 1.21 V OH OH IN Output Low Voltage V I = +3.2 mA, V > 250 mV 0.3 V OL OL IN POWER SUPPLY Power Supply Rejection Ratio PSRR +2.7 V ≤ V , V ≤ +6 V 40 dB CC ∞EE Supply Currents V = 0 V, R = O L V+ Supply Current I+ 4.0 4.5 mA –40°C ≤ T ≤ +85°C 5.5 mA A Ground Supply Current I 1.6 2.5 mA GND –40°C ≤ T ≤ +85°C 3.0 mA A V– Supply Current I– 2.4 3.3 mA –40°C ≤ T ≤ +85°C 3.8 mA A DYNAMIC PERFORMANCE Propagation Delay t 100 mV Step with 20 mV Overdrive2 8.5 9.8 ns P NOTES 1Output high voltage without pull-up resistor. It may be useful to have a pull-up resistor to V+ for 3 V operation. 2Guaranteed by design. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS Package Type (cid:5) 2 (cid:5) Units JA JC Total Supply Voltage from V– to V+ . . . . . . . . . . . . . . . . . 14 V 8-Lead Plastic DIP (N) 103 43 °C/W Input Voltage1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±7 V 8-Lead SO (R) 158 43 °C/W Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . .±8 V 8-Lead TSSOP 240 43 °C/W Output Short-Circuit Duration to GND . . . . . . . . . Indefinite NOTES Storage Temperature Range 1The analog input voltage is equal to ±7 V or the analog supply voltage, whichever is less. N, R, RU Package . . . . . . . . . . . . . . . . . . –65°C to +150°C 2θ is specified for the worst case conditions, i.e., θ is specified for device in socket JA JA Operating Temperature Range . . . . . . . . . . . –40°C to +85°C for P-DIP and θJA is specified for device soldered in circuit board for SOIC and TSSOP packages. Junction Temperature Range N, R, RU Package . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering, 10 sec) . . . . . . . . 350°C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD8561 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. –4– Rev. D

AD8561 Typical Performance Characteristics (V+ = +5 V, V– = 0 V, T = +25(cid:4)C unless otherwise noted) A 5 500 20 +125(cid:4)C VS = 5V, SINGLE SUPPLY VS = 5V, SINGLE SUPPLY STEP SIZE = 100mV AGE – Volts43 –40(cid:4)C MPARATORS340000 DELAY – ns15 CAPACITANCE LOAD = 10pTFA = +25(cid:4)C UT VOLT2 +25(cid:4)C R OF CO200 GATION 10 P E A UT MB OP 5 O1 U100 R N P 0 0 0 –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 –5 –4 –3 –2 –1 0 1 2 3 4 5 0 10 20 30 40 50 DIFFERENTIAL INPUT VOLTAGE – mV INPUT VOLTAGE – mV OVERDRIVE – mV Figure 1.Output Voltage vs. Differen- Figure 2.Typical Distribution of Input Figure 3.Propagation Delay vs. tial Input Voltage Offset Voltage Overdrive 20 40 20 PROPAGATION DELAY – ns11550 VSOSTV EE=P R5 DSVRI,Z SIEVIN E=G L1LO0E0FAF mASADVULL =LPL It5tIPNPNPmLDGDGY V – + EEDDGGEE PROPAGATION DELAY – ns 321000 VOCSAV PE= AR5CDVIR,T SIAVISNNETGC E=LE P1E L0S mSOIZUAVEPD P= = L8 4Y1000020pm0mF0VVmTVA1 =0 0+m25V(cid:4)C PROPAGATION DELAY – ns 11550 SSOCITAVNEPEGPARL CDSEIRI TZSIAEVU NEP=C P=1EL 05 Y0Lmm,OVVAD = 10pFTA = +25(cid:4)C 00 10 20 30 40 50 00 0.5 1 1.5 2 04.5 4.75 5 5.25 5.5 LOAD CAPACITANCE – pF SOURCE RESISTANCE – k(cid:6) SUPPLY VOLTAGE – Volts Figure 4.Propagation Delay vs. Load Figure 5.Propagation Delay vs. Figure 6.Propagation Delay vs. Posi- Capacitance Source Resistance tive Supply Voltage 20 20 4 +25(cid:4)C VS = +5V, SINGLE SUPPLY AY – ns15 SOLOTVEAEPDR DSCRIAZIEPV AE= C =1I 0T50AmmNVVC,E = 10pF AY – ns15 –40(cid:4)C 3 DEL DEL +125(cid:4)C ns ON 10 ON 10 E – 2 HOLD TIME ATI ATI TIM SET-UP TIME G G A A P P RO 5 RO 5 VS = 5V 1 P P STEP SIZE = 100mV OVERDRIVE = 5mV LOAD CAPACITANCE = 10pF 0 0 0 –50 –25 0 25 50 75 100 125 0 1 2 3 4 5 –50 –25 0 25 50 75 100 125 TEMPERATURE – (cid:4)C COMMON-MODE VOLTAGE – Volts TEMPERATURE – (cid:4)C Figure 7.Propagation Delay vs. Figure 8.Propagation Delay vs. V Figure 9.Latch Setup-and-Hold Time CM Temperature vs. Temperature Rev. D –5–

AD8561 0.5 5.0 0 A m GE – Volts0.4 GE – Volts4.4 TA = +125(cid:4)C RRENT – –1.0 V+ = 5V, V– = 0V A0.3 A3.8 U–2.0 VOLT TA = –40(cid:4)C TA = +25(cid:4)C VOLT TA = +25(cid:4)C PLY C V+ = 5V, V– = –5V OUTPUT LOW 00..21 TA = +125(cid:4)C OUTPUT HIGH 32..26 TA = –40(cid:4)C –, ANALOG SUP––34..00 I 0 2.0 –5.0 0 3 6 9 12 15 0 3 6 9 12 15 –75 –50 –25 0 25 50 75 100 125 150 SINK CURRENT – mA SOURCE CURRENT – mA TEMPERATURE – (cid:4)C Figure 10.Output Low Voltage, V Figure 11.Output High Voltage, V Figure 12.Analog Supply Current vs. OL OH vs. Sink Current vs. Source Current Temperature for +5 V, –5 V Supplies 0 40 0 mA mA35 URRENT – ––21..00 TA = –40(cid:4)C URRENT – 3205 (cid:7)RENT – A ––12 SUPPLY C–3.0 TTAA == ++12255(cid:4)C(cid:4)C SUPPLY C2105 +125(cid:4)C +25(cid:4)C BIAS CUR –3 –, ANALOG –4.0 POSITIVE 150 –40(cid:4)C INPUT –4 I –5.0 0 –5 2 4 6 8 10 12 1 10 100 –7.5 –5 –2.5 0 2.5 5 SUPPLY VOLTAGE –Volts FREQUENCY – MHz INPUT COMMON-MODE VOLTAGE – Volts Figure 13.Analog Supply Current vs. Figure 14.Positive Supply Current Figure 15.Input Bias Current vs. Input Supply Voltage for +5 V, –5 V Supplies vs. Frequency Common-Mode Voltage for +5 V, –5 V Supplies 0 A–1.0 (cid:7) – T N RE–2.0 R U C S A–3.0 BI T U P N–4.0 I –5.0 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE – (cid:4)C Figure 16.Input Bias Current vs. Temperature –6– Rev. D

AD8561 APPLICATIONS Example: A comparator compares a fast moving signal to a OPTIMIZING HIGH SPEED PERFORMANCE fixed 2.5 V reference. Since the comparator only needs to oper- As with any high speed comparator or amplifier, proper design ate when the signal is near 2.5 V, both signals will be within the and layout techniques should be used to ensure optimal perfor- input range (near 2.5 V and well under 3.0 V) when the com- mance from the AD8561. The performance limits of high speed parator needs to change output. circuitry can easily be a result of stray capacitance, improper Note that signals much greater than 3.0 V will result increased ground impedance or other layout issues. input currents and may cause the device to operate more slowly. Minimizing resistance from source to the input is an important The input bias current of the AD8561 is lower (–3μA typical) consideration in maximizing the high speed operation of the than the LT1016 (+5μA typical), and the current flows out of AD8561. Source resistance in combination with equivalent the AD8561 and into LT1016. If relatively low value resistors input capacitance could cause a lagged response at the input, and/or low impedance sources are used on the inputs, the volt- thus delaying the output. The input capacitance of the AD8561 age shift due to bias current should be small. in combination with stray capacitance from an input pin to The AD8561 (6.75 ns typical) is faster than the LT1016 (10 ns ground could result in several picofarads of equivalent capaci- tance. A combination of 3 kΩ source resistance and 5 pF of typical). While this is beneficial to many systems, timing may need to be adjusted to take advantage of the higher speed. input capacitance yields a time constant of 15 ns, which is slower than the 5 ns capability of the AD8561. Source imped- The AD8561 has slightly more output voltage swing, from 0.2V ances should be less than 1 kΩ for the best performance. above ground to within 1.1 V of the positive supply voltage. It is also important to provide bypass capacitors for the power The AD8561 uses less current (typically 5 mA) than the LT1016 supply in a high speed application. A 1 μF electrolytic bypass (typically 25 mA). capacitor should be placed within 0.5 inches of each power supply pin, Pin 1 and Pin 4, to ground. These capacitors will INCREASING OUTPUT SWING reduce any potential voltage ripples from the power supply. In Although not required for normal operation, the output voltage addition, a 10 nF ceramic capacitor should be placed as close as swing of the AD8561 can be increased by connecting a 5 kΩ possible from the power supply pins to ground. These capacitors resistor from the output of the device to the V+ power supply. act as a charge reservoir for the device during high frequency This configuration can be useful in low voltage power supply switching. applications where maximizing output voltage swing is impor- tant. Adding a 5 kΩ pull-up resistor to the device’s output will A ground plane is recommended for proper high speed perfor- not adversely affect the specifications of the AD8561. mance. This can be created by using a continuous conductive plane over the surface of the circuit board, only allowing breaks OUTPUT LOADING CONSIDERATIONS in the plane for necessary current paths. The ground plane The AD8561 output can deliver up to 40 mA of output current provides a low inductive ground, eliminating any potential dif- without any significant increase in propagation delay. The ferences at different ground points throughout the circuit board output of the device should not be connected to more than caused from “ground bounce.” A proper ground plane also twenty (20) TTL input logic gates, or drive a load resistance minimizes the effects of stray capacitance on the circuit board. less than 100 Ω. REPLACING THE LT1016 To ensure the best performance from the AD8561 it is impor- The AD8561 is pin compatible with the LT1016 comparator. tant to minimize capacitive loading of the output of the device. While it is easy to replace the LT1016 with the higher perfor- Capacitive loads greater than 50 pF will cause ringing on the mance AD8561, please note that there are differences, and it is output waveform and will reduce the operating bandwidth of useful to check these to ensure proper operation. the comparator. There are five major differences between the AD8561 and the SETUP AND HOLD TIMES FOR LATCHING THE LT1016—input voltage range, input bias currents, speed, out- OUTPUT put swing and power consumption. The latch input, Pin 5, can be used to retain data at the output When operated on a +5 V single supply, the LT1016 has an of the AD8561. When the voltage at the latch input goes high, input voltage range from +1.25 V to +3.5 V. The AD8561 has a the output of the device will remain constant regardless of the wider input range from 0 V to 3.0 V. Signals above 3.0 V may input voltages. The setup time for the latch is 2 ns–3 ns and the result in slower response times (see Figure 8). If both signals hold time is 3 ns. This means that to ensure data retention at exceed 3.0 V, the signals may be shifted or attenuated to bring the output, the input signal must be valid at least 5 ns before them into range, keeping in mind the note about source resis- the latch pin goes high and must remain valid at least 3 ns after tance in Optimizing High Speed Performance. If only one of the the latch pin goes high. Once the latch input voltage goes low, signals exceeds 3.0 V only slightly, and the other signal is always new output data will appear in approximately 8 ns. well within the 0V to 3 V range, the comparator may operate A logic high for the latch input is a minimum of +2.0 V and a without changes to the circuit. logic low is a maximum of +0.8 V. This makes the latch input easily interface with TTL or CMOS logic gates. The latch circuitry in the AD8561 has no built-in hysteresis. Rev. D –7–

AD8561 INPUT STAGE AND BIAS CURRENTS The input signal is connected directly to the noninverting input The AD8561 uses a PNP differential input stage that enables of the comparator. The output is fed back to the inverting input the input common-mode range to extend all the way from the through R1 and R2. The ratio of R1 to R1 + R2 establishes the negative supply rail to within 2.2 V of the positive supply rail. width of the hysteresis window with VREF setting the center of The input common-mode voltage can be found as the average the window, or the average switching voltage. The Q output will of the voltage at the two inputs of the device. To ensure the switch high when the input voltage is greater than VHI and will fastest response time, care should be taken not to allow the not switch low again until the input voltage is less than VLO as input common-mode voltage to exceed either of these voltages. given in Equation 1: The input bias current for the AD8561 is 3 μA. As with any ( ) R1 PNP differential input stage, this bias current will go to zero on V = V –1–V +V an input that is high and will double on an input that is low. HI + REF R1+R2 REF Care should be taken in choosing resistor values to be con- (1) nected to the inputs as large resistors could cause significant ⎛ R1 ⎞ V =V ⎜1– ⎟ voltage drops due to the input bias current. LO REF⎝ R1+R2⎠ The input capacitance for the AD8561 is typically 3 pF. This is measured by inserting a 5 kΩ source resistance to the input and Where V is the positive supply voltage. + measuring the change in propagation delay. The capacitor C can also be added to introduce a pole into the F feedback network. This has the effect of increasing the amount USING HYSTERESIS of hysteresis at high frequencies. This can be useful when com- Hysteresis can easily be added to a comparator through the paring a relatively slow signal in a high frequency noise environ- addition of positive feedback. Adding hysteresis to a comparator offers an advantage in noisy environments where it is not desir- 1 ment. At frequencies greater than f = , the hysteresis able for the output to toggle between states when the input P 2πC R2 F signal is near the switching threshold. Figure 17 shows a window approaches V = V – 1 V and V = 0 V. At frequen- HI + LO method for configuring the AD8561 with hysteresis. cies less than f the threshold voltages remain as in Equation 1. P COMPARATOR SIGNAL R1 R2 VREF CF Figure 17.Configuring the AD8561 with Hysteresis –8– Rev. D

AD8561 SPICE Model * AD8561 SPICE Macro-Model Typical Values * 4/98, Ver. 1.0 * TAM / ADSC * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | |Latch * | | | | |DGND * | | | | | | Q * | | | | | | |QNOT * | | | | | | | | .SUBCKT AD8561 1 2 99 50 80 51 45 65 * * INPUT STAGE * * Q1 4 3 5 PIX Q2 6 2 5 PIX IBIAS 99 5 800E-6 RC1 4 50 1E3 RC2 6 50 1E3 CL1 4 6 1E-12 CIN 1 2 3E-12 VCM1 99 7 1 D1 5 7 DX EOS 3 1 POLY(1) (31,98) 1E-3 1 * * Reference Voltage * EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 RREF 98 0 100E3 * * CMRR=80dB, ZERO AT 1kHz * ECM1 30 98 POLY(2) (1,98) (2,98) 0 0.5 0.5 RCM1 30 31 10E3 RCM2 31 98 1 CCM1 30 31 15.9E-9 * * Latch Section * RX 80 51 100E3 E1 10 98 (4,6) 1 S1 10 11 (80,51) SLATCH1 R2 11 12 1 C3 12 98 10E-12 E2 13 98 (12,98) 1 R3 12 13 500 * * Power Supply Section * Rev. D –9–

AD8561 GSY1 99 52 POLY(1) (99,50) 4E-3 -2.6E-4 GSY2 52 50 POLY(1) (99,50) 3.7E-3 -.6E-3 RSY 52 51 10 * * Gain Stage Av=250 fp=100MHz * G2 98 20 (12,98) 0.25 R1 20 98 1000 C1 20 98 10E-13 D2 20 21 DX D3 22 20 DX V1 99 21 DC 0.8 V2 22 50 DC 0.8 * * Q Output * Q3 99 41 46 NOX Q4 47 42 50 NOX RB1 43 41 200 RB2 40 42 5E3 CB1 99 41 10E-12 CB2 42 50 5E-12 RO1 46 45 2E3 RO2 47 45 500 EO1 98 43 POLY(1) (20,98) 0 1 EO2 40 98 POLY(1) (20,98) 0 1 * * Q NOT Output * Q5 99 61 66 NOX Q6 67 62 50 NOX RB3 63 61 200 RB4 60 62 5E3 CB3 99 61 10E-12 CB4 62 50 5E-12 RO3 66 65 2E3 RO4 67 65 500 EO3 63 98 POLY(1) (20,98) 0 1 EO4 98 60 POLY(1) (20,98) 0 1 * * MODELS * .MODEL PIX PNP(BF=100,IS=1E-16) .MODEL NOX NPN(BF=100,VAF=130,IS=1E-14) .MODEL DX D(IS=1E-16) .MODEL SLATCH1 VSWITCH(ROFF=1E6,RON=500,VOFF=2.1,VON=1.4) .ENDS AD8561 –10– Rev. D

AD8561 OUTLINE DIMENSIONS 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 8 5 0.280 (7.11) 0.250 (6.35) 1 4 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.100 (2.54) 0.300 (7.62) BSC 0.060 (1.52) 0.195 (4.95) 0.210 (5.33) MAX 0.130 (3.30) MAX 0.115 (2.92) 0.015 0.150 (3.81) (0.38) 0.015 (0.38) 0.130 (3.30) MIN GAUGE 0.115 (2.92) SEATING PLANE 0.014 (0.36) PLANE 0.010 (0.25) 0.022 (0.56) 0.008 (0.20) 0.005 (0.13) 0.430 (10.92) 0.018 (0.46) MIN MAX 0.014 (0.36) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) COMPLIANTTO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONSARE IN INCHES; MILLIMETER DIMENSIONS (RCINOEFRPENAREREREN NLCTEEHA EODSNSEL MSY)AAAYNR BDEE AR CROOEU NNNFODIGETUDAR-POEPFDRFOA INSPC RWHIAH ETOEQL UFEIO VORAR LU EHSNAETL ISFN FLDOEEARSDIGSN.. 070606-A Figure 18. 8-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-8) Dimensions shown in inches and (millimeters) 5.00(0.1968) 3.10 4.80(0.1890) 3.00 2.90 8 5 4.00(0.1574) 6.20(0.2441) 8 5 3.80(0.1497) 1 4 5.80(0.2284) 4.50 4.40 6.40 BSC 4.30 1.27(0.0500) 0.50(0.0196) BSC 1.75(0.0688) 0.25(0.0099) 45° 1 4 0.25(0.0098) 1.35(0.0532) 8° 0.10(0.0040) 0° PIN 1 COPLANARITY 0.51(0.0201) 0.65 BSC 0.10 SEATING 0.31(0.0122) 0.25(0.0098) 10..2470((00..00510507)) 0.15 1.20 PLANE 0.17(0.0067) 0.05 MAX 8° COMPLIANTTOJEDECSTANDARDSMS-012-AA COPLANARITY 0.30 SEATING 0.20 0° 0.75 CONTROLLINGDIMENSIONSAREINMILLIMETERS;INCHDIMENSIONS 0.10 0.19 PLANE 0.09 00..6405 (INPARENTHESES)AREROUNDED-OFFMILLIMETEREQUIVALENTSFOR COMPLIANT TO JEDEC STANDARDS MO-153-AA REFERENCEONLYANDARENOTAPPROPRIATEFORUSEINDESIGN. Figure 19. 8-Lead Standard Small Outline Package [SOIC_N] Figure 20. 8-Lead Thin Shrink Small Outline Package [TSSOP] (RU-8) Narrow Body (R-8) Dimensions shown in millimeters Dimensions shown in millimeters and (inches) Rev. D | Page 11 of 12

AD8561 ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD8561ANZ −40°C to +85°C 8-Lead Plastic Dual In-Line Package [PDIP] N-8 AD8561ARUZ −40°C to +85°C 8-Lead Thin Shrink Small Outline Package [TSSOP] RU-8 AD8561ARUZ-REEL −40°C to +85°C 8-Lead Thin Shrink Small Outline Package [TSSOP] RU-8 AD8561ARZ −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD8561ARZ-REEL −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD8561ARZ-REEL7 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 1 Z = RoHS Compliant Part. REVISION HISTORY 12/2016—Rev. C to Rev. D Changed SO-8 to R-8... ................................................. Throughout Changes to General Description Section ...................................... 1 11/2016—Rev. B to Rev. C Changes to Absolute Maximum Ratings Section ......................... 4 12/2013—Rev. A to Rev. B Changes to Figure 19 Caption and Figure 20 Caption .............. 11 Changes to Ordering Guide .......................................................... 12 4/2013—Rev. 0 to Rev. A Change to Lead Temperature Range (Soldering, 10 Sec) Parameter, Absolute Maximum Ratings Section .......................... 4 Updated Outline Dimensions ....................................................... 11 Moved Ordering Guide and Added Revision History Section ...... 12 Changes to Ordering Guide .......................................................... 12 6/1998—Revision 0: Initial Version ©1998–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D3220-0-12/16(D) Rev. D | Page 12 of 12