a m 5 V, 14-Bit Serial, 5 s ADC in SO-8 Package AD7894 FEATURES FUNCTIONAL BLOCK DIAGRAM Fast 14-Bit ADC with 5 ms Conversion Time 8-Lead SOIC Package REF IN VDD Single 5 V Supply Operation High Speed, Easy-to-Use, Serial Interface AD7894 On-Chip Track/Hold Amplifier Selection of Input Ranges TRACK/ 610 V for AD7894-10 SIGNAL HOLD 62.5 V for AD7894-3 VIN SCALING* 14-BIT ADC 0 V to +2.5 V for AD7894-2 High Input Impedance Low Power: 20 mW Typ OUTPUT CONVST Pin Compatible Upgrade of 12-Bit AD7895 REGISTER GND BUSY SCLK SDATA *AD7894-10, AD7894-3 GENERAL DESCRIPTION The AD7894 is a fast, 14-bit ADC that operates from a single PRODUCT HIGHLIGHTS +5 V supply and is housed in a small 8-lead SOIC. The part contains a 5 m s successive approximation A/D converter, an on- 1. Fast, 14-Bit ADC in 8-Lead Package The AD7894 contains a 5␣m s ADC, a track/hold amplifier, chip track/hold amplifier, an on-chip clock and a high speed control logic and a high speed serial interface, all in an 8-lead serial interface. package. This offers considerable space saving over alterna- Output data from the AD7894 is provided via a high speed, tive solutions. serial interface port. This two-wire serial interface has a serial 2. Low Power, Single Supply Operation clock input and a serial data output with the external serial clock The AD7894 operates from a single +5 V supply and con- accessing the serial data from the part. sumes only 20 mW. The automatic power-down mode, In addition to the traditional dc accuracy specifications such as where the part goes into power-down once conversion is linearity, full-scale and offset errors, the AD7894 is also speci- complete and “wakes up” before the next conversion cycle, fied for dynamic performance parameters including harmonic makes the AD7894 ideal for battery powered or portable distortion and signal-to-noise ratio. applications. The part accepts an analog input range of – 10 V (AD7894-10), 3. High Speed Serial Interface – 2.5 V (AD7894-3), 0 V to +2.5 V (AD7894-2), and operates The part provides high speed serial data and serial clock lines from a single +5 V supply consuming only 20 mW typical. allowing for an easy, two-wire serial interface arrangement. The AD7894 features a high sampling rate mode and, for low power applications, a proprietary automatic power-down mode where the part automatically goes into power-down once conver- sion is complete and “wakes up” before the next conversion cycle. The part is available in a small outline IC (SOIC). REV.0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1998

AD7894–SPECIFICATIONS (V = +5 V 6 5%, GND = 0 V, REF IN = +2.5 V. All specifications T to T unless DD MIN MAX otherwise noted.) Parameter A Versionsl B Versions1 Units Test Conditions/Comments DYNAMIC PERFORMANCE2 Signal to (Noise + Distortion) Ratio3 @ +25(cid:176) C 78 78 dB min f = 70 kHz Sine Wave, f = 160 kHz IN SAMPLE T to T 77 77 dB min See Figure 14 MIN MAX Total Harmonic Distortion (THD)3 –86 –86 dB max f = 10 kHz Sine Wave, f = 160 kHz, IN SAMPLE Typically –87 dB. See Figure 15 Peak Harmonic or Spurious Noise3 –92 –92 dB typ f = 10 kHz Sine Wave, f = 160 kHz IN SAMPLE Intermodulation Distortion (IMD)3 fa = 9 kHz, fb = 9.5 kHz, f = 160 kHz SAMPLE 2nd Order Terms –92 –92 dB typ 3rd Order Terms –92 –92 dB typ DC ACCURACY Resolution 14 14 Bits Minimum Resolution for Which No Missing Codes Are Guaranteed 14 14 Bits Relative Accuracy3 – 2 – 1.5 LSB max Differential Nonlinearity3 –1 to +1.5 –1 to +1.5 LSB max AD7894-2 Positive Gain Error3 – 12 – 10 LSB max Unipolar Offset Error – 8 – 6 LSB max AD7894-10, AD7894-3 Only Positive Gain Error3 – 8 – 6 LSB max Negative Gain Error3 – 8 – 6 LSB max Bipolar Zero Error – 10 – 8 LSB max ANALOG INPUT AD7894-10 Input Voltage Range – 10 – 10 V Input Current 2 2 mA max See Analog Input Section AD7894-3 Input Voltage Range – 2.5 – 2.5 V Input Current 1.5 1.5 mA max See Analog Input Section AD7894-2 Input Voltage Range 0 to +2.5 0 to +2.5 V Input Current 500 500 nA max REFERENCE INPUT REF IN Input Voltage Range 2.375/2.625 2.375/2.625 V min/V max 2.5 V – 5% Input Current 1 1 m A max Input Capacitance4 10 10 pF max LOGIC INPUTS Input High Voltage, V 2.4 2.4 V min V = 5 V – 5% INH DD Input Low Voltage, V 0.8 0.8 V max V = 5 V – 5% INL DD Input Current, I – 10 – 10 m A max V = 0 V to V IN IN DD Input Capacitance, C 4 10 10 pF max IN LOGIC OUTPUTS Output High Voltage, V 4.0 4.0 V min I = 400 m A OH SOURCE Output Low Voltage, V 0.4 0.4 V max I = 1.6 mA OL SINK Output Coding AD7894-10, AD7894-3 Twos Complement AD7894-2 Straight (Natural) Binary CONVERSION RATE Conversion Time Mode 1 Operation 5 5 m s max Mode 2 Operation5 10 10 m s max Track/Hold Acquisition Time3 0.35 0.35 m s max SAMPLE AND HOLD –3 dB Small Signal Bandwidth 7.5 7.5 MHz typ Aperture Jitter 50 50 ps typ –2– REV. 0

AD7894 Parameter A Versionsl B Versions1 Units Test Conditions/Comments POWER REQUIREMENTS V +5 +5 V nom – 5% for Specified Performance DD I 5.5 5.5 mA max Digital Inputs @ V , V = 5 V – 5% DD DD DD Power Dissipation 27.5 27.5 mW max Typically 20 mW Power-Down Mode I @ T to T 20 20 m A max Digital Inputs @ GND, V = 5 V – 5% DD MIN MAX DD Power Dissipation T to T 100 100 m W max Typ 15 m W MIN MAX NOTES 1Temperature ranges are as follows: A, B Versions: –40(cid:176)C to +85(cid:176)C. 2Applies to Mode 1 operation. See Operating Modes section. 3See Terminology. 4Sample tested @ +25(cid:176)C to ensure compliance. 5This 10 m s includes the “wake-up” time from standby. This “wake-up” time is timed from the rising edge of CONVST, whereas conversion is timed from the falling edge of CONVST, for narrow CONVST pulsewidth the conversion time is effectively the “wake-up” time plus conversion time, hence 10 m s. This can be seen from Figure 3. Note that if the CONVST pulsewidth is greater than 5 m s, the effective conversion time will increase beyond 10 m s. Specifications subject to change without notice. TIMING CHARACTERISTICS1, 2 (V = +5 V 6 5%, GND = 0 V, REF IN = +2.5 V) DD Parameter A, B Versions Units Test Conditions/Comments t 40 ns min CONVST Pulsewidth 1 t 31.252 ns min SCLK High Pulsewidth 2 t 31.252 ns min SCLK Low Pulsewidth 3 t 603 ns max Data Access Time after Falling Edge of SCLK 4 V = 5 V – 5% DD t 10 ns min Data Hold Time after Falling Edge of SCLK 5 t 204 ns max Bus Relinquish Time after Falling Edge of SCLK 6 NOTES 1Sample tested at +25(cid:176)C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6 V. 2The SCLK maximum frequency is 16 MHz. Care must be taken when interfacing to account for the data access time, t, and the setup time required for the user’s 4 processor. These two times will determine the maximum SCLK frequency with which the user’s system can operate. See Serial Interface section for more information. 3Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.0 V. 4Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t , quoted in the timing characteristics is the true bus relinquish time 6 of the part and as such is independent of external bus loading capacitances. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS* Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150(cid:176) C (T = +25(cid:176)C unless otherwise noted) SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW A V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3␣V to +7 V ␣␣q Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 170(cid:176) C/W DD JA Analog Input Voltage to GND ␣␣Lead Temperature, Soldering ␣␣AD7894-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 17 V ␣␣␣␣Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215(cid:176) C ␣␣AD7894-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 7 V ␣␣␣␣Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .+220(cid:176) C ␣␣AD7894-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to +10 V *Stresses above those listed under Absolute Maximum Ratings may cause perma- Reference Input Voltage to GND . . . . –0.3 V to VDD + 0.3 V nent damage to the device. This is a stress rating only; functional operation of the Digital Input Voltage to GND . . . . . . . –0.3 V to V + 0.3 V device at these or any other conditions above those listed in the operational DD Digital Output Voltage to GND . . . . . –0.3 V to V + 0.3 V sections of this specification is not implied. Exposure to absolute maximum rating DD conditions for extended periods may affect device reliability. Operating Temperature Range ␣␣Commercial (A, B Versions) . . . . . . . . . . . –40(cid:176) C to +85(cid:176) C ␣␣Storage Temperature Range . . . . . . . . . . . –65(cid:176) C to +150(cid:176) C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD7894 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –3–

AD7894 ORDERING GUIDE Temperature Package Package Model Range INL Input Range SNR Description Option AD7894AR-10 –40(cid:176) C to +85(cid:176) C – 2 LSB – 10 V 77 dB 8-Lead Narrow Body SOIC SO-8 AD7894BR-10 –40(cid:176) C to +85(cid:176) C – 1.5 LSB – 10 V 77 dB 8-Lead Narrow Body SOIC SO-8 AD7894AR-3 –40(cid:176) C to +85(cid:176) C – 2 LSB – 2.5 V 77 dB 8-Lead Narrow Body SOIC SO-8 AD7894BR-3 –40(cid:176) C to +85(cid:176) C – 1.5 LSB – 2.5 V 77 dB 8-Lead Narrow Body SOIC SO-8 AD7894AR-2 –40(cid:176) C to +85(cid:176) C – 2 LSB 0 V to +2.5 V 77 dB 8-Lead Narrow Body SOIC SO-8 PIN FUNCTION DESCRIPTIONS Pin Pin No. Mnemonic Description 1 REF IN Voltage Reference Input. An external reference source should be connected to this pin to provide the reference voltage for the AD7894’s conversion process. The REF IN input is buffered on-chip. The nominal reference voltage for correct operation of the AD7894 is +2.5␣V. 2 V Analog Input Channel. The analog input range is – 10 V (AD7894-10), – 2.5 V (AD7894-3) and 0 V to IN +2.5␣V (AD7894-2). 3 GND Analog Ground. Ground reference for track/hold, comparator, digital circuitry and DAC. 4 SCLK Serial Clock Input. An external serial clock is applied to this input to obtain serial data from the AD7894. A new serial data bit is clocked out on the falling edge of this serial clock. Data is guaranteed valid for 10 ns after this falling edge so data can be accepted on the falling edge when a fast serial clock is used. The serial clock input should be taken low at the end of the serial data transmission. 5 SDATA Serial Data Output. Serial data from the AD7894 is provided at this output. The serial data is clocked out by the falling edge of SCLK, but the data can also be read on the falling edge of SCLK. This is pos- sible because data bit N is valid for a specified time after the falling edge of SCLK (data hold time) (see Figure 5). Sixteen bits of serial data are provided as two leading zeroes followed by the 14 bits of conver- sion data. On the 16th falling edge of SCLK, the SDATA line is held for the data hold time and then disabled (three-stated). Output data coding is twos complement for the AD7894-10 and AD7894-3, and straight binary for the AD7894-2. 6 BUSY The BUSY pin is used to indicate when the part is doing a conversion. The BUSY pin will go high on the falling edge of CONVST and will return low when the conversion is complete. 7 CONVST Conversion Start. Edge-triggered logic input. On the falling edge of this input, the track/hold goes into its hold mode and conversion is initiated. If CONVST is low at the end of conversion, the part goes into power-down mode. In this case, the rising edge of CONVST will cause the part to begin waking up. 8 V Positive supply voltage, +5 V – 5%. DD 1.6mA PIN CONFIGURATION SOIC (SO-8) TO OUTPUT +1.6V PIN 50pF REF IN 1 8 VDD 400mA VIN 2 TAODP7 V8IE9W4 7 CONVST GND 3 (Not to Scale) 6 BUSY SCLK 4 5 SDATA Figure 1.Load Circuit for Access Time and Bus Relinquish Time –4– REV. 0

AD7894 TERMINOLOGY Relative Accuracy Signal to (Noise + Distortion) Ratio Relative accuracy or endpoint nonlinearity is the maximum This is the measured ratio of signal to (noise + distortion) at the deviation from a straight line passing through the endpoints of output of the A/D converter. The signal is the rms amplitude of the ADC transfer function. the fundamental. Noise is the rms sum of all nonfundamental Differential Nonlinearity signals up to half the sampling frequency (f /2), excluding dc. S This is the difference between the measured and the ideal 1␣LSB The ratio is dependent upon the number of quantization levels change between any two adjacent codes in the ADC. in the digitization process; the more levels, the smaller the quan- tization noise. The theoretical signal to (noise + distortion) ratio Positive Gain Error (AD7894-10) for an ideal N-bit converter with a sine wave input is given by: This is the deviation of the last code transition (01 . . . 110 to 01 . . . 111) from the ideal (4 · VREF – 1 LSB) after the Signal to (Noise + Distortion) = (6.02␣N + 1.76) dB Bipolar Zero Error has been adjusted out. Thus for a 14-bit converter, this is 86.04 dB. Positive Gain Error (AD7894-3) Total Harmonic Distortion This is the deviation of the last code transition (01 . . . 110 to Total harmonic distortion (THD) is the ratio of the rms sum of 01 . . . 111) from the ideal (VREF – 1 LSB) after the Bipolar harmonics to the fundamental. For the AD7894, it is defined as: Zero Error has been adjusted out. Positive Gain Error (AD7894-2) THD(dB)=20log V22+V32+V42+V52+V62 This is the deviation of the last code transition (11 . . . 110 to V 11 . . . 111) from the ideal (VREF – 1 LSB) after the Unipolar 1 Offset Error has been adjusted out. where V is the rms amplitude of the fundamental and V , V , 1 2 3 V , V and V are the rms amplitudes of the second through the Bipolar Zero Error (AD7894-10, AD7894-3) 4 5 6 This is the deviation of the midscale transition (all 0s to all 1s) sixth harmonics. from the ideal 0 V (GND). Peak Harmonic or Spurious Noise Unipolar Offset Error (AD7894-2) Peak harmonic or spurious noise is defined as the ratio of the This is the deviation of the first code transition (00 . . . 000 to rms value of the next largest component in the ADC output 00 . . . 001) from the ideal 1 LSB. spectrum (up to f /2 and excluding dc) to the rms value of the S fundamental. The value of this specification is normally deter- Negative Gain Error (AD7894-10) mined by the largest harmonic in the spectrum, but for parts This is the deviation of the first code transition (10 . . . 000 to where the harmonics are buried in the noise floor, it will be a 10 . . . 001) from the ideal (–4 · VREF + 1 LSB) after Bipolar noise peak. Zero Error has been adjusted out. Intermodulation Distortion Negative Gain Error (AD7894-3) With inputs consisting of sine waves at two frequencies, fa and This is the deviation of the first code transition (10 . . . 000 to fb, any active device with nonlinearities will create distortion 10 . . . 001) from the ideal (– VREF + 1 LSB) after Bipolar products at sum and difference frequencies of mfa – nfb where Zero Error has been adjusted out. m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which Track/Hold Acquisition Time neither m nor n is equal to zero. For example, the second order Track/Hold acquisition time is the time required for the output terms include (fa + fb) and (fa – fb), while the third order terms of the track/hold amplifier to reach its final value, within include (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (fa – 2 fb). – 1/2␣LSB, after the end of conversion (the point at which the The AD7894 is tested using two input frequencies. In this case, track/hold returns to track mode). It also applies to situations the second and third order terms are of different significance. where there is a step input change on the input voltage applied The second order terms are usually distanced in frequency from to the V input of the AD7894. This means that the user must IN the original sine waves, while the third order terms are usually at wait for the duration of the track/hold acquisition time after the a frequency close to the input frequencies. As a result, the second end of conversion or after a step input change to V before IN and third order terms are specified separately. The calculation starting another conversion, to ensure that the part operates to of the intermodulation distortion is as per the THD specification specification. where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dBs. REV. 0 –5–

AD7894 CONVERTER DETAILS input is benign, with no dynamic charging currents as the resis- The AD7894 is a fast, 14-bit single supply A/D converter. It tor stage is followed by a high input impedance stage of the provides the user with signal scaling, track/hold, A/D converter track/hold amplifier. For the AD7894-10, R1 = 8 kW , R2 = 2 kW and serial interface logic functions on a single chip. The A/D and R3 = 2 kW . For the AD7894-3, R1 = R2 = 2 kW and R3 converter section of the AD7894 consists of a conventional is open circuit. The current flowing in the analog input is di- successive-approximation converter based around an R-2R rectly related to the analog input voltage. The maximum input ladder structure. The signal scaling on the AD7894-10 and current flows when the analog input is at negative full scale. AD7894-3 allows the part to handle – 10 V and – 2.5 V input For the AD7894-10 and AD7894-3, the designed code transi- signals respectively while operating from a single +5␣V supply. tions occur on successive integer LSB values (i.e., 1 LSB, 2 LSBs, The AD7894-2 accepts an analog input range of 0 V to +2.5 V. 3 LSBs . . .). Output coding is twos complement binary with The part requires an external +2.5 V reference. The reference 1LSB = FS/16384. The ideal input/output transfer function for input to the part is buffered on-chip. The AD7894 has two the AD7894-10 and AD7894-3 is shown in Table I. operating modes, the high sampling mode and the “auto-sleep” mode where the part automatically goes into sleep after the end Table I. Ideal Input/Output Code Table for the AD7894-10/ of conversion. These modes are discussed in more detail in the AD7894-3 Timing and Control Section. A major advantage of the AD7894 is that it provides all of the Digital Output above functions in an 8-lead SOIC package. This offers the user Analog Inputl Code Transition considerable space saving advantages over alternative solutions. +FSR/2 – 1 LSB2 011 . . . 110 to 011 . . . 111 The AD7894 typically consumes only 20␣mW, making it ideal +FSR/2 – 2 LSBs 011 . . . 101 to 011 . . . 110 for battery powered applications. +FSR/2 – 3 LSBs 011 . . . 100 to 011 . . . 101 Conversion is initiated on the AD7894 by pulsing the CONVST GND + 1 LSB 000 . . . 000 to 000 . . . 001 input. On the falling edge of CONVST, the on-chip track/hold GND 111 . . . 111 to 000 . . . 000 goes from track-to-hold mode and the conversion sequence is GND – 1 LSB 111 . . . 110 to 111 . . . 111 started. The conversion clock for the part is generated internally using a laser-trimmed clock oscillator circuit. Conversion time for –FSR/2 + 3 LSBs 100 . . . 010 to 100 . . . 011 the AD7894 is 5␣m s in the high sampling mode (10 m s for the auto –FSR/2 + 2 LSBs 100 . . . 001 to 100 . . . 010 sleep mode), and the track/hold acquisition time is 0.35␣m s. To –FSR/2 + 1 LSB 100 . . . 000 to 100 . . . 001 obtain optimum performance from the part, the read operation NOTES should not occur during the conversion or during 250 ns prior 1FSR is full-scale range = 20 V (AD7894-10) and = 5 V (AD7894-3) with to the next conversion. This allows the part to operate at through- REF IN = +2.5 V. put rates up to 160 kHz and achieve data sheet specifications. 21 LSB = FSR/16384 = 1.22 mV (AD7894-10) and 0.3 mV (AD7894-3) with REF IN = +2.5 V. The analog input section for the AD7894-2 contains no biasing CIRCUIT DESCRIPTION resistors and the V pin drives the input directly to the track/ Analog Input Section IN The AD7894 is offered as three part types, the AD7894-10, hold amplifier. The analog input range is 0 V to +2.5 V into a which handles a – 10 V input voltage range, the AD7894-3, high impedance stage with an input current of less than 500␣nA. which handles input voltage range – 2.5 V and the AD7894-2, This input is benign, with no dynamic charging currents. Once again, the designed code transitions occur on successive integer which handles a 0␣V to +2.5␣V input voltage range. LSB values. Output coding is straight (natural) binary with 1 LSB = FS/16384 = 2.5 V/16384 = 0.15 mV. Table II shows the ideal input/output transfer function for the AD7894-2. TO ADC REFERENCE Table II. Ideal Input/Output Code Table for AD7894-2 REF IN CIRCUITRY R2 Digital Output R1 Analog Input1 Code Transition VIN TCOO MINPTAERRANTAOLR TRACK/ +FSR – 1 LSB2 111 . . . 110 to 111 . . . 111 R3 HOLD +FSR – 2 LSB 111 . . . 101 to 111 . . . 110 GND +FSR – 3 LSB 111 . . . 100 to 111 . . . 101 AD7894-10/AD7894-3 GND + 3 LSB 000 . . . 010 to 000 . . . 011 GND + 2 LSB 000 . . . 001 to 000 . . . 010 GND + 1 LSB 000 . . . 000 to 000 . . . 001 Figure 2.AD7894-10/AD7894-3 Analog Input Structure Figure 2 shows the analog input section for the AD7894-10 and NOTES 1FSR is full-scale range and is 2.5 V for AD7894-2 with VREF = +2.5 V. AD7894-3. The analog input range of the AD7894-10 is – 10 V 21 LSB = FSR/16384 and is 0.15 mV for AD7894-2 with VREF = +2.5 V. and the analog input range for the AD7894-3 is – 2.5 V. This –6– REV. 0

AD7894 Track/Hold Section the next falling edge of CONVST to optimize the settling of the The track/hold amplifier on the analog input of the AD7894 track/hold amplifier before the next conversion is initiated. allows the ADC to accurately convert an input sine wave of full- With the serial clock frequency at its maximum of 16␣MHz, the scale amplitude to 14-bit accuracy. The input bandwidth of the achievable throughput rate for the part is 5␣m s (conversion track/hold is greater than the Nyquist rate of the ADC, even time) plus 1.0␣m s (read time) plus 250␣ns (quiet time). This when the ADC is operated at its maximum throughput rate of results in a minimum throughput time of 6.25␣m s (equivalent to 160 kHz (i.e., the track/hold can handle input frequencies in a throughput rate of 160 kHz). A serial clock of less than 16MHz excess of 100 kHz). can be used, but this will in turn mean that the throughput time will increase. The track/hold amplifier acquires an input signal to 14-bit accu- racy in less than 0.35␣m s. The operation of the track/hold is The read operation consists of 16 serial clock pulses to the essentially transparent to the user. With the high sampling output shift register of the AD7894. After 16 serial clock pulses operating mode the track/hold amplifier goes from its tracking the shift register is reset and the SDATA line is three-stated. If mode to its hold mode at the start of conversion (i.e., the falling there are more serial clock pulses after the 16th clock, the shift edge of CONVST). The aperture time for the track/hold (i.e., register will be moved on past its reset state. However, the shift the delay time between the external CONVST signal and the register will be reset again on the falling edge of the CONVST track/hold actually going into hold) is typically 15␣ns. At the signal to ensure that the part returns to a known state every end of conversion (on the falling edge of BUSY) the part re- conversion cycle. As a result, a read operation from the output turns to its tracking mode. The acquisition time of the track/ register should not straddle across the falling edge of CONVST hold amplifier begins at this point. For the auto shutdown mode, as the output shift register will be reset in the middle of the the rising edge of CONVST wakes up the part and the track read operation and the data read back into the microprocessor and hold amplifier goes from its tracking mode to its hold mode will appear invalid. 5 m s after the rising edge of CONVST (provided that the OPERATING MODES CONVST high time is less than 5 m s). Once again the part re- Mode 1 Operation (High Sampling Performance) turns to its tracking mode at the end of conversion when the The timing diagram in Figure 3 is for optimum performance in BUSY signal goes low. operating Mode 1 where the falling edge of CONVST starts Reference Input conversion and puts the Track/Hold amplifier into its hold The reference input to the AD7894 is buffered on-chip with a mode. This falling edge of CONVST also causes the BUSY maximum reference input current of 1␣m A. The part is specified signal to go high to indicate that a conversion is taking place. with a +2.5 V reference input voltage. Errors in the reference The BUSY signal goes low when the conversion is complete, source will result in gain errors in the AD7894’s transfer func- which is 5 m s max after the falling edge of CONVST and new tion and will add to the specified full-scale errors on the part. data from this conversion is available in the output register of Suitable reference sources for the AD7894 include the AD780 the AD7894. A read operation accesses this data. This read and AD680 precision +2.5 V references. operation consists of 16 clock cycles and the length of this read operation will depend on the serial clock frequency. For the Timing and Control Section fastest throughput rate (with a serial clock of 16 MHz) the read Figure 3 shows the timing and control sequence required to operation will take 1.0 m s. The read operation must be com- obtain optimum performance from the AD7894. In the se- plete at least 250 ns before the falling edge of the next CONVST quence shown, conversion is initiated on the falling edge of and this gives a total time of 6.25 m s for the full throughput CONVST and new data from this conversion is available in the output register of the AD7894 5␣m s later. Once the read opera- time (equivalent to 160 kHz). This mode of operation should be used for high sampling applications. tion has taken place, a further 250␣ns should be allowed before t1 = 40ns MIN CONVST BUSY 250ns MIN SCLK tCONVERT = 5ms CONVERSION IS CONVERSION SERIAL READ READ OPERATION OUTPUT INITIATED; ENDS OPERATION SHOULD END SERIAL TRACK/HOLD 5ms LATER 250ns PRIOR TO SHIFT GOES INTO HOLD NEXT FALLING REGISTER EDGE OF CONVST IS RESET Figure 3.Mode 1 Timing Operation Diagram for High Sampling Performance REV. 0 –7–

AD7894 CONVST BUSY 250ns MIN SCLK tCONVERT = 10ms PART CONVERSION CONVERSION SERIAL READ READ OPERATION OUTPUT WAKES IS INITIATED; ENDS OPERATION SHOULD END 250ns SERIAL SHIFT UP TRACK/HOLD 10ms LATER PRIOR TO NEXT REGISTER GOES INTO RISING EDGE OF IS RESET HOLD CONVST Figure 4.Mode 2 Timing Diagram Where Automatic Sleep Function is Initiated t2 = t3 = 31.25ns MIN, t4 = 60ns MAX, t5 = 10ns MIN, t6 = 20ns MAX @ 5V, A, B, VERSIONS t t 2 3 SCLK (I/P) 1 2 3 4 15 16 t4 t5 THtR6EE- THREE-STATE 2 LEADING STATE DOUT (O/P) ZEROS DB13 DB12 DB0 Figure 5.Data Read Operation Mode 2 Operation (Auto Sleep After Conversion) easy-to-use interface to most microcontrollers, DSP processors The timing diagram in Figure 4 is for optimum performance in and shift registers. operating Mode 2, where the part automatically goes into sleep Figure 5 shows the timing diagram for the read operation to the mode once BUSY goes low, after conversion and “wakes up” AD7894. The serial clock input (SCLK) provides the clock before the next conversion takes place. This is achieved by keep- source for the serial interface. Serial data is clocked out from ing CONVST low at the end of conversion, whereas it was high the SDATA line on the falling edge of this clock and is valid on at the end of conversion for Mode 1 Operation. The rising edge both the rising and falling edges of SCLK. The advantage of of CONVST “wakes up” the AD7894. This wake-up time is having the data valid on both the rising and falling edges of the typically 5 m s and is controlled internally by a monostable cir- SCLK is to give the user greater flexibility in interfacing to the cuit. While the AD7894 is waking up there is some digital activ- part and so a wider range of microprocessor and microcontrol- ity internal to the part. If the falling edge of CONVST (putting ler interfaces can be accommodated. This also explains the two the track/hold amplifier into hold mode) should occur during timing figures, t and t , that are quoted on the diagram. The this digital activity, noise will be injected into the track/hold 4 5 time t specifies how long after the falling edge of the SCLK the amplifier resulting in a poor conversion. For optimum results 4 next data bit becomes valid, whereas the time t specifies for the CONVST pulse should be between 40 ns and 2 m s or greater 5 how long after the falling edge of the SCLK the current data bit than 6 m s in width. The narrower pulse will allow a system to is valid. The first leading zero is clocked out on the first rising instruct the AD7894 to begin waking up and perform a conver- edge of SCLK. Note that the first zero will be valid on the first sion when ready, whereas the pulse greater than 6 m s will give falling edge of SCLK even though the data access time is speci- control over when the sampling instant takes place. Note that fied at 60 ns for the other bits. The reason for this is that the the 10 m s wake-up time shown in Figure 4 is for a CONVST pulse first bit will be clocked out faster than the other bits is due to less than 2 m s. If a CONVST pulse greater than 6 m s is used, the the internal architecture of the part. Sixteen clock pulses must conversion will not complete for a further 5 m s after the falling edge be provided to the part to access to full conversion result. The of CONVST. Even though the part is in sleep mode, data can still AD7894 provides two leading zeros followed by the 14-bit be read from it. The read operation consists of 16 clock cycles as in conversion result starting with the MSB (DB13). The last data Mode 1 Operation. For the fastest serial clock of 16 MHz, the read bit to be clocked out on the penultimate falling clock edge is the operation will take 1.0 m s and this must be complete at least 250 ns LSB (DB0). On the 16th falling edge of SCLK the LSB (DB0) before the falling edge of the next CONVST, to allow the track/ will be valid for a specified time to allow the bit to be read on hold amplifier to have enough time to settle. This mode is very the falling edge of the SCLK and then the SDATA line is dis- useful when the part is converting at a slow rate, as the power abled (three-stated). After this last bit has been clocked out, consumption will be significantly reduced from that of Mode 1 the SCLK input should return low and remain low until the Operation. next serial data read operation. If there are extra clock pulses Serial Interface after the 16th clock, the AD7894 will start over again with The serial interface to the AD7894 consists of just three wires, a outputting data from its output register and the data bus will serial clock input (SCLK) and the serial data output (SDATA) no longer be three-stated even when the clock stops. Provided and a conversion status output (BUSY). This allows for an the serial clock has stopped before the next falling edge of –8– REV. 0

AD7894 CONVST, the AD7894 will continue to operate correctly The serial clock rate from the 8X51/L51 is limited to signifi- with the output shift register being reset on the falling edge of cantly less than the allowable input serial clock frequency with CONVST. However, the SCLK line must be low when CONVST which the AD7894 can operate. As a result, the time to read goes low in order to reset the output shift register correctly. data from the part will actually be longer than the conversion The serial clock input does not have to be continuous during the time of the part. This means that the AD7894 cannot run at its serial read operation. The 16 bits of data (two leading zeros and maximum throughput rate when used with the 8X51/L51. 14-bit conversion result) can be read from the AD7894 in a number of bytes. The AD7894 counts the serial clock edges to know which bit P1.2 OR INT1 BUSY from the output register should be placed on the SDATA out- AD7894 8X51/L51 put. To ensure that the part does not lose synchronization, the P3.0 SDATA serial clock counter is reset on the falling edge of the CONVST input provided the SCLK line is low. The user should ensure that the SCLK line remains low until the end of the conversion. P3.1 SCLK When the conversion is complete, BUSY goes low, the output register will be loaded with the new conversion result and can be Figure 6.AD7894 to 8X51/L51 Interface read from with 16 clock cycles of SCLK. AD7894 to 68HC11/L11 Interface MICROPROCESSOR/MICROCONTROLLER INTERFACE An interface circuit between the AD7894 and the 68HC11/L11 The AD7894 provides a two-wire serial interface that can be microcontroller is shown in Figure 7. For the interface shown, used for connection to the serial ports of DSP processors and the 68L11 SPI port is used and the 68L11 is configured in its microcontrollers. Figures 6 through 9 show the AD7894 single-chip mode. The 68L11 is configured in the master mode interfaced to a number of different microcontrollers and DSP with its CPOL bit set to a logic zero and its CPHA bit set to a processors. The AD7894 accepts an external serial clock and logic one. As with the previous interface, the diagram shows the as a result, in all interfaces shown here, the processor/controller simplest form of the interface where the AD7894 is the only part is configured as the master, providing the serial clock, with connected to the serial port of the 68L11 and therefore no de- the AD7894 being the slave in the system. The BUSY signal coding of the serial read operations is required. need not be used for a two-wire interface if the read can be Once again, to select the AD7894 in systems where more than timed to occur 5m s after the start of conversion (assuming one device is connected to the 68HC11’s serial port, a port bit, Mode 1 operation). configured as an output from one of the 68HC11’s parallel AD7894 to 8X51/L51 Interface ports, can be used to gate on or off the serial clock to the AD7894. Figure 6 shows an interface between the AD7894 and the A simple AND function on this port bit and the serial clock 8X51/L51 microcontroller. The 8X51/L51 is configured for its from the 68L11 will provide this function. The port bit should Mode 0 serial interface mode. The diagram shows the simplest be high to select the AD7894 and low when it is not selected. form of the interface where the AD7894 is the only part con- The end of conversion is monitored by using the BUSY signal, nected to the serial port of the 8X51/L51 and, therefore, no which is shown in the interface diagram of Figure 7. With the decoding of the serial read operations is required. BUSY line from the AD7894 connected to the Port PC2 of the To select the AD7894 in systems where more than one device is 68HC11/L11 the BUSY line can be polled by the 68HC11/L11. connected to the 8X51/L51’s serial port, a port bit, configured The BUSY line can be connected to the IRQ line of the 68HC11/ as an output from one of the 8X51/L51’s parallel ports, can be L11 if an interrupt driven system is preferred. These two op- used to gate on or off the serial clock to the AD7894. A simple tions are shown in the diagram. AND function on this port bit and the serial clock from the The serial clock rate from the 68HC11/L11 is limited to signifi- 8X51/L51 will provide this function. The port bit should be cantly less than the allowable input serial clock frequency with high to select the AD7894 and low when it is not selected. which the AD7894 can operate. As a result, the time to read The end of conversion can be monitored by using the BUSY data from the part will be longer than the conversion time of the signal, which is shown in the interface diagram of Figure 6. part. This means that the AD7894 cannot run at its maximum With the BUSY line from the AD7894 connected to the Port throughput rate when used with the 68HC11/L11. P1.2 of the 8X51/L51 the BUSY line can be polled by the 8X51/L51. The BUSY line can be connected to the INT1 line of the 8X51/L51 if an interrupt driven system is preferred. PC2 OR IRQ BUSY These two options are shown on the diagram. AD7894 68HC11/L11 Note also that the AD7894 outputs the MSB first during a read SCK SCLK operation while the 8X51/L51 expects the LSB first. Therefore, the data that is read into the serial buffer needs to be rearranged before the correct data format from the AD7894 appears in the MISO SDATA accumulator. Figure 7.AD7894 to 68HC11/L11 Interface REV. 0 –9–

AD7894 AD7894 to ADSP-2101/5 Interface The BUSY line from the AD7894 is connected to the MODA/ An interface circuit between the AD7894 and the ADSP-2101/5 IRQA input of the DSP56002/L002 so that an interrupt will be DSP processor is shown in Figure 8. In the interface shown, the generated at the end of conversion. This ensures that the read RFS1 output from the ADSP-2101/5s SPORT1 serial port is operation will take place after conversion is finished. used to gate the serial clock (SCLK1) of the ADSP-2101/5 before it is applied to the SCLK input of the AD7894. The RFS1 output is configured for active high operation. The BUSY line from the AD7894 is connected to the IRQ2 line of the MODA/IRQA BUSY ADSP-2101/5 so that at the end of conversion an interrupt is DSP56002/L002 AD7894 generated telling the ADSP-2101/5 to initiate a read operation. SCK SCLK The interface ensures a noncontinuous clock for the AD7894’s serial clock input, with only 16 serial clock pulses provided and SDR SDATA the serial clock line of the AD7894 remaining low between data transfers. The SDATA line from the AD7894 is connected to the DR1 line of the ADSP-2101/5’s serial port. Figure 9.AD7894 to DSP56002/L002 Interface The timing relationship between the SCLK1 and RFS1 outputs of the ADSP-2101/5 are such that the delay between the rising AD7894 PERFORMANCE edge of the SCLK1 and the rising edge of an active high RFS1 Linearity is up to 30␣ns. There is also a requirement that data must be set The linearity of the AD7894 is determined by the on-chip up 10␣ns prior to the falling edge of the SCLK1 to be read cor- 14-bit D/A converter. This is a segmented DAC which is laser rectly by the ADSP-2101/5. The data access time for the AD7894 trimmed for 14-bit integral linearity and differential linearity. is 60␣ns (A, B versions) from the rising edge of its SCLK input. Typical relative accuracy numbers for the part are – 1/2␣LSB Assuming a 10␣ns propagation delay through the external AND while the typical DNL errors are – 1/3␣LSB. gate, the high time of the SCLK1 output of the ADSP-2105 Noise must be ‡ (30 + 60 + 10 + 10)␣ns, i.e., ‡ 110 ns. This means In an A/D converter, noise exhibits itself as code uncertainty in that the serial clock frequency with which the interface of Figure dc applications and as the noise floor (in an FFT, for example) 8 can work is limited to 4.5␣MHz. in ac applications. In a sampling A/D converter like the AD7894, Another alternative scheme is to configure the ADSP-2101/5 all information about the analog input appears in the baseband such that it accepts an external noncontinuous serial clock. In from dc to 1/2 the sampling frequency. The input bandwidth of this case, an external noncontinuous serial clock is provided that the track/hold exceeds the Nyquist bandwidth, so an antialiasing drives the serial clock inputs of both the ADSP-2101/5 and the filter should be used to remove unwanted signals above fS/2 in AD7894. In this scheme, the serial clock frequency is limited to the input signal in applications where such signals exist. the processor’s cycle rate, up to a maximum of 13.8 MHz. Figure 10 shows a histogram plot for 8192 conversions of a dc input using the AD7894. The analog input was set at the center of a code transition. It can be seen that almost all the codes IRQ2 BUSY appear in the one output bin indicating very good noise perfor- mance from the ADC. RFS1 AD7894 ADSP-2101/5 SCLK SCLK1 6000 DR1 SDATA 5000 Figure 8.AD7894 to ADSP-2101/5 Interface 4000 S AD7894 to DSP56002/L002 Interface NT U Figure 9 shows an interface circuit between the AD7894 and the O 3000 C DSP56002/L002 DSP processor. The DSP56002/L002 is configured for normal-mode asynchronous operation with gated 2000 clock. It is also set up for a 16-bit word with SCK as gated clock output. In this mode, the DSP56002/L002 provides 16 1000 serial clock pulses to the AD7894 in a serial read operation. The DSP56002/L002 assumes valid data on the first falling 0 97 98 99 100 101 102 103 edge of SCK so the interface is simply three-wire as shown in ADC CODE Figure 9. Figure 10. Histogram of 8192 Conversions of a DC Input –10– REV. 0

AD7894 Dynamic Performance (Mode 1 Only) Power Considerations With a conversion time of 5 m s, the AD7894 is ideal for wide In the automatic power-down mode the part may be operated at bandwidth signal processing applications. These applications a sample rate that is considerably less than 160 kHz. In this require information on the ADC’s effect on the spectral con- case, the power consumption will be reduced and will depend tent of the input signal. Signal to (Noise + Distortion), Total on the sample rate. Figure 13 shows a graph of the power con- Harmonic Distortion, Peak Harmonic or Spurious Noise and sumption versus sampling rates from 1 Hz to 100 kHz in the Intermodulation Distortion are all specified. Figure 11 shows a automatic power-down mode. The conditions are 5 V supply typical FFT plot of a 10 kHz, – 10␣V input after being digitized +25(cid:176) C. The SCLK pin was held low and no data was read from by the AD7894-10 operating at a 160 kHz sampling rate. The the part. signal to (noise + distortion) ratio is 80.24 dB and the total harmonic distortion is –96.35dB. 100 The formula for signal to (noise + distortion) ratio (see Ter- minology section) is related to the resolution or number of bits in the converter. Rewriting the formula, below, gives a mea- sure of performance expressed in effective number of bits (N): 10 W m N =(SNR–1.76) ER – 6.02 OW P where SNR is Signal to (Noise + Distortion) Ratio. 1 0 fS = 160kHz –20 FSINNR = =1 08k0H.2z4dB 0.1 THD = –96.35dB 1 10 100 1000 10000 100000 SAMPLING FREQUENCY – Hz –40 Figure 13.Power vs. Sampling Rate in Automatic Power- –60 Down Mode s B d –80 82 fS = 160kHz –100 FIN = 10kHz –120 81 –140 dB 0 10 20 30 40 50 60 70 80 – FREQUENCY – kHz D 80 + R Figure 11.AD7894 FFT Plot N S The effective number of bits for a device can be calculated from its measured signal to (noise + distortion) ratio. Figure 12 79 shows a typical plot of effective number of bits versus frequency for the AD7894 from dc to f /2. The sampling fre- SAMPLING quency is 160 kHz. The plot shows that the AD7894 converts 78 –40 –20 0 20 40 60 80 an input sine wave of 10␣kHz to an effective numbers of bits of TEMPERATURE – 8C 13.00, which equates to a signal to (noise + distortion) level of Figure 14.SNR + D vs. Temperature 80.02 dB. 14 100 90 13 80 70 NOBs 12 D – dB 6500 E H 11 T 40 30 10 20 10 9 0 10 100 1000 10 100 1000 FREQUENCY – kHz FREQUENCY – kHz Figure 12.Effective Number of Bits vs. Frequency Figure 15.THD vs. Frequency REV. 0 –11–

AD7894 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead Narrow Body SOIC (SO-8) 8 0.1968 (5.00) 9 0.1890 (4.80) –9/ 8 – 2 8 5 4 0.1574 (4.00) 0.2440 (6.20) 3 0.1497 (3.80) 1 4 0.2284 (5.80) C3 PIN 1 0.0688 (1.75) 0.0196 (0.50) 0.0098 (0.25) 0.0532 (1.35) 0.0099 (0.25)3 458 0.0040 (0.10) 88 SEPALTAINNGE 0(B.10.S52C070) 00..00119328 ((00..4395)) 00..00009785 ((00..2159)) 08 00..00510600 ((10..2471)) A. S. U. N D I E T N RI P –12– REV. 0

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD7894ARZ-2 AD7894ARZ-3 AD7894BRZ-3 AD7894ARZ-2REEL7 AD7894AR-10REEL7 AD7894ARZ-3REEL AD7894BRZ-10 AD7894ARZ-3REEL7 AD7894AR-10 AD7894ARZ-2REEL AD7894ARZ-10 AD7894ARZ-10REEL7 AD7894BRZ-10REEL7