Low Power, 16-/24-Bit Sigma-Delta ADC for Bridge Sensors Low Power, 16-/24-Bit Data Sheet AD7796/AD7797 FEATURES FUNCTIONAL BLOCK DIAGRAM RMS noise: 65 nV GND AVDD REFIN(+) REFIN(–) Instrumentation amp AD7796:16-BITADC AVDD AD7797:24-BITADC Temperature sensor Internal clock oscillator AIN(+) SERIAL DOUT/RDY Simultaneous 50 Hz/60 Hz rejection AIN(–) MUX ×128 AΣD-ΔC INCTOEANRNTFDRAOCLE DSCINLK Update rate range: 4.17 Hz to 123 Hz LOGIC CS Current: 250 µA typ GND REFERENCE Power-down: 1 µA AD7796/ SETNEMSOPR INCTLEORCNKAL DVDD P–4o0w°eCr t sou +p8p5ly°C r atnemgep: e2r.a7t Vu rteo r5a.n2g5e V AD7797 CLK 06083-001 Independent interface power supply Figure 1. 16-lead TSSOP INTERFACE 3-wire serial SPI, QSPI™, MICROWIRE, and DSP compatible Schmitt trigger on SCLK APPLICATIONS Weigh scales Strain gages Industrial process control Instrumentation Portable instrumentation GENERAL DESCRIPTION The AD7796/AD7797 are complete, analog front ends for high The devices can be operated with the internal clock or an external precision, bridge sensor applications such as weigh scales. The clock. The output data rate from the devices is software- AD7796/AD7797 contain a Σ-∆ ADC capable of 16-/24-bit programmable and can be varied from 4.17 Hz to 123 Hz. resolution, respectively. The on-chip instrumentation amplifier The AD7796/AD7797 operate with a power supply from 2.7 V has a fixed gain of 128, allowing small amplitude signals such as to 5.25 V. Each device consumes a current of 250 µA typical and those from bridge sensors to be directly interfaced to the ADC. is housed in a 16-lead TSSOP. Each device has one differential input and contains a temperature sensor that is internally connected to the ADC. This sensor can be used to perform temperature compensation of the bridge. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2006–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD7796/AD7797 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ID Register................................................................................... 14 Interface ............................................................................................. 1 Offset Register ............................................................................ 15 Applications ....................................................................................... 1 Full-Scale Register ...................................................................... 15 Functional Block Diagram .............................................................. 1 ADC Circuit Information .............................................................. 16 General Description ......................................................................... 1 Overview ..................................................................................... 16 Revision History ............................................................................... 2 Digital Interface .......................................................................... 17 Specifications ..................................................................................... 3 Circuit Description......................................................................... 20 Timing Characteristics ..................................................................... 5 Analog Input Channel ............................................................... 20 Timing Diagrams .......................................................................... 6 Bipolar/Unipolar Configuration .............................................. 20 Absolute Maximum Ratings ............................................................ 7 Data Output Coding .................................................................. 20 Thermal Resistance ...................................................................... 7 Reference ..................................................................................... 20 ESD Caution .................................................................................. 7 Reset ............................................................................................. 21 Pin Configuration and Function Descriptions ............................. 8 Burnout Currents ....................................................................... 21 RMS Noise and Resolution Specifications .................................... 9 AV Monitor ............................................................................. 21 DD Typical Performance Characteristics ........................................... 10 Temperature Monitor ................................................................ 21 On-Chip Registers .......................................................................... 11 Calibration ................................................................................... 21 Communication Register .......................................................... 11 Grounding and Layout .............................................................. 22 Status Register ............................................................................. 12 Applications Information .............................................................. 23 Mode Register ............................................................................. 12 Weigh Scales ................................................................................ 23 Configuration Register .............................................................. 14 Outline Dimensions ....................................................................... 24 Data Register ............................................................................... 14 Ordering Guide .......................................................................... 24 REVISION HISTORY 3/16—Rev. A to Rev. B Changes to RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80 Section and Table 11 ....................................................................... 12 8/06—Rev. 0 to Rev. A Changes to Table 1 ............................................................................ 3 Changes to Figure 5 .......................................................................... 8 Changes to Table 14 ........................................................................ 13 7/06—Revision 0: Initial Version Rev. B | Page 2 of 24

Data Sheet AD7796/AD7797 SPECIFICATIONS AV = 2.7 V to 5.25 V, DV = 2.7 V to 5.25 V, GND = 0 V, all specifications T to T , unless otherwise noted. DD DD MIN MAX Table 1. Parameter AD7796B/AD7797B1 Unit Test Conditions/Comments ADC CHANNEL Output Update Rate 4.17 to 123 Hz nom No Missing Codes2 24 Bits min AD7797 only 16 Bits min AD7796 only Resolution See Table 7 and Table 8 RMS Noise and Update Rates See Table 6 Integral Nonlinearity ±10 ppm of FSR typ Offset Error3, 4 ±1 µV typ Offset Error Drift vs. Temperature4 ±10 nV/°C typ Full-Scale Error3, 4, 5 ±10 µV typ Gain Drift vs. Temperature4 ±3 ppm/°C typ Power Supply Rejection 90 dB min AIN = 1 V/128 ANALOG INPUTS Differential Input Voltage Ranges ±V /128 V nom V = REFIN(+) – REFIN(–) REF REF Absolute AIN Voltage Limits2 GND + 300 mV V min AV − 1.1 V max DD Common-Mode Voltage, V 0.5 V min V = (AIN(+) + AIN(–))/2 CM CM Analog Input Current Average Input Current2 ±250 pA max Update rate < 100 Hz Average Input Current Drift ±2 pA/°C typ Normal Mode Rejection2 Internal Clock At 50 Hz, 60 Hz 65 dB min 80 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 10106 At 50 Hz 80 dB min 90 dB typ, 50 ± 1 Hz, FS[3:0] = 10016 At 60 Hz 90 dB min 100 dB typ, 60 ± 1 Hz, FS[3:0] = 10006 External Clock At 50 Hz, 60 Hz 80 dB min 90 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 10106 At 50 Hz 94 dB min 100 dB typ, 50 ± 1 Hz, FS[3:0] = 10016 At 60 Hz 90 dB min 100 dB typ, 60 ± 1 Hz, FS[3:0] = 10006 Common-Mode Rejection At DC 90 dB min AIN = 7.81 mV At 50 Hz, 60 Hz2 90 dB min 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 10106 At 50 Hz, 60 Hz2 90 dB min 50 ± 1 Hz (FS[3:0] = 10016), 60 ± 1 Hz, FS[3:0] = 10006 REFERENCE External REFIN Voltage 2.5 V nom REFIN = REFIN(+) – REFIN(–) Reference Voltage Range2 0.1 V min AV V max DD Absolute REFIN Voltage Limits2 GND − 30 mV V min AV + 30 mV V max DD Average Reference Input Current 400 nA/V typ Average Reference Input Current Drift ±0.03 nA/V/°C typ Normal Mode Rejection Same as for analog inputs Common-Mode Rejection 100 dB typ TEMPERATURE SENSOR Accuracy ±2 °C typ Applies if user calibrates the temperature sensor Sensitivity 0.81 mV/°C typ Rev. B | Page 3 of 24

AD7796/AD7797 Data Sheet Parameter AD7796B/AD7797B1 Unit Test Conditions/Comments INTERNAL/EXTERNAL CLOCK Internal Clock Frequency2 64 ± 3% kHz min/max Duty Cycle 50:50 % typ External Clock Frequency 64 kHz nom A 128 kHz clock can be used if the divide by 2 function is used (Bit CLK1 = CLK0 = 1) Duty Cycle 45:55 to 55:45 % typ Applies for external 64 kHz clock (a 128 kHz clock can have a less stringent duty cycle) LOGIC INPUTS CS2 Input Low Voltage, V 0.8 V max DV = 5 V INL DD 0.4 V max DV = 3 V DD Input High Voltage, V 2.0 V min DV = 3 V or 5 V INH DD SCLK, CLK, and DIN (Schmitt-Triggered Input)2 V(+) 1.4/2 V min/V max DV = 5 V T DD V(–) 0.8/1.7 V min/V max DV = 5 V T DD V(+) − V(–) 0.1/0.17 V min/V max DV = 5 V T T DD V(+) 0.9/2 V min/V max DV = 3 V T DD V(–) 0.4/1.35 V min/V max DV = 3 V T DD VT(+) − VT(–) 0.06/0.13 V min/V max DVDD = 3 V Input Currents ±10 µA max V = DV or GND IN DD Input Capacitance 10 pF typ All digital inputs LOGIC OUTPUTS (INCLUDING CLK) Output High Voltage, V 2 DV − 0.6 V min DV = 3 V, I = 100 µA OH DD DD SOURCE 4 V min DV = 5 V, I = 200 µA DD SOURCE Output Low Voltage, V 2 0.4 V max DV = 3 V, I = 100 µA OL DD SINK 0.4 V max DV = 5 V, I = 1.6 mA (DOUT/RDY)/800 µA (CLK) DD SINK Floating-State Leakage Current ±10 µA max Floating-State Output Capacitance 10 pF typ Data Output Coding Offset Binary SYSTEM CALIBRATION2 Full-Scale Calibration Limit +1.05 × FS V max Zero-Scale Calibration Limit −1.05 × FS V min Input Span 0.8 × FS V min 2.1 × FS V max POWER REQUIREMENTS7 Power Supply Voltage AV – GND 2.7/5.25 V min/max DD DV – GND 2.7/5.25 V min/max DD Power Supply Currents I Current 325 µA max 250 µA typ at AV = 3 V, 280 µA typ at AV = 5 V DD DD DD I (Power-Down Mode) 1 µA max DD 1 Temperature range is –40°C to +85°C. 2 Specification is not production tested, but is supported by characterization data at initial product release. 3 Following a calibration, this error is in the order of the noise for the update rate selected. 4 Recalibration at any temperature removes these errors. 5 Full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (AVDD = 4 V, TA = 25°C). 6 FS[3:0] are the four bits used in the mode register to select the output word rate. 7 Digital inputs equal to DVDD or GND. Rev. B | Page 4 of 24

Data Sheet AD7796/AD7797 TIMING CHARACTERISTICS AV = 2.7 V to 5.25 V, DV = 2.7 V to 5.25 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DV , unless otherwise noted. DD DD DD Table 2. Parameter1, 2 Limit at T , T (B Version) Unit Test Conditions/Comments MIN MAX t 100 ns min SCLK high pulse width 3 t 100 ns min SCLK low pulse width 4 Read Operation t 0 ns min CS falling edge to DOUT/RDY active time 1 60 ns max DV = 4.75 V to 5.25 V DD 80 ns max DV = 2.7 V to 3.6 V DD t 3 0 ns min SCLK active edge to data valid delay4 2 60 ns max DV = 4.75 V to 5.25 V DD 80 ns max DV = 2.7 V to 3.6 V DD t 5, 6 10 ns min Bus relinquish time after CS inactive edge 5 80 ns max t 0 ns min SCLK inactive edge to CS inactive edge 6 t 10 ns min SCLK inactive edge to DOUT/RDY high 7 Write Operation t 0 ns min CS falling edge to SCLK active edge setup time4 8 t 30 ns min Data valid to SCLK edge setup time 9 t 25 ns min Data valid to SCLK edge hold time 10 t 0 ns min CS rising edge to SCLK edge hold time 11 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V. 2 See Figure 3 and Figure 4. 3 These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits. 4 SCLK active edge is falling edge of SCLK. 5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the devices and, as such, are independent of external bus loading capacitances. 6 RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high. Care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read only once. ISINK(1.6mAWITHDVDD=5V, 100µAWITHDVDD=3V) TO OUTPUT 1.6V PIN 50pF I1S0O0UµRACWE(IT20H0DµAVDWDIT=H3VD)VDD=5V, 06083-002 Figure 2. Load Circuit for Timing Characterization Rev. B | Page 5 of 24

AD7796/AD7797 Data Sheet TIMING DIAGRAMS CS(I) t1 t6 t5 DOUT/RDY(O) MSB LSB t2 t7 t3 SCLK(I) I= INPUT, O= OUTPUT t4 06083-003 Figure 3. Read Cycle Timing Diagram CS(I) t8 t11 SCLK(I) t9 t10 DIN(I) MSB LSB I= INPUT 06083-004 Figure 4. Write Cycle Timing Diagram Rev. B | Page 6 of 24

Data Sheet AD7796/AD7797 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. THERMAL RESISTANCE A θ is specified for the worst-case conditions, that is, a device JA Table 3. soldered in a circuit board for surface-mount packages. Parameter Rating AVDD to GND −0.3 V to +7 V Table 4. DVDD to GND −0.3 V to +7 V Package Type θJA θJC Unit Analog Input Voltage to GND −0.3 V to AV + 0.3 V DD TSSOP 128 14 °C/W Reference Input Voltage to GND −0.3 V to AV + 0.3 V DD Digital Input Voltage to GND −0.3 V to DV + 0.3 V DD Digital Output Voltage to GND −0.3 V to DVDD + 0.3 V ESD CAUTION AIN/Digital Input Current 10 mA Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. B | Page 7 of 24

AD7796/AD7797 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SCLK 1 16 DIN CLK 2 15 DOUT/RDY AD7796/ CS 3 AD7797 14 DVDD NC 4 TOPVIEW 13 AVDD (NottoScale) AIN(+) 5 12 GND AIN(–) 6 11 NC NC 7 10 REFIN(–) NC 8 9 REFIN(+) NC=NOCONNECT 06083-005 Figure 5. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 SCLK Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt- triggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a constant train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to or from the ADC in smaller batches of data. 2 CLK Clock In/Clock Out. The internal clock can be made available at this pin. Alternatively, the internal clock can be disabled, and the ADC can be driven by an external clock. This allows several ADCs to be driven from a common clock, allowing simultaneous conversions to be performed. 3 CS Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device. 4 NC No Connect. 5 AIN(+) Analog Input. AIN(+) is the positive terminal of the differential analog input pair AIN(+)/AIN(−). 6 AIN(−) Analog Input. AIN(−) is the negative terminal of the differential analog input pair AIN(+)/AIN(−). 7 NC No Connect. 8 NC No Connect. 9 REFIN(+) Positive Reference Input/Analog Input. An external reference can be applied between REFIN(+) and REFIN(–). REFIN(+) can lie anywhere between AV and GND + 0.1 V. The nominal reference voltage (REFIN(+) – REFIN(−)) DD is 2.5 V, but the devices function with a reference of 0.1 V to AV . DD 10 REFIN(−) Negative Reference Input/Analog Input. REFIN(−) is the negative reference input for REFIN. This reference input can lie anywhere between GND and AV − 0.1 V. DD 11 NC No Connect. 12 GND Ground Reference Point. 13 AV Supply Voltage, 2.7 V to 5.25 V. DD 14 DV Digital Interface Supply Voltage. The logic levels for the serial interface pins are related to this supply, which is DD between 2.7 V and 5.25 V. The DV voltage is independent of the voltage on AV ; therefore, AV can equal 5 DD DD DD V with DV at 3 V or vice versa. DD 15 DOUT/RDY Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. It functions as a serial data output pin to access the output shift register of the ADC. The output shift register can contain data from any of the on- chip data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available. With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the data/control word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. 16 DIN Serial Data Input. This serial data input accesses the input shift register on the ADC. Data in this shift register is transferred to the control registers within the ADC; the register selection bits of the communication register identify the appropriate register. Rev. B | Page 8 of 24

Data Sheet AD7796/AD7797 RMS NOISE AND RESOLUTION SPECIFICATIONS Table 6 shows the rms noise of the AD7796/AD7797 for some Table 7. Typical Resolution (Bits) vs. Output Update Rate for of the update rates. The numbers given are for the bipolar input the AD7797 Using a 2.5 V Reference range with an external 2.5 V reference. These numbers are typical Update Rate (Hz) Effective Bits (p-p) and are generated with a differential input voltage of 0 V. Table 7 4.17 19 (16.5) and Table 8 show the effective resolution, while the output 6.25 19 (16.5) peak-to-peak (p-p) resolution is shown in parentheses. It is 8.33 19 (16) important to note that the effective resolution is calculated using 10 18.5 (16) the rms noise, while the p-p resolution is based on the p-p 12.5 18.5 (16) noise. The p-p resolution represents the resolution for which 16.7 18.5 (15.5) there is no code flicker. These numbers are typical and are 33.2 18 (15) rounded to the nearest 0.5 LSB. 50 17.5 (15) 62 17.5 (14.5) Table 6. RMS Noise (µV) vs. Output Update Rate for the 123 16.5 (13.5) AD7796/AD7797 Using a 2.5 V Reference Update Rate (Hz) RMS Noise (µV) Table 8. Typical Resolution (Bits) vs. Output Update Rate for 4.17 0.065 the AD7796 Using a 2.5 V Reference 6.25 0.07 Update Rate (Hz) Effective Bits (p-p) 8.33 0.08 4.17 16 (16) 10 0.09 6.25 16 (16) 12.5 0.1 8.33 16 (16) 16.7 0.12 10 16 (16) 33.2 0.17 12.5 16 (16) 50 0.21 16.7 16 (15.5) 62 0.23 33.2 16 (15) 123 0.43 50 16 (15) 62 16 (14.5) 123 16 (13.5) Rev. B | Page 9 of 24

AD7796/AD7797 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 60 2.0 1.5 40 1.0 0.5 20 µV) µV) 0 ( ( 0 –0.5 –1.0 –20 –1.5 –40 –2.0 0 100 200 300 400SAM50P0LES600 700 800 900 1000 06083-006 0 100 200 300 400SAM50P0LES600 700 800 900 1000 06083-008 Figure 6. AD7797 Noise (VREF = AVDD, Update Rate = 16.7 Hz) Figure 8. AD7797 Noise (VREF = AVDD, Update Rate = 4.17 Hz) 17.5 35 15.0 30 12.5 25 E E C C N10.0 N 20 E E R R R R U U C 7.5 C 15 C C O O 5.0 10 2.5 5 0 0 8388485 8388550 8388600CODE8388650 8388700 8388744 06083-007 8388553 8388580 8388600CODE8388620 8388640 8388662 06083-009 Figure 7. AD7797 Noise Distribution Histogram Figure 9. AD7797 Noise Distribution Histogram (VREF = AVDD, Update Rate = 16.7 Hz) (VREF = AVDD, Update Rate = 4.17 Hz) Rev. B | Page 10 of 24

Data Sheet AD7796/AD7797 ON-CHIP REGISTERS The ADC is controlled and configured via a number of on-chip Once the subsequent read or write operation to the selected registers, which are described on the following pages. In the register is complete, the interface returns to where it expects a following descriptions, set implies a Logic 1 State and cleared write operation to the communication register (this is the implies a Logic 0 State, unless otherwise stated. default state of the interface). On power-up or after a reset, the ADC is in this default state waiting for a write operation to the COMMUNICATION REGISTER communication register. In situations where the interface sequence RS2, RS1, RS0 = 0, 0, 0 is lost, a write operation of at least 32 serial clock cycles with The communication register is an 8-bit write-only register. All DIN high returns the ADC to this default state by resetting the communication to the device must start with a write operation entire device. Table 9 outlines the bit designations for the to this register. The data written to the communication register communication register. CR0 through CR7 indicate the bit determines whether the next operation is a read or write opera- location, with CR denoting that the bits are in the communication tion, and selects the register where this operation takes place. register. CR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. MSB LSB CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 WEN(0) R/W(0) RS2(0) RS1(0) RS0(0) CREAD(0) 0(0) 0(0) Table 9. Communication Register Bit Designations Bit Location Bit Name Description CR7 WEN Write Enable Bit. A 0 must be written to this bit first to ensure that a write to the communication register occurs. If a 1 is the first bit written, the device does not clock onto subsequent bits in the register; it stays at this bit location until a 0 is written. Once a 0 is written to the WEN bit, the next seven bits are loaded to the communication register. CR6 R/W A 0 in this bit location indicates that the next operation is a write to a specified register. A 1 in this position indicates that the next operation is a read from the designated register. CR5 to CR3 RS2 to RS0 Register Address Bits. These address bits determine which ADC registers are being selected during this serial interface communication. See Table 10. CR2 CREAD Continuous Read of the Data Register. When this bit is set to 1 (and the data register is selected), the serial interface is configured to continuously read the data register. For example, the contents of the data register are automatically placed on the DOUT pin when the SCLK pulses are applied and after the RDY pin goes low. This indicates that a conversion is complete. The communication register does not have to be written to for data reads. To enable continuous read mode, the instruction 01011100 must be written to the communication register. To exit the continuous read mode, the instruction 01011000 must be written to the communication register while the RDY pin is low. While in continuous read mode, the ADC monitors activity on the DIN line so it can receive the instruction to exit continuous read mode. Additionally, a reset occurs if 32 consecutive 1s are seen on DIN. Therefore, DIN should be held low in continuous read mode until an instruction is written to the device. CR1 to CR0 0 These bits must be programmed to Logic 0 for correct operation. Table 10. Register Selection RS2 RS1 RS0 Register Register Size 0 0 0 Communication Register During a Write Operation 8 bits 0 0 0 Status Register During a Read Operation 8 bits 0 0 1 Mode Register 16 bits 0 1 0 Configuration Register 16 bits 0 1 1 Data Register 16 bits (AD7796), 24 bits (AD7797) 1 0 0 ID Register 8 bits 1 0 1 Reserved 8 bits 1 1 0 Offset Register 16 bits (AD7796), 24 bits (AD7797) 1 1 1 Full-Scale Register 16 bits (AD7796), 24 bits (AD7797) Rev. B | Page 11 of 24

AD7796/AD7797 Data Sheet STATUS REGISTER RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80 The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communication register, select the next operation to be a read, and load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 11 outlines the bit designations for the status register. SR0 through SR7 indicate the bit locations, with SR denoting that the bits are in the status register. SR7 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. MSB LSB SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 RDY(1) ERR(0) 0(0) 0(0) 0(0/1) CH2(0) CH1(0) CH0(0) Table 11. Status Register Bit Designations Bit Location Bit Name Description SR7 RDY Ready Bit for ADC. Cleared when data is written to the ADC data register. Set automatically after the ADC data register has been read or before the data register is updated with a new conversion result to indicate to the user not to read the conversion data. It is also set when the device is placed in power-down mode. DOUT/RDY also indicates the end of a conversion and can be used as an alternative to the status register for monitoring the ADC for conversion data. SR6 ERR ADC Error Bit. This bit is written to at the same time as the RDY bit. Set to indicate that the result written to the ADC data register has been clamped to all 0s or all 1s. Error sources include overrange and underrange. Cleared by a write operation to start a conversion. SR5 to SR4 0 These bits are automatically cleared. SR3 0 This bit is automatically cleared on the AD7796 and is automatically set on the AD7797. SR2 to SR0 CH2 to CH0 These bits indicate the channel that is being converted by the ADC. MODE REGISTER RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x000A The mode register is a 16-bit read/write register. This register is used to select the operating mode, update rate, and clock source. Table 12 outlines the bit designations for this register. MR0 through MR15 indicate the bit locations, with MR denoting that the bits are in the mode register. MR15 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. Any write to the setup register resets the modulator and filter, and sets the RDY bit. MSB LSB MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8 MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0 MD2(0) MD1(0) MD0(0) 0(0) 0(0) 0(0) 0(0) 0(0) CLK1(0) CLK0(0) 0(0) 0(0) FS3(1) FS2(0) FS1(1) FS0(0) Table 12. Mode Register Bit Designations Bit Location Bit Name Description MR15 to MR13 MD2 to MD0 Mode Select Bits. These bits select the operational mode of the AD7796/AD7797 (see Table 13). MR12 to MR8 0 These bits must be programmed with a Logic 0 for correct operation. MR7 to MR6 CLK1 to CLK0 These bits are used to select the clock source for the AD7796/AD7797. Either an on-chip 64 kHz clock or an external clock can be used. The ability to override using an external clock allows several AD7796/ AD7797 devices to be synchronized. In addition, 50 Hz/60 Hz rejection is improved when an accurate external clock drives the AD7796/AD7797. CLK1 CLK0 ADC Clock Source 0 0 Internal 64 kHz Clock. Internal clock is not available at the CLK pin. 0 1 Internal 64 kHz Clock. This clock is made available at the CLK pin. 1 0 External 64 kHz Clock Used. An external clock gives better 50 Hz/60 Hz rejection. See Table 1 for the external clock specifications. 1 1 External Clock Used. The external clock is divided by 2 within the AD7796/AD7797. MR5 to MR4 0 These bits must be programmed with a Logic 0 for correct operation. MR3 to MR0 FS3 to FS0 Filter Update Rate Select Bits (see Table 14). Rev. B | Page 12 of 24

Data Sheet AD7796/AD7797 Table 13. Operating Modes MD2 MD1 MD0 Mode 0 0 0 Continuous Conversion Mode (default). In continuous conversion mode, the ADC continuously performs conversions and places the result in the data register. RDY goes low when a conversion is complete. The user can read these conversions by placing the device in continuous read mode, whereby the conversions are automatically placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can instruct the ADC to output the conversion by writing to the communication register. After a power-on, channel change, or write to the mode or configuration register, the first conversion is available after a period of 2/f , while subsequent conversions are ADC available at a frequency of f . ADC 0 0 1 Single Conversion Mode. When single conversion mode is selected, the ADC powers up and performs a single conversion. The oscillator requires 1 ms to power up and settle. The ADC then performs the conversion, which takes a time of 2/f . The conversion result is placed in the data register, RDY goes low, and the ADC returns to power- ADC down mode. The conversion remains in the data register and RDY remains active (low) until the data is read or another conversion is performed. 0 1 0 Idle Mode. In idle mode, the ADC filter and modulator are held in a reset state although the modulator clocks are still provided. 0 1 1 Power-Down Mode. In power-down mode, all the AD7796/AD7797 circuitry is powered down, including the burnout currents and CLKOUT circuitry. 1 0 0 Internal Zero-Scale Calibration. An internal short is automatically connected to the channel. A calibration takes two conversion cycles to complete. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is placed in the offset register. 1 0 1 Reserved. 1 1 0 System Zero-Scale Calibration. Users should connect the system zero-scale input to the channel input pins. A system offset calibration takes two conversion cycles to complete. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is placed in the offset register. 1 1 1 System Full-Scale Calibration. Users should connect the system full-scale input to the channel input pins. A calibration takes two conversion cycles to complete. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full- scale coefficient is placed in the full-scale register. Table 14. Update Rates Available FS3 FS2 FS1 FS0 f (Hz) t (ms) Rejection at 50 Hz/60 Hz (Internal Clock) ADC SETTLE 0 0 0 0 X X 0 0 0 1 X X 0 0 1 0 X X 0 0 1 1 123 16 0 1 0 0 62 32 0 1 0 1 50 40 0 1 1 0 X X 0 1 1 1 33.2 60 1 0 0 0 X X 1 0 0 1 16.7 120 80 dB (50 Hz only) 1 0 1 0 16.7 120 65 dB (50 Hz and 60 Hz) 1 0 1 1 12.5 160 66 dB (50 Hz and 60 Hz) 1 1 0 0 10 200 69 dB (50 Hz and 60 Hz) 1 1 0 1 8.33 240 70 dB (50 Hz and 60 Hz) 1 1 1 0 6.25 320 72 dB (50 Hz and 60 Hz) 1 1 1 1 4.17 480 74 dB (50 Hz and 60 Hz) Rev. B | Page 13 of 24

AD7796/AD7797 Data Sheet CONFIGURATION REGISTER RS2, RS1, RS0 = 0, 1, 0; Power-On/Reset = 0x0710 The configuration register is a 16-bit read/write register. This register is used to configure the ADC for unipolar or bipolar mode, enable or disable the burnout currents, and select the analog input channel. Table 15 outlines the bit designations for the configuration register. CON0 through CON15 indicate the bit locations, with CON denoting that the bits are in the configuration register. CON15 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. MSB LSB CON15 CON14 CON13 CON12 CON11 CON10 CON9 CON8 CON7 CON6 CON5 CON4 CON3 CON2 CON1 CON0 0(0) 0(0) BO(0) U/B(0) 0(0) 1(1) 1(1) 1(1) 0(0) 0(0) 0(0) 1(1) 0(0) CH2(0) CH1(0) CH0(0) Table 15. Configuration Register Bit Designations Bit Location Bit Name Description CON15 to CON14 0 These bits must be programmed with a Logic 0 for correct operation. CON13 BO Burnout Current Enable Bit. When this bit is set to 1 by the user, the 100 nA current sources in the signal path are enabled. When BO = 0, the burnout currents are disabled. CON12 U/B Unipolar/Bipolar Bit. Set by user to enable unipolar coding, that is, a zero differential input results in 0x0000(00) output, and a full-scale differential input results in 0xFFFF(FF) output. Cleared by the user to enable bipolar coding. A negative full-scale differential input results in an output code of 0x0000(00), a zero differential input results in an output code of 0x8000(00), and a positive full-scale differential input results in an output code of 0xFFFF(FF). CON11 0 This bit must be programmed with a Logic 0 for correct operation. CON10 to CON8 1 These bits must be programmed with a Logic 1 for correct operation. CON7 to CON5 0 These bits must be programmed with a Logic 0 for correct operation. CON4 1 This bit must be programmed with a Logic 1 for correct operation. CON3 0 This bit must be programmed with a Logic 0 for correct operation. CON2 to CON0 CH2 to CH0 Channel Select bits. Written by the user to select the active analog input channel to the ADC. CH2 CH1 CH0 Channel 0 0 0 AIN(+) − AIN(–) 0 0 1 Reserved 0 1 0 Reserved 0 1 1 AIN(–) − AIN(–) 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Temp Sensor 1 1 1 AV Monitor DD DATA REGISTER RS2, RS1, RS0 = 0, 1, 1; Power-On/Reset = 0x0000 (AD7796)/0x000000 (AD7797) The conversion result from the ADC is stored in this data register. This is a read-only register. On completion of a read operation from this register, the RDY bit/pin is set. ID REGISTER RS2, RS1, RS0 = 1, 0, 0; Power-On/Reset = 0x5A (AD7796)/0x5B (AD7797) The identification number for the AD7796/AD7797 is stored in the ID register. This is a read-only register. Rev. B | Page 14 of 24

Data Sheet AD7796/AD7797 OFFSET REGISTER RS2, RS1, RS0 = 1, 1, 0; Power-On/Reset = 0x8000 (AD7796)/0x800000 (AD7797) The analog input channel has an offset register that holds the offset calibration coefficient for the channel. This register is 16 bits wide on the AD7796 and 24 bits wide on the AD7797, and its power-on/reset value is 0x8000(00). The offset register is used in conjunction with the full-scale register to form a register pair. The power-on/reset value is automatically overwritten if an internal or system zero-scale calibration is initiated by the user. The offset register is a read/write register. However, the AD7796/AD7797 must be in idle mode or power-down mode when writing to this register. FULL-SCALE REGISTER RS2, RS1, RS0 = 1, 1, 1; Power-On/Reset = 0x5XXX (AD7796)/0x5XXX00 (AD7797) The full-scale register is a 16-bit register on the AD7796 and a 24-bit register on the AD7797. The full-scale register holds the full-scale calibration coefficient for the ADC. The full-scale register is a read/write register. However, when writing to the full-scale register, the ADC must be placed in power-down mode or idle mode. The full-scale register is configured on power-on with the factory-calibrated full-scale calibration coefficient. Therefore, every device has a different default coefficient. The default value is automatically overwritten if a system full-scale calibration is initiated by the user, or if the full-scale register is written to. Rev. B | Page 15 of 24

AD7796/AD7797 Data Sheet ADC CIRCUIT INFORMATION OVERVIEW 0 The AD7796/AD7797 are low power ADCs that incorporate a Σ-∆ modulator, in-amp, and an on-chip digital filter intended –20 for measuring wide dynamic range, low frequency signals, such as those in pressure transducers and weigh scales. –40 B) Each device has one differential input that is buffered. Figure 10 d ( shows the basic connections required to operate the device. –60 VDD –80 IN+ REFIN(+)AVDD VDD AD7796/AD7797 –100 OUT–IN– OUT+ AAIINN((–+)) MUX ×128 AΣD-ΔC INCTSOLEEANORRNTGFIDRAIACOLCLE DDSCCOISNLUKT/RDY 0 Figure2 101. Filter 4P0roFfRilEeQ wUiEt6hN0 CUYpd(Hazt)e8 R0ate = 41.1070 Hz 120 06083-011 TEMP GND INTERNAL DVDD 0 SENSOR CLOCK REFIN(–) GND CLK 06083-010 –20 Figure 10. Basic Connection Diagram –40 The output rate of the AD7796/AD7797 (fADC) is user- dB) programmable. The allowable update rates, along with the ( –60 corresponding settling times, are listed in Table 14. Normal mode rejection is the major function of the digital filter. –80 Simultaneous 50 Hz and 60 Hz rejection is optimized when the update rate equals 16.7 Hz or less because notches are placed at both 50 Hz and 60 Hz with these update rates (see Figure 12). –100 The AD7796/AD7797 use slightly different filter types, 0 20 40 60 FR80EQU1E0N0CY1(H20z) 140 160 180 200 06083-012 depending on the output update rate used to optimize the Figure 12. Filter Profile with Update Rate = 16.7 Hz rejection of quantization noise and device noise. When the 0 update rate is 4.17 Hz to 12.5 Hz, a Sinc3 filter and an averaging filter are used. When the update rate is 16.7 Hz to 33.2 Hz, a –20 modified Sinc3 filter is used. This filter gives simultaneous 50 Hz/60 Hz rejection when the update rate equals 16.7 Hz. A Sinc4 filter is used when the update rate is from 50 Hz to –40 123 Hz. Figure 11 to Figure 13 show the frequency response B) d of the different filter types for some of the update rates. ( –60 –80 –100 0 100 200 300 F4R0E0QU5E0N0CY6(H00z) 700 800 900 1000 06083-013 Figure 13. Filter Profile with Update Rate = 50 Hz Rev. B | Page 16 of 24

Data Sheet AD7796/AD7797 DIGITAL INTERFACE Figure 3 shows the timing for a read operation from the AD7796/ AD7797 output shift register, while Figure 4 shows the timing As outlined in the On-Chip Registers section, the AD7796/ for a write operation to the input shift register. It is possible to AD7797 programmable functions are controlled by a set of read the same word from the data register several times, even on-chip registers. Data is written to these registers via the serial though the DOUT/RDY line returns high after the first read interface of the device and read access to the on-chip registers is operation. However, care must be taken to ensure that the read also provided by this interface. All communication with the device operations have been completed before the next output update must start with a write to the communication register. After power- occurs. In continuous read mode, the data register can be read on or reset, the device expects a write to its communication only once. register. The data written to this register determines whether the next operation is a read or a write operation, and determines The serial interface can operate in 3-wire mode by tying CS low. the register where this operation occurs. Therefore, write access In this case, the SCLK, DIN, and DOUT/RDY lines are used to any of the other registers on the device begins with a write to communicate with the AD7796/AD7797. The end of the operation to the communication register followed by a write to conversion can be monitored using the RDY bit in the status the selected register. A read operation from any other register register. This scheme is suitable for interfacing to micro- (except when continuous read mode is selected) starts with a controllers. If CS is required as a decoding signal, it can be write to the communication register followed by a read generated from a port pin. For microcontroller interfaces, it is operation from the selected register. recommended that SCLK idle high between data transfers. The serial interface of the AD7796/AD7797 consists of four The AD7796/AD7797 can be operated with CS being used as a signals: CS, DIN, SCLK, and DOUT/RDY. The DIN line is used frame synchronization signal. This scheme is useful for DSP to transfer data into the on-chip registers, while DOUT/RDY is interfaces. In this case, the first bit (MSB) is effectively clocked used for accessing from the on-chip registers. SCLK is the serial out by CS because CS normally occurs after the falling edge of clock input for the device, and all data transfers (either on DIN SCLK in DSPs. The SCLK can continue to run between data or DOUT/RDY) occur with respect to the SCLK signal. The transfers, provided the timing numbers are obeyed. DOUT/RDY pin also operates as a data-ready signal, that is, the line goes low when a new data-word is available in the output The serial interface can be reset by writing a series of 1s on the register. It is reset high when a read operation from the data DIN input. If a Logic 1 is written to the AD7796/AD7797 DIN register is complete. DOUT/RDY also goes high prior to the line for at least 32 serial clock cycles, the serial interface is reset. data register update to indicate when not to read from the This ensures that the interface can be reset to a known state if device. This ensures that a data read is not attempted while the the interface gets lost due to a software error or glitch in the register is being updated. CS is used to select a device. It can be system. Reset returns the interface to the state where it is expecting used to decode the AD7796/AD7797 in systems where several a write to the communication register. This operation resets the components are connected to the serial bus. contents of all registers to their power-on values. Following a reset, the user should allow a period of 500 µs before addressing Figure 3 and Figure 4 show timing diagrams for interfacing to the serial interface. the AD7796/AD7797 with CS being used to decode the device. The AD7796/AD7797 can be configured to continuously convert or to perform a single conversion. See Figure 14 through Figure 16. Rev. B | Page 17 of 24

AD7796/AD7797 Data Sheet Single Conversion Mode Continuous Conversion Mode In single conversion mode, the AD7796/AD7797 are placed in This is the default power-up mode. The AD7796/AD7797 shutdown mode between conversions. When a single conver- continuously convert, and the RDY pin in the status register sion is initiated by setting MD2, MD1, and MD0 in the mode goes low each time a conversion is complete. If CS is low, the register to 0, 0, and 1, respectively, the device powers up, DOUT/RDY line also goes low when a conversion is complete. performs a single conversion, and then returns to shutdown To read a conversion, the user can write to the communication mode. The on-chip oscillator requires 1 ms to power-up. A register, indicating that the next operation is a read of the data conversion requires a time period of 2 × tADC. DOUT/RDY goes register. The digital conversion is placed on the DOUT/RDY low to indicate the completion of a conversion. When the data- pin as soon as SCLK pulses are applied to the ADC. DOUT/RDY word has been read from the data register, DOUT/RDY goes returns high when the conversion is read. The user can read this high. If CS is low, DOUT/RDY remains high until another register additional times, if required. However, the user must conversion is initiated and completed. The data register can be ensure that the data register is not being accessed at the completion read several times, if required, even when DOUT/RDY has of the next conversion, or the new conversion word is lost. gone high. CS DIN 0x08 0x200A 0x58 DATA DOUT/RDY SCLK 06083-014 Figure 14. Single Conversion CS 0x58 0x58 DIN DATA DATA DOUT/RDY SCLK 06083-015 Figure 15. Continuous Conversion Rev. B | Page 18 of 24

Data Sheet AD7796/AD7797 Continuous Read Mode The user must also ensure that the data-word is read before the next conversion is complete. If the user has not read the conversion Rather than write to the communication register each time a before the completion of the next conversion, or if insufficient conversion is complete to access the data, the AD7796/AD7797 serial clocks are applied to the AD7796/AD7797 to read the word, can be configured to automatically place the conversions on the the serial output register is reset when the next conversion is DOUT/RDY line. By writing 01011100 to the communication complete. The new conversion is placed in the output serial register, the user need only apply the appropriate number of register. SCLK cycles to the ADC. The 16-/24-bit word is automatically placed on the DOUT/RDY line when a conversion is complete. To exit continuous read mode, the instruction 01011000 must The ADC should be configured for continuous conversion mode. be written to the communication register while the DOUT/RDY pin is low. While in continuous read mode, the ADC monitors When DOUT/RDY goes low to indicate the end of a conversion, activity on the DIN line to receive the instruction to exit the sufficient SCLK cycles must be applied to the ADC. The data continuous read mode. Additionally, a reset occurs if 32 conversion is placed on the DOUT/RDY line. When the conver- consecutive 1s are seen on DIN. Therefore, DIN should be sion is read, DOUT/RDY returns high until the next conversion held low in continuous read mode until an instruction is is available. In this mode, the data can be read only once. written to the device. CS 0x5C DIN DATA DATA DATA DOUT/RDY SCLK 06083-016 Figure 16. Continuous Read Rev. B | Page 19 of 24

AD7796/AD7797 Data Sheet CIRCUIT DESCRIPTION ANALOG INPUT CHANNEL When the ADC is configured for bipolar operation, the output code is offset binary with a negative full-scale voltage resulting The AD7796/AD7797 have one differential analog input in a code of 000...000, a zero differential input voltage resulting channel. The input channel feeds into a high impedance input in a code of 100...000, and a positive full-scale input voltage stage of the amplifier. Therefore, the input can tolerate signifi- resulting in a code of 111...111. The output code for any analog cant source impedances and is tailored for direct connection to input voltage can be represented as external resistive-type sensors such as strain gages. Code = 2N – 1 × [(AIN × 128 /V ) + 1] REF The absolute input voltage range is restricted to a range between GND + 300 mV and AVDD − 1.1 V. Care must be taken in setting where: up the common-mode voltage to avoid exceeding these limits. AIN is the analog input voltage Otherwise, there is degradation in linearity and noise N = 16/24 for the AD7796/AD7797. performance. REFERENCE This low noise in-amp means that signals of small amplitude can be gained within the AD7796/AD7797 while still maintain- The AD7796/AD7797 have a fully differential input capability ing excellent noise performance. The amplifier is configured to for the channel. The common-mode range for these differential have a gain of 128. Therefore, with an external 2.5 V reference, inputs is GND to AVDD. The reference input is unbuffered; the unipolar range is 0 mV to 20 mV while the bipolar range is therefore, excessive R-C source impedances introduce gain ±20 mV. The common-mode voltage ((AIN(+) + AIN(–))/2 errors. The reference voltage REFIN (REFIN(+) − REFIN(−)) is must be ≥ 0.5 V. 2.5 V nominal, but the AD7796/AD7797 are functional with reference voltages 0.1 V to AV . In applications where the DD BIPOLAR/UNIPOLAR CONFIGURATION excitation (voltage or current) for the transducer on the analog The analog input to the AD7796/AD7797 can accept either input also drives the reference voltage for the device, the effect unipolar or bipolar input voltage ranges. A bipolar input range of the low frequency noise in the excitation source is removed does not imply that the device can tolerate negative voltages because the application is ratiometric. If the AD7796/AD7797 with respect to system GND. Unipolar and bipolar signals on are used in a nonratiometric application, a low noise reference the AIN(+) input are referenced to the voltage on the AIN(–) should be used. input. For example, if AIN(−) is 2.5 V and the ADC is Recommended 2.5 V reference voltage sources for the AD7796/ configured for unipolar mode, the input voltage range on the AD7797 include the ADR381 and ADR391, which are low noise, AIN(+) pin is 2.5 V to 2.02 V. low power references. Also note that the reference inputs provide If the ADC is configured for bipolar mode, the analog input a high impedance, dynamic load. Because the input impedance range on the AIN(+) input is 2.48 V to 2.52 V. The bipolar/ of each reference input is dynamic, resistor/ capacitor combinations unipolar option is chosen by programming the U/B bit in the on these inputs can cause dc gain errors, depending on the configuration register. output impedance of the source that is driving the reference inputs. DATA OUTPUT CODING Reference voltage sources such as those recommended above When the ADC is configured for unipolar operation, the output (the ADR391, for example) typically have low output impedances code is natural (straight) binary with a zero differential input and are, therefore, tolerant to decoupling capacitors on REFIN(+) voltage resulting in a code of 00...00, a midscale voltage resulting in without introducing gain errors in the system. Deriving the a code of 100...000, and a full-scale input voltage resulting in a reference input voltage across an external resistor means that code of 111...111. The output code for any analog input voltage the reference input sees a significant external source impedance. can be represented as External decoupling on the REFIN pins is not recommended in Code = (2N × AIN × 128)/V REF this type of circuit configuration. Rev. B | Page 20 of 24

Data Sheet AD7796/AD7797 RESET TEMPERATURE MONITOR The circuitry and serial interface of the AD7796/AD7797 can The AD7796/AD7797 have an embedded temperature sensor be reset by writing 32 consecutive 1s to the device. This resets that is accessed when Bit CH2 to Bit CH0 are equal to 1, 1, 0, the logic, the digital filter, and the analog modulator, while all respectively. When the internal temperature sensor is selected, on-chip registers are reset to their default values. A reset is the AD7796/AD7797 use an internal 1.17 V reference for automatically performed on power-up. When a reset is initiated, the conversions. The temperature sensor has a sensitivity of the user must allow a period of 500 µs before accessing any of 0.81 mV/°C. However, a two-point calibration is required to the on-chip registers. A reset is useful if the serial interface optimize the accuracy. The temperature sensor is not factory becomes asynchronous because of noise on the SCLK line. calibrated; a user calibration is required. Following a calibration, the accuracy is 2°C. BURNOUT CURRENTS CALIBRATION The AD7796/AD7797 contain two 100 nA constant current generators, one sourcing current from AV to AIN(+) and one The AD7796/AD7797 provide three calibration modes that can DD sinking current from AIN(–) to GND. Both currents are either be programmed via the mode bits in the mode register. These on or off, depending on the burnout current enable (BO) bit in are internal zero-scale calibration, system zero-scale calibration, the configuration register. These currents can be used to verify and system full-scale calibration, which effectively reduces the that an external transducer is still operational before attempting offset error and full-scale error to the order of the noise. After to take measurements. When the burnout currents are turned each conversion, the ADC conversion result is scaled using the on, they flow in the external transducer circuit, and a measure- ADC calibration registers before being written to the data register. ment of the input voltage on the analog input channel can be The offset calibration coefficient is subtracted from the result taken. If the resulting voltage is full scale, the user needs to prior to multiplication by the full-scale coefficient. verify why this is the case. A full-scale reading could mean that To start a calibration, write the relevant value to the MD2 to the front-end sensor is open circuit. It could also mean that the MD0 bits in the mode register. DOUT/RDY goes high when the front-end sensor is overloaded and is justified in outputting full calibration is initiated. After the calibration is complete, the scale, or that the reference could be absent, thus clamping the contents of the corresponding calibration registers are updated, data to all 1s. the RDY bit in the status register is set, the DOUT/ RDY pin goes When reading all 1s from the output, the user needs to check low (if CS is low), and the AD7796/AD7797 revert to idle mode. these three cases before making a judgment. If the voltage measured is 0 V, it could indicate that the transducer has short During an internal zero-scale calibration, the zero input is circuited. For normal operation, these burnout currents are automatically connected internally to the ADC input pins. A turned off by writing a 0 to the BO bit in the configuration system calibration, however, expects the system zero-scale and register. system full-scale voltages to be applied to the ADC pins before the calibration mode is initiated. In this way, external ADC AV MONITOR DD errors are removed. Along with converting external voltages, the ADC can be used From an operational point of view, a calibration should be to monitor the voltage on the AV pin. When Bit CH2 to DD treated like another ADC conversion. A zero-scale calibration Bit CH0 equal 1, the voltage on the AV pin is internally DD (if required) should always be performed before a full-scale attenuated by 6. The resulting voltage is applied to the Σ-∆ calibration. System software should monitor the RDY bit in the modulator using an internal 1.17 V reference for analog-to- status register or the DOUT/RDY pin to determine the end of digital conversion. This is useful because variations in the power supply voltage can be monitored. calibration via a polling sequence or an interrupt-driven routine. Both an internal offset calibration and system offset calibration takes two conversion cycles. An internal offset calibration is not needed because the ADC itself removes the offset continuously. A system full-scale calibration takes two conversion cycles to complete. The measured full-scale coefficient is placed in the full-scale register. If system offset calibrations are being performed along with system full-scale calibrations, the offset calibration should be performed before the system full-scale calibration is initiated. Rev. B | Page 21 of 24

AD7796/AD7797 Data Sheet GROUNDING AND LAYOUT The ground planes of the AD7796/AD7797 should be allowed to run under the AD7796/AD7797 to prevent noise coupling. Because the analog input and reference input of the ADC are The power supply lines to the AD7796/AD7797 should use as differential, most of the voltages in the analog modulator are wide a trace as possible to provide low impedance paths and common-mode voltages. The excellent common-mode reject- reduce the effects of glitches on the power supply line. Fast ion of the device removes common-mode noise on these inputs. switching signals such as clocks should be shielded with digital The digital filter provides rejection of broadband noise on the ground to avoid radiating noise to other sections of the board, power supply, except at integer multiples of the modulator and clock signals should never be run near the analog inputs. sampling frequency. The digital filter also removes noise from Avoid crossover of digital and analog signals. Traces on the analog and reference inputs provided that these noise opposite sides of the board should run at right angles to each sources do not saturate the analog modulator. As a result, the other. This reduces the effects of feedthrough through the AD7796/AD7797 are more immune to noise interference than board. A micro-strip technique is by far the best, but it is not conventional high resolution converters. However, because the always possible with a double-sided board. In this technique, resolution of the AD7796/AD7797 is so high, and the noise the component side of the board is dedicated to ground planes, levels from the AD7796/AD7797 are so low, care must be taken while signals are placed on the solder side. with regard to grounding and layout. Good decoupling is important when using high resolution ADCs. The printed circuit board that houses the AD7796/AD7797 AV should be decoupled with 10 µF tantalum in parallel with should be designed such that the analog and digital sections are DD 0.1 µF capacitors to GND. DV should be decoupled with 10 separated and confined to certain areas of the board. A minimum DD µF tantalum in parallel with 0.1 µF capacitors to the DGND etch technique is generally best for ground planes because it plane of the system, with the AGND to DGND connection of gives the best shielding. the system being close to the AD7796/ AD7797. To achieve the It is recommended that the GND pins of the AD7796/AD7797 best results from these decoupling components, they should be be tied to the AGND plane of the system. In any layout, it is placed as close as possible to the device, ideally right up against important that the user pay attention to the flow of currents in the device. All logic chips should be decoupled with 0.1 µF the system, and ensure that the return paths for all currents are ceramic capacitors to DGND. as close as possible to the paths the currents took to reach their destinations. Avoid forcing digital currents to flow through the AGND sections of the layout. Rev. B | Page 22 of 24

Data Sheet AD7796/AD7797 APPLICATIONS INFORMATION scale output range from the transducer is 10 mV when the The AD7796/AD7797 offer a high resolution analog-to-digital sensitivity is 2 mV/V. The excitation voltage for the bridge can function. Because the analog-to-digital function is provided by be used to directly provide the reference for the ADC because a Σ-∆ architecture, the devices are more immune to noisy the reference input range includes the supply voltage. This allows a environments, making them ideal for use in sensor measurement, ratiometric measurement. Therefore, variations of the excitation and industrial and process-control applications. voltage do not affect the measurement. WEIGH SCALES The on-chip temperature sensor can be used for temperature Figure 17 shows the AD7796/AD7797 being used in a weigh compensation of the bridge so the variation of the sensor scale application. The load cell is arranged in a bridge network resistance with temperature drift can be monitored and the and gives a differential output voltage between its OUT+ and conversions from the bridge can be compensated. OUT– terminals. Assuming a 5 V excitation voltage, the full- VDD AVDD AD7796/AD7797 IN+ REFIN(+) VDD OUT– OUT+ AIN(+) SERIAL DOUT/RDY IN– AIN(–) MUX ×128 AΣD-ΔC INCTOEANRNTFDRAOCLE DSCINLK LOGIC CS TEMP GND INTERNAL DVDD SENSOR CLOCK REFIN(–) GND CLK 06083-017 Figure 17. Weigh Scales Using the AD7796/AD7797 Rev. B | Page 23 of 24

AD7796/AD7797 Data Sheet OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.09 0.75 0.30 8° 0.60 B0.S6C5 0.19 SPELAANTIENG 0° 0.45 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 18. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD7796BRUZ –40°C to +85°C 16-Lead TSSOP RU-16 AD7796BRUZ-REEL –40°C to +85°C 16-Lead TSSOP RU-16 AD7797BRUZ –40°C to +85°C 16-Lead TSSOP RU-16 AD7797BRUZ-REEL –40°C to +85°C 16-Lead TSSOP RU-16 EVAL-AD7796EB Evaluation Board EVAL-AD7797EB Evaluation Board 1 Z = RoHS Compliant Part. ©2006–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06083-0-3/16(B) Rev. B | Page 24 of 24