12-Bit, 65 MSPS IF to Baseband Diversity Receiver AD6652 FEATURES APPLICATIONS SNR = 90 dB in 150 kHz bandwidth (to Nyquist Communications @ 61.44 MSPS) Diversity radio systems Worst harmonic = 83 dBc (to Nyquist @ 61.44 MSPS) Multimode digital receivers: Integrated dual-channel ADC: GSM, EDGE, PHS, AMPS, UMTS, WCDMA, CDMA-ONE, Sample rates up to 65 MSPS IS95, IS136, CDMA2000, IMT-2000 IF sampling frequencies to 200 MHz I/Q demodulation systems Internal ADC voltage reference Smart antenna systems Integrated ADC sample-and-hold inputs General-purpose software radios Flexible analog input range (1 V to 2 V p-p) Broadband data applications Differential analog inputs Instrumentation and test equipment ADC clock duty cycle stabilizer 85 dB channel isolation/crosstalk Integrated wideband digital downconverter (DDC): Crossbar switched DDC inputs Digital resampling for noninteger decimation Programmable decimating FIR filters Flexible control for multicarrier and phased array Dual AGC stages for output level control Dual 16-bit parallel or 8-bit link output ports User-configurable built-in self-test (BIST) capability Energy-saving power-down modes FUNCTIONAL BLOCK DIAGRAM DUAL-CHANNEL 12-BIT A/D FRONT END WIDEBAND DIGITAL DOWNCONVERTER (DDC) RAM VINA+ SHA CHAANDNCEL 1/2 CHANNEL A RESRACMICP2LER CIC5 FCILOTEEFR. TO OUTPUT PORTS 8P-BOITR TD SAP VINA– A OTRA NCO CHANNEL 0 CHANRNCEFL SO U0,T 1P,U 2T, S3 LINK LIA OR RREEFFTBAA PSEUDLOIA RIX RESRACMICP2LER CIC5 FCRILOATEMEFR. TO OUTPUT PORTS POA1UR6TA-BPLIULTETL VSRENEFSE VREF RNAONDISOEM MAT NCO CHANNEL 1 AGC A* CONTROL SEQUENCE UT OUTPUT RREEFFTBBB LLIIBB INP RESRACMICP2LER CIC5 FCRILOATEMEFR. TPOO ROTUSTPUT CIRMCUUXITRY OTRB CHANNEL 2 PORT B VINB+ ADC 12 NCO AGC B* SHA CHANNEL / 8-BIT DSP VINB– B CHANNEL B RCIC2 CIC5 CROAEMF. TO OUTPUT PORTS LINK RESAMPLER FILTER OR NCO CHANNEL 3 CHANRNCEFL SO U0,T 1P,U 2T, S3 PA1R6A-BLILTEL OUTPUT *DATA INTERLEAVING AND INTERPOLATING HB FILTER CONTROL CLOCK SHRPDDRWENF SMEOLEDCET DUATCYLEKN STCADYBUCITLLYIZEER SSSSYYYYNNNNCCCCABCD EXCSTIRYECNRUCNI.ATL DCDLKC SCBEIRLUCFIL-UTTIE-TISNRTY MPIRCOROGPROARMT +3.0AVDD +3.3VDDIO 2.5VDD AGND DGND CLK D/AT8ACO/N3TA/D3D 03198-0-001 Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and Tel: 781.329.4700 www.analog.com registered trademarks are the property of their respective owners. Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.

AD6652 TABLE OF CONTENTS Product Description.........................................................................4 Gain Switching............................................................................31 Product Highlights.......................................................................4 Numerically Controlled Oscillator...............................................33 Specifications.....................................................................................5 Frequency Translation to Baseband.........................................33 Recommended Operating Conditions......................................5 NCO Shadow Register...............................................................33 ADC DC Specifications...............................................................5 NCO Frequency Hold-Off Register.........................................33 ADC Switching Specifications....................................................5 Phase Offset.................................................................................33 ADC AC Specifications...............................................................6 NCO Control Register...............................................................33 Electrical Characteristics.............................................................7 Second-Order rCIC Filter.............................................................35 General Timing Characteristics.................................................8 rCIC2 Scale Factor.....................................................................35 Microprocessor Port Timing Characteristics...........................9 rCIC2 Output Level...................................................................36 Absolute Maximum Ratings..........................................................10 rCIC2 Rejection..........................................................................36 Thermal Characteristics............................................................10 Decimation and Interpolation Registers.................................36 Test Level.....................................................................................10 rCIC2 Scale Register..................................................................36 ESD Caution................................................................................10 Fifth-Order CIC Filter...................................................................37 Pin Configuration and Function Descriptions...........................11 CIC5 Rejection...........................................................................37 Typical Performance Characteristics...........................................14 RAM Coefficient Filter..................................................................38 DDC Timing Diagrams.................................................................17 RCF Decimation Register..........................................................38 Terminology....................................................................................23 RCF Decimation Phase..............................................................38 ADC Equivalent Circuits...........................................................23 RCF Filter Length.......................................................................38 Theory of Operation......................................................................24 RCF Output Scale Factor and Control Register.....................39 ADC Architecture......................................................................24 Interpolating Half-Band Filters....................................................40 Digital Downconverter Architecture Overview.........................29 Automatic Gain Control................................................................41 Data Input Matrix.......................................................................29 AGC Loop...................................................................................41 Numerically Controlled Oscillator...........................................29 Desired Signal Level Mode........................................................41 Second-Order rCIC Filter.........................................................29 Synchronization..........................................................................44 Fifth-Order CIC Filter...............................................................29 User-Configurable Built-In Self-Test (BIST)..............................45 RAM Coefficient Filter..............................................................29 RAM BIST...................................................................................45 Interpolating Half-Band Filters and AGC...............................29 Channel BIST..............................................................................45 Control Register and Memory Map Address Notation.............31 Channel/Chip Synchronization....................................................46 DDC Input Matrix......................................................................31 Start..............................................................................................46 DDC Data Latency.....................................................................31 Hop...............................................................................................48 Rev. 0 | Page 2 of 76

AD6652 Parallel Output Ports.......................................................................50 Pin_Sync Control Register.........................................................57 Channel Mode.............................................................................50 Sleep Control Register................................................................57 AGC Mode...................................................................................51 Data Address Registers...............................................................57 Master/Slave PCLK Modes........................................................52 Channel Address Registers (CAR)............................................57 Parallel Port Pin Functions........................................................52 Input Port Control Registers.....................................................63 Link Port...........................................................................................53 Output Port Control Registers..................................................64 Link Port Data Format...............................................................53 Microport Control......................................................................71 Link Port Timing.........................................................................53 Applications.....................................................................................73 TigerSHARC Configuration......................................................54 AD6652 Receiver Applications..................................................73 External Memory Map...................................................................55 Design Guidelines.......................................................................73 Access Control Register (ACR).................................................56 AD6652 Evaluation Board and Software.....................................75 Channel Address Register (CAR).............................................56 Outline Dimensions........................................................................76 Soft_Sync Control Register........................................................56 Ordering Guide...........................................................................76 REVISION HISTORY 7/04—Revision 0: Initial Version Rev. 0 | Page 3 of 76

AD6652 PRODUCT DESCRIPTION digitizes a wide spectrum of IF frequencies and then down- The AD6652 is a mixed-signal IF to baseband receiver converts the desired signals to baseband using individual consisting of dual 12-bit 65 MSPS ADCs and a wideband channel NCOs. The AD6652 provides user-configurable digital multimode digital downconverter (DDC). The AD6652 is filters for removal of undesired baseband components, and the designed to support communications applications where low data is then passed on to an external DSP, where demodulation cost, small size, and versatility are desired. The AD6652 is also and other signal processing tasks are performed to complete the suitable for other applications in imaging, medical ultrasound, information retrieval process. Each receive channel is independ- instrumentation, and test equipment. ently configurable to provide simultaneous reception of the The dual ADC core features a multistage differential pipelined carrier to which it is tuned. This IF sampling architecture architecture with integrated output error correction logic. Both greatly reduces component cost and complexity compared with ADCs feature wide bandwidth differential sample-and-hold traditional analog techniques or less integrated digital methods. analog input amplifiers supporting a variety of user-selectable High dynamic range decimation filters offer a wide range of input ranges. An integrated voltage reference eases design decimation rates. The RAM-based architecture allows easy considerations. A duty cycle stabilizer is provided to compen- reconfiguration for multimode applications. The decimating sate for variations in the ADC clock duty cycle, allowing the filters remove unwanted signals and noise from the channel of converters to maintain excellent performance. interest. When the channel occupies less bandwidth than the ADC data outputs are internally connected directly to the input signal, this rejection of out-of-band noise is referred to as receiver’s digital downconverter (DDC) input matrix, simplify- processing gain. By using large decimation factors, this process- ing layout and reducing interconnection parasitics. Overrange ing gain can improve the SNR of the ADC by 20 dB or more. In bits are provided for each ADC channel to alert the user to addition, the programmable RAM coefficient filter allows ADC clipping. Level indicator bits are also provided for each antialiasing, matched filtering, and static equalization functions DDC input port that can be used for external digital VGA to be combined in a single, cost-effective filter. control. Flexible power-down options allow significant power savings, The digital receiver has four reconfigurable channels and when desired. provides extraordinary processing flexibility. The receiver input PRODUCT HIGHLIGHTS matrix routes the ADC data to individual channels, or to all four receive processing channels. Each receive channel has five • Integrated dual 12-bit 65 MSPS ADC. cascaded signal processing stages: a 32-bit frequency translator • Integrated wideband digital downconverter (DDC). (numerically controlled oscillator (NCO)), two fixed-coefficient decimating filters (CIC), a programmable RAM coefficient • Proprietary, differential SHA input maintains excellent decimating FIR filter (RCF), and an interpolating half-band SNR performance for input frequencies up to 200 MHz. filter/AGC stage. Following the CIC filters, one, several, or all channels can be configured to use one, several, or all the RCF • Crossbar-switched digital downconverter input ports. filters. This permits the processing power of four 160-tap RCF FIR filters to be combined or used individually. • Digital resampling permits noninteger relationships between the ADC clock and the digital output data rate. After FIR filtering, data can be routed directly to the two external 16-bit output ports. Alternatively, data can be routed • Energy-saving power-down modes. through two additional half-band interpolation stages, where up • 32-bit NCOs with selectable amplitude and phase dithering to four channels can be combined (interleaved), interpolated, for better than −100 dBc spurious performance. and processed by an automatic gain control (AGC) circuit with 96 dB range. The outputs from the two AGC stages are also • CIC filters with user-programmable decimation and routed directly to the two external 16-bit output ports. Each interpolation factors. output port has a 16-bit parallel output and an 8-bit link port to permit seamless data interface with DSP devices such as the • 160-tap RAM coefficient filter for each DDC channel. TS-101 TigerSHARC® DSP. A multiplexer for each port selects one of six data sources to appear on the device outputs pins. • Dual 16-bit parallel output ports and dual 8-bit link ports. The AD6652 is part of the Analog Devices SoftCell® multimode • 8-bit microport for register programming, register read- and multicarrier transceiver chipset. The SoftCell receiver back, and coefficient memory programming. Rev. 0 | Page 4 of 76

AD6652 SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Table 1. Parameter Temp Test Level Min Typ Max Unit AVDD Full IV 2.75 3.0 3.3 V VDD Full IV 2.25 2.5 2.75 V VDDIO Full IV 3.0 3.3 3.6 V T IV −40 +25 +85 °C AMBIENT ADC DC SPECIFICATIONS AVDD = 3.0 V, VDD = 2.5 V, VDDIO = 3.3 V, 61.44 MSPS, −1.0 dBFS differential input, 1.0 V internal reference, unless otherwise noted. Table 2. Parameter (Conditions) Temp Test Level Min Typ Max Unit RESOLUTION Full IV 12 Bits INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Full IV ±5 ±35 mV Load Regulation @ 1.0 mA Full V 0.8 mV Output Voltage Error (0.5 V Mode) Full V ±2.5 mV Load Regulation @ 0.5 mA Full V 0.1 mV INPUT REFERRED NOISE Input Span = 1 V Internal 25°C V 0.54 LSB rms Input Span = 2 V Internal 25°C V 0.27 LSB rms ANALOG INPUT Input Span = 1.0 V Full IV 1 V p-p Input Span = 2.0 V Full IV 2 V p-p Input Capacitance Full V 7 pF REFERENCE INPUT RESISTANCE Full V 7 kΩ MATCHING CHARACTERISTICS Offset Error Full V ±0.1 % FSR Gain Error Full V ±0.1 % FSR ADC SWITCHING SPECIFICATIONS AVDD = 3.0 V, VDD = 2.5 V, VDDIO = 3.3 V, 61.44 MSPS, −1.0 dBFS differential input, 1.0 V internal reference, unless otherwise noted. Table 3. Parameter (Conditions) Temp Test Level Min Typ Max Unit SWITCHING PERFORMANCE Maximum Conversion Rate Full IV 65 MSPS Minimum Conversion Rate Full V 1 MSPS ACLK Period Full V 15.4 ns ACLK Pulse Width High1 Full V 6.2 ACLK/2 ns ACLK Pulse Width Low1 Full V 6.2 ACLK/2 ns DATA OUTPUT PARAMETERS Wake-Up Time2 Full V 2.5 ms OUT-OF-RANGE RECOVERY TIME Full V 2 Cycles 1 Duty cycle stabilizer enabled. 2 Wake-up time is dependent on the value of decoupling capacitors, typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB. Rev. 0 | Page 5 of 76

AD6652 ADC AC SPECIFICATIONS AVDD = 3.0 V, VDD = 2.5 V, VDDIO = 3.3 V, 61.44 MSPS, −1.0 dBFS differential input, 1.0 V internal reference. Table 4. Parameter (Conditions) Temp Test Level Min Typ Max Unit SIGNAL-TO-NOISE RATIO1 (WITHOUT HARMONICS) Analog Input Frequency 10.4 MHz 25°C V 90 dB Full V 90 dB 25.0 MHz 25°C II 85 90 dB Full V 90 dB 68.0 MHz 25°C II 84 89.5 dB Full V 88.5 dB 101 MHz 25°C V 88.0 dB 150 MHz 25°C V 87.5 dB 200 MHz 25°C V 85 dB WORST HARMONIC (2nd or 3rd)1 Analog Input Frequency 10.4 MHz 25°C V −85 dBc Full V −83 dBc 25 MHz 25°C II −83 −71 dBc Full V −80 dBc 68 MHz 25°C II −80 dBc Full V −76 dBc 101 MHz 25°C V −79 dBc 150 MHz 25°C V −72 dBc 200 MHz 25°C V −69 dBc TWO-TONE IMD REJECTION (TWO TONES SEPARATED BY 1 MHz)2 Analog Inputs = 15/16 MHz 25°C V −81 dBc Analog Inputs = 55/56 MHz 25°C V −79 dBc CHANNEL ISOLATION/CROSSTALK3 Full V 85 dB 1 Analog Input A or B = single tone @ −1 dB below full scale, 150 kHz DDC filter bandwidth. 2 Analog Input A or B = each single tone @ −7 dB below full scale, 5 MHz DDC filter bandwidth. 3 Analog Inputs A and B = each single tone @ −1 dB below full scale at 4.3 MHz and 68 MHz, 150 kHz DDC filter bandwidth. Rev. 0 | Page 6 of 76

AD6652 ELECTRICAL CHARACTERISTICS AVDD = 3.0 V, VDD = 2.5 V, VDDIO = 3.3 V, 61.44 MSPS, −1.0 dBFS differential input, 1.0 V internal reference, unless otherwise noted. Table 5. Parameter (Conditions) Temp Test Level Min Typ Max Unit LOGIC INPUTS Logic Compatibility Full IV 3.3 V CMOS Logic 1 Voltage Full IV 2.0 V Logic 0 Voltage Full IV 0.8 V Logic 1 Current Full IV −10 +10 µA Logic 0 Current Full IV −10 +10 µA Input Capacitance 25°C V 4 pF LOGIC OUTPUTS Logic Compatibility Full IV 3.3 V CMOS/TTL Logic 1 Voltage (V ) (I = 0.25 mA) Full IV 2.4 VDDIO − 0.2 V OH OH Logic 0 Voltage (V ) (I = 0.25 mA) Full IV 0.2 0.4 V OL OL SUPPLY CURRENTS Narrow Band (150 kHz BW) (61.44 MHz CLK) Four Individual Channels I 25°C II 160 200 215 mA AVDD I 25°C II 240 280 300 mA VDD I 25°C II 25 40 45 mA VDDIO CDMA (1.25MHz BW) (61.44 MHz CLK) Example1 I 25°C V 200 mA AVDD I 25°C V 336 mA VDD I 25°C V 68 mA VDDIO WCDMA (5 MHz BW) (61.44 MHz CLK) Example1 I 25°C V 200 mA AVDD I 25°C V 330 mA VDD I 25°C V 89 mA VDDIO TOTAL POWER DISSIPATION Narrow Band (150 kHz BW) (61.44 MHz CLK) 25°C II 1.2 1.5 1.6 W Four Individual Channels CDMA (61.44 MHz)1 25°C V 1.7 W WCDMA (61.44 MHz)1 25°C V 1.7 W ADC in Standby and DDC in Sleep Mode2 25°C V 2.3 mW 1 All signal processing stages and all DDC channels active. 2 ADC standby power measured with ACLK inactive. Rev. 0 | Page 7 of 76

AD6652 GENERAL TIMING CHARACTERISTICS All timing specifications valid over VDD range of 2.25 V to 2.75 V and VDDIO range of 3.0 V to 3.6 V. CLOAD = 40 pF on all outputs, unless otherwise specified. Table 6. Parameter (Conditions) Temp Test Level Min Typ Max Unit CLK TIMING REQUIREMENTS t CLK Period Full IV 15.4 ns CLK t CLK Width Low Full IV 6.2 t /2 ns CLKL CLK t CLK Width High Full IV 6.2 t /2 ns CLKH CLK RESET TIMING REQUIREMENTS t RESET Width Low Full IV 30.0 ns RESL LEVEL INDICATOR OUTPUT SWITCHING CHARACTERISTICS tDLI ↑CLK to LI (LIA, LIA; LIB, LIB) Output Delay Time Full IV 3.3 10.0 ns SYNC TIMING REQUIREMENTS tSS SYNC(A,B,C,D) to ↑CLK Setup Time Full IV 2.0 ns tHS SYNC(A,B,C,D) to ↑CLK Hold Time Full IV 1.0 ns PARALLEL PORT TIMING REQUIREMENTS (MASTER MODE) Switching Characteristics1 tDPOCLKL ↓CLK to ↑PCLK Delay (Divide-by-1) Full IV 6.5 10.5 ns tDPOCLKLL ↓CLK to ↑PCLK Delay (Divide-by-2, -4, or -8) Full IV 8.3 14.6 ns tDPREQ ↑PCLK to ↑PxREQ Delay 1.0 ns tDPP ↑PCLK to Px[15:0] Delay 0.0 ns Input Characteristics tSPA PxACK to ↓PCLK Setup Time 7.0 ns tHPA PxACK to ↓PCLK Hold Time −3.0 ns PARALLEL PORT TIMING REQUIREMENTS (SLAVE MODE) Switching Characteristics1 t PCLK Period Full IV 12.5 ns POCLK t PCLK Low Period (when PCLK Divisor = 1) Full IV 2.0 0.5 × t ns POCLKL POCLK t PCLK High Period (when PCLK Divisor = 1) Full IV 2.0 0.5 × t ns POCLKH POCLK tDPREQ ↑PCLK to ↑PxREQ Delay 10.0 ns tDPP ↑PCLK to Px[15:0] Delay 11.0 ns Input Characteristics tSPA PxACK to ↓PCLK Setup Time IV 1.0 ns tHPA PxACK to ↓PCLK Hold Time IV 1.0 ns LINK PORT TIMING REQUIREMENTS Switching Characteristics1 tRDLCLK ↑PCLK to ↑LxCLKOUT Delay Full IV 2.5 ns tFDLCLK ↓PCLK to ↓LxCLKOUT Delay Full IV 0 ns tRLCLKDAT ↑LCLKOUT to Lx[7:0] Delay Full IV 0 2.9 ns tFLCLKDAT ↓LCLKOUT to Lx[7:0] Delay Full IV 0 2.2 ns 1 The timing parameters for Px[15:0], PxREQ, and PxACK apply for Port A and B (x stands for A or B). Rev. 0 | Page 8 of 76

AD6652 MICROPROCESSOR PORT TIMING CHARACTERISTICS All timing specifications valid over VDD range of 2.25 V to 2.75 V and VDDIO range of 3.0 V to 3.6 V. CLOAD = 40 pF on all outputs, unless otherwise specified. Table 7. MICROPROCESSOR PORT, MODE INM (MODE = 0) Temp Test Level Min Typ Max Unit MODE INM WRITE TIMING tSC Control1 to ↑CLK Setup Time Full IV 2.0 ns tHC Control1 to ↑CLK Hold Time Full IV 2.5 ns t WR(R/W) to RDY(DTACK) Hold Time Full IV 7.0 ns HWR t Address/Data to WR(R/W) Setup Time Full IV 3.0 ns SAM t Address/Data to RDY(DTACK) Hold Time Full IV 5.0 ns HAM t WR(R/W) to RDY(DTACK) Delay Full IV 8.0 ns DRDY t WR(R/W) to RDY(DTACK) High Delay Full IV 4 × t 5 × t 9 × t ns ACC CLK CLK CLK MODE INM READ TIMING tSC Control1 to ↑CLK Setup Time Full IV 5.0 ns tHC Control1 to ↑CLK Hold Time Full IV 2.0 ns t Address to RD(DS) Setup Time Full IV 0.0 ns SAM t Address to Data Hold Time Full IV 5.0 ns HAM t RD(DS) to RDY(DTACK) Delay Full IV 8.0 ns DRDY t RD(DS) to RDY(DTACK) High Delay Full IV 8 × t 10 × t 13 × t ns ACC CLK CLK CLK MICROPROCESSOR PORT, MODE MNM (MODE = 1) Temp Test Level Min Typ Max Unit MODE MNM WRITE TIMING tSC Control1 to ↑CLK Setup Time Full IV 2.0 ns tHC Control1 to ↑CLK Hold Time Full IV 2.5 ns t DS(RD) to DTACK(RDY) Hold Time Full IV 8.0 ns HDS t R/W(WR) to DTACK(RDY) Hold Time Full IV 7.0 ns HRW t Address/Data To R/W(WR) Setup Time Full IV 3.0 ns SAM t Address/Data to R/W(WR) Hold Time Full IV 5.0 ns HAM t DS(RD) to DTACK(RDY) Delay Full IV 8.0 ns DDTACK t R/W(WR) to DTACK(RDY) Low Delay Full IV 4 × t 5 × t 9 × t ns ACC CLK CLK CLK MODE MNM READ TIMING tSC Control1 to ↑CLK Setup Time Full IV 5.0 ns tHC Control1 to ↑CLK Hold Time Full IV 2.0 ns t DS(RD) to DTACK(RDY) Hold Time Full IV 8.0 ns HDS t Address to DS(RD) Setup Time Full IV 0.0 ns SAM t Address to Data Hold Time Full IV 5.0 ns HAM t DS(RD) to DTACK(RDY) Delay Full IV 8.0 ns DDTACK t DS(RD) to DTACK(RDY) Low Delay Full IV 8 × t 10 × t 13 × t ns ACC CLK CLK CLK 1 Specification pertains to control signals: R/W, (WR), DS, (RD), and CS. Rev. 0 | Page 9 of 76

AD6652 ABSOLUTE MAXIMUM RATINGS Table 8. Stresses above those listed under the Absolute Maximum Parameter Rating Ratings may cause permanent damage to the device. This is a ELECTRICAL stress rating only; functional operation of the device at these or AVDD Voltage −0.3 V to +3.9 V any other conditions above those indicated in the operational VDD Voltage −0.3 V to +2.75 V section of this specification is not implied. Exposure to absolute VDDIO Voltage −0.3 V to +3.9 V maximum rating conditions for extended periods may affect AGND, DGND −0.3 V to +0.3 V device reliability. ADC VINA, VINB Analog Input Voltage −0.3 V to AVDD + 0.3 V THERMAL CHARACTERISTICS ADC Digital Input Voltage −0.3 V to AVDD + 0.3 V ADC OTRA, OTRB Digital Output Voltage −0.3 V to VDDIO + 0.3 V 256-lead CSPBGA, 17 mm sq. ADC VREF, REFA, REFB Input Voltage −0.3 V to AVDD + 0.3 V DDC Digital Input Voltage −0.3 V to VDDIO + 0.3 V θJA = 23°C/W, still air. DDC Digital Output Voltage −0.3 V to VDDIO + 0.3 V Estimate based on JEDEC JC51-2 model using horizontally ENVIRONMENTAL positioned 4-layer board. Operating Temperature Range −40°C to +85°C (Ambient) TEST LEVEL Maximum Junction Temperature 150°C I. 100% production tested. Under Bias II. 100% production tested at 25°C. Storage Temperature Range (Ambient) −65°C to +150°C III. Sample tested only. IV. Parameter guaranteed by design and characterization testing. V. Parameter is a typical value only. VI. 100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 10 of 76

AD6652 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 9. BGA Pin Configuration (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A DGND PA7_LA7 A2 PA6_LA6 D1 D3 CS RESET MODE SYNCD OTRA PDWN AVDD AVDD AGND AGND B CDoon nNeoctt PA4_LA4 PLOAAUCCTHL K0 _ A0 DGND R/W (WR) D4 D6 SYNCC SYNCA LIA DUTYEN AVDD AVDD AGND AGND C PA9 PA3_LA3 A1 DS (RD) D0 D2 D5 D7 D(RTDAYC)K SYNCB LIA LIB AVDD AVDD AGND VIN+B D PA1_LA1 PA2_LA2 PLAACCHLK1I_N VDD VDD VDD VDD VDDIO VDDIO VDDIO VDDIO VDDIO AVDD AVDD AGND VIN−B E PA8 PA5_LA5 n.c. VDD VDD VDD VDD VDDIO VDDIO VDDIO VDDIO VDDIO AVDD AVDD AGND AGND F PA0_LA0 DGND PA10 DGND DGND DGND DGND DGND DGND DGND DGND VDDIO AVDD AGND AGND AGND G PA12 PA11 PA13 DGND DGND DGND DGND DGND DGND DGND DGND VDDIO AVDD AGND REFBB REFTB H PAREQ PA15 PA14 DGND DGND DGND DGND DGND DGND DGND DGND VDDIO AVDD AGND AGND SENSE J CHIP_ID1 DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND VDDIO AVDD AGND AGND VREF K CHIP_ID3 PAACK CHIP_ID0 DGND DGND DGND DGND DGND DGND DGND DGND VDDIO AVDD AGND REFBA REFTA L PB6_LB6 PB7_LB7 DGND DGND DGND DGND DGND DGND DGND DGND DGND VDDIO AVDD AGND AGND AGND M CHIP_ID2 PB3_LB3 PB4_LB4 VDDIO VDDIO VDDIO VDDIO VDD VDD VDD VDD VDDIO AVDD AVDD AGND AGND N PAIQ PLBBCCLHK1 _IN PB2_LB2 VDDIO VDDIO VDDIO VDDIO VDD VDD VDD VDD VDDIO AVDD AVDD AGND VIN−A P DGND PB0_LB0 PB8 PB10 PB14 VDDIO PBACK LIB n.c. n.c. OTRB n.c. AVDD AVDD AGND VIN+A R PBIQ PBBCCLKHO0U_LT PB1_ LB1 PB9 PB12 PB15 n.c. n.c. n.c. n.c. n.c. PDWN AVDD AVDD AGND AGND T DGND PCLK PB5_ LB5 PB11 PB13 PBREQ n.c. n.c. n.c. n.c. DCLK SHRDREF AVDD ACLK AGND AGND Rev. 0 | Page 11 of 76

AD6652 Table 10. Pin Function Descriptions Pin No. Mnemonic Type Function POWER SUPPLY A13, B13, C13, D13, E13, F13, G13, H13, J13, K13, L13, M13, N13, P13, R13, AVDD Power 3.0 V Analog Supply, 25 Pins. T13, A14, B14, C14, D14, E14, M14, N14, P14, R14 D4, D5, D6, D7, E4, E5, E6, E7, M8, M9, M10, M11, N8, N9, N10, N11 VDD Power 2.5 V Digital Core Supply, 16 Pins. D8, D9, D10, D11, D12, E8, E9, E10, E11, E12, F12, G12, H12, J12, K12, L12, VDDIO Power 3.3 V Digital I/O Supply, 27 Pins. M4, M5, M6, M7, M12, N4, N5, N6, N7, N12, P6 A1, B5, F2, F4, F5, F6, F7, F8, F9, F10, F11, G4, G5, G6, G7, G8, G9, G10, G11, DGND Ground Digital Ground, 56 Pins. H4, H5, H6, H7, H8, H9, H10, H11, J2, J3, J4, J5, J6, J7, J8, J9, J10, J11, K4, K5, K6, K7, K8, K9, K10, K11, L3, L4, L5, L6, L7, L8, L9, L10, L11, P1, T1 A15, A16, B15, B16, C15, D15, E15, E16, F14, F15, F16, G14, H14, H15, J14, AGND Ground Analog Ground, 28 Pins. J15, K14, L14, L15, L16, M15, M16, N15, P15, R15, R16, T15, T16 MISCELLANEOUS E3, P9, P10, P12, R7, R8, R9, R10, R11, T7, T8, T9, T10 NC N/A No Connect, 13 Pins. B1 DNC N/A Do Not Connect. Pin No. Mnemonic Type Function ADC INPUTS P16 VIN+A Input Differential Analog Input Pin (+) for Channel A. N16 VIN−A Input Differential Analog Input Pin (−) for Channel A. C16 VIN+B Input Differential Analog Input Pin (+) for Channel B. D16 VIN−B Input Differential Analog Input Pin (−) for Channel B. J16 VREF I/O Voltage Reference Input/Output. H16 SENSE Input Voltage Reference Mode Select. T14 ACLK Input ADC Master Clock. B12 DUTYEN Input Duty Cycle Stabilizer, Active High. A12, R12 PDWN1 Input Power-Down Enable, Active High. T12 SHRDREF Input Shared Voltage Reference Select, Low = Independent, High = Shared. ADC OUTPUTS A11 OTRA Output Out-of-Range Indicator for Channel A, High = Overrange. P11 OTRB Output Out-of-Range Indicator for Channel B, High = Overrange. K16 REFTA Output Top Reference Voltage, Channel A. G16 REFTB Output Top Reference Voltage, Channel B. K15 REFBA Output Bottom Reference Voltage, Channel A. G15 REFBB Output Bottom Reference Voltage, Channel B. DDC INPUTS A8 RESET Input Master Reset, Active Low. T11 DCLK Input DDC Master Clock. T2 PCLK I/O Link Port Clock Output or Parallel Port Clock Input. D3 PACH1_LACLKIN 2 I/O Channel ID Output Bit, MSB, for Parallel Port A, or Link Port A Data Ready Input. Function depends on logic state of 0x1B:7 of output port control register. N2 PBCH1_LBCLKIN2 I/O Channel ID Output Bit, MSB, for Parallel Port B, or Link Port B Data Ready Input. Function depends on logic state of 0x1D:7 of output port control register. B10 SYNCA3 Input Hardware Sync, Pin A, Routed to All Receiver Channels. C10 SYNCB3 Input Hardware Sync, Pin B, Routed to All Receiver Channels. B9 SYNCC3 Input Hardware Sync, Pin C, Routed to All Receiver Channels. A10 SYNCD3 Input Hardware Sync, Pin D, Routed to All Receiver Channels. K3, J1, M1, CHIP_ID[3:0]3 Input Chip ID Selector, Four Pins, Used in Conjunction with Access Control Register K1 Bits 5–2. Rev. 0 | Page 12 of 76

AD6652 Pin No. Mnemonic Type Function DDC OUTPUTS B11 LIA Output Level Indicator, Input A, Data A. C11 LIA Output Level Indicator, Input A, Data A. C12 LIB Output Level Indicator, Input B, Data B. P8 LIB Output Level Indicator, Input B, Data B. B3 PACH0_LACLKOUT2 Output Channel ID Output Bit, LSB, for Parallel Port A, or Link Port A Clock Output. Function depends on logic state of 0x1B:7 of output port control register. R2 PACH0_LBCLKOUT2 Output Channel ID Output Bit, LSB, for Parallel Port B, or Link Port B Clock Output. Function depends on logic state of 0x1D:7 of output port control register. F1, D1, D2, PA[7:0]_LA[7:0] Output Link Port A Data or Parallel Port A Data [7:0], Eight Pins. C2, B2, E2, A4, A2 P2, R3, N3, PB[7:0_LB[7:0] Output Link Port B Data or Parallel Port B Data [7:0], Eight Pins. M2, M3, T3, L1, L2 E1, C1, F3, PA[15:8] Output Parallel Port A Data [15:8], Eight Pins. G2, G1, G3, H3, H2 P3, R4, P4, PB[15:8] Output Parallel Port B Data [15:8], Eight Pins. T4, R5, T5, P5, R6 N1 PAIQ Output Parallel Port A I or Q Data Indicator, I = High, Q = Low. R1 PBIQ Output Parallel Port B I or Q Data Indicator, I = High, Q = Low. PARALLEL OUTPUT PORT CONTROL K2 PAACK Input Parallel Port A Acknowledge. H1 PAREQ Output Parallel Port A Request. P7 PBACK Input Parallel Port B Acknowledge. T6 PBREQ Output Parallel Port B Request. MICROPORT CONTROL C5, A5, C6, D[7:0] I/O Bidirectional Microport Data, Eight Pins. This bus is three-stated when CS is high. A6, B7, C7, B8, C8 B4, C3, A3 A[2:0] Input Microport Address Bus, 3 Pins. C4 DS(RD)4 Input Function depends upon MODE pin. Active Low Data Strobe when MODE = 1. Active Low Read Strobe when MODE = 0. C9 DTACK(RDY)4, 5 Output Function depends upon MODE pin. Active Low Data Acknowledge when MODE = 1. Microport Status Pin when MODE = 0. B6 R/W (WR)4 Input Read/Write Strobe when MODE = 1. Active Low Write strobe when MODE = 0. A9 MODE4 Input Mode Select Pin. 0 = Intel mode, 1 = Motorola mode. A7 CS3 Input Active Low Chip Select. Logic 1 three-states the microport data bus. 1 PDWN pins must be the same logic level: both logic high or both logic low. 2 PACH0 and PACH1 form a 2-bit output word in the parallel output mode that identifies the processing channel (0, 1, 2, or 3) whose data appears on Port A parallel outputs. Likewise, PBCH0 and PBCH1 identify the channel for Port B. 3 Pins with a pull-down resistor of nominal 70 kΩ. 4 Mode 0 is Intel nonmultiplexed (IMN), and Mode 1 is Motorola nonmultiplexed (MNM). Pin logic level corresponds to mode. 5 Pins with a pull-up resistor of nominal 70 kΩ. Rev. 0 | Page 13 of 76

AD6652 TYPICAL PERFORMANCE CHARACTERISTICS 0 0 –10 AIN =–1dBFS –10 32k FFT SNR = 90dB (200kHz BW) –20 32k FFT –20 –30 –30 –40 –40 –50 –50 –60 –60 S –70 S –70 F F dB –80 dB –80 –90 –90 –100 –100 –110 –110 –120 –120 –130 –130 –140 –140 –150–300 –200 –10F0REQUEN0CY (kHz1)00 200 300 03198-0-060 –150–300 –200 –10F0REQUEN0CY (kHz1)00 200 300 03198-0-059 Figure 2. GSM/EDGE with Single Tone AIN = 30 MHz; Encode = 61.44 MSPS Figure 5. GSM/EDGE Carrier AIN = 30 MHz; Encode = 61.44 MSPS 0 0 –10 AIN =–1dBFS –10 32k FFT SNR = 80dB (1.25MHz BW) –20 32k FFT –20 –30 –30 –40 –40 –50 –50 –60 –60 S –70 S –70 F F dB –80 dB –80 –90 –90 –100 –100 –110 –110 –120 –120 –130 –130 –140 –140 –150–1.2 –0.8 –0.F4REQUEN0CY (MHz0).4 0.8 1.2 03198-0-062 –150–1.2 –0.8 –0.F4REQUEN0CY (MHz0).4 0.8 1.2 03198-0-061 Figure 3. CDMA2000 with Single Tone AIN = 76 MHz; Encode = 61.44 MSPS Figure 6. CDMA2000 Carrier AIN = 76 MHz; Encode = 61.44 MSPS 0 0 –10 AIN =–1dBFS –10 32k FFT SNR = 70dB (5MHz BW) –20 32k FFT –20 –30 –30 –40 –40 –50 –50 –60 –60 S –70 S –70 F F dB –80 dB –80 –90 –90 –100 –100 –110 –110 –120 –120 –130 –130 –140 –140 –150–4 –3 –2 F–R1EQUEN0CY (MH1z) 2 3 4 03198-0-064 –150–4 –3 –2 F–R1EQUEN0CY (MH1z) 2 3 4 03198-0-063 Figure 4. WCDMA with Single Tone AIN = 169 MHz; Encode = 61.44 MSPS Figure 7. WCDMA Carrier AIN = 169 MHz; Encode = 61.44 MSPS Rev. 0 | Page 14 of 76

AD6652 0 0 ENCODE = 61.44MSPS ENCODE = 61.44MSPS –10 –10 AIN =–7dBFS AIN =–7dBFS –20 32k FFT –20 32k FFT –30 –30 –40 –40 –50 –50 –60 –60 S –70 S –70 F F dB –80 dB –80 –90 –90 –100 –100 –110 –110 –120 –120 –130 –130 –140 –140 –150–4 –3 –2 F–R1EQUEN0CY (MH1z) 2 3 4 03198-0-070 –150–4 –3 –2 F–R1EQUEN0CY (MH1z) 2 3 4 03198-0-066 Figure 8. Two Tones at 15 MHz and 16 MHz Figure 11. Two Tones at 55 MHz and 56 MHz 100 100 90 90 BW] 80 BW] 80 Hz Hz k k 0 0 15 70 15 70 B) [ SNR B) [ SNR d d R ( 60 R ( 60 N N S S 50 50 40–60 –50 ANAL–O4G0 INPUT –A3M0PLITUD–E2 0(dBFS)–10 0 03198-0-071 40–60 –50 ANAL–O4G0 INPUT –A3M0PLITUD–E2 0(dBFS)–10 0 03198-0-072 Figure 9. Noise vs. Analog Amplitude at 25 MHz Figure 12. Noise vs. Analog Amplitude at 68 MHz 100 100 90 90 c) 80 c) 80 B B d d NICS ( 70 HARMONICS NICS ( 70 HARMONICS O O HARMONICS = 80dB RM RM REFERENCE LINE HA 60 HRAEFREMROENNICCSE =L I8N0EdB HA 60 50 50 40–60 –50 ANAL–O4G0 INPUT –A3M0PLITUD–E2 0(dBFS)–10 0 03198-0-073 40–60 –50 ANAL–O4G0 INPUT –A3M0PLITUD–E2 0(dBFS)–10 0 03198-0-074 Figure 10. Harmonics vs. Analog Amplitude at 25 MHz Figure 13. Harmonics vs. Analog Amplitude at 68 MHz Rev. 0 | Page 15 of 76

AD6652 92 92 AIN =–1dBFS AIN =–1dBFS 25°C 90 z]0kH 90 85°C 0kHz] 5 5 1 1 = = W W 88 B B B) [ B) [ d –40°C d R ( 88 R ( 25°C N N S S 86 860 10 AN2A0LOG INP30UT FREQ40UENCY 5(0MHz) 60 70 03198-0-068 840 20 40ANAL60OG IN8P0UT 1F0R0EQU1E20NCY1 4(M0Hz)160 180 200 03198-0-067 Figure 14. Noise vs. Analog Frequency Figure 16. Noise vs. Analog Frequency (IF) 90 AIN =–1dBFS c) 85 B d C ( NI MO 80 R HA 25°C E AS 75 C T- S R O W 70 650 25 50ANAL7O5G FRE1Q00UENC1Y2 5(MHz)150 175 200 03198-0-069 Figure 15. Harmonics vs. Analog Frequency Rev. 0 | Page 16 of 76

AD6652 DDC TIMING DIAGRAMS t CLK t CLKL CLK t CLKH t DLI LIA, LIB LIA, LIB 03198-0-065 Figure 17. Level Indicator Output Switching Characteristics RESET tRESL 03198-0-003 Figure 18. Reset Timing Requirements CLK tSS tHS SSSSYYYYNNNNCCCCDABC 03198-0-006 Figure 19. SYNC Timing Inputs CLK tDPOCLKL PCLK 03198-0-007 Figure 20. PCLK to CLK Switching Characteristics Divide-by-1 CLK t DPOCLKLL PCLK tPOCLKH tPOCLKL 03198-0-008 Figure 21. PCLK to CLK Switching Characteristics Divide-by-2, -4, or -8 Rev. 0 | Page 17 of 76

AD6652 PCLK t HPA t SPA PxACK 03198-0-009 Figure 22. Master Mode PxACK to PCLK Setup and Hold Characteristics PCLK PxREQ t t SPA SPA PxACK t t DPP DPP Px[15:0] DATA 1 DATA 2 DATA N– 1 DATA N 03198-0-010 Figure 23. Master Mode PxACK to PCLK Switching Characteristics PCLK PxACK t DPREQ PxREQ t t DPP DPP Px[15:0] DATA 1 DATA N 03198-0-011 Figure 24. Master Mode PxREQ to PCLK Switching Characteristics t POCLKL PCLK t POCLKH t SPA t HPA PxACK 03198-0-012 Figure 25. Slave Mode PxACK to PCLK Setup and Hold Characteristics Rev. 0 | Page 18 of 76

AD6652 PCLK PxREQ t t SPA SPA PxACK t t DPP DPP Px[15:0] DATA 1 DATA 2 DATA N– 1 DATA N 03198-0-013 Figure 26. Slave Mode PxACK to PCLK Switching Characteristics PCLK PxACK t DPREQ PxREQ t t DPP DPP Px[15:0] DATA 1 DATA N 03198-0-014 Figure 27. Slave Mode PxREQ to PCLK Switching Characteristics PCLK LxCLKOUT tRDLCLK tFDLCL 03198-0-015 Figure 28. LxCLKOUT to PCLK Switching Characteristics Rev. 0 | Page 19 of 76

AD6652 LxCLKOUT WAIT≥ 6 CYCLES ONE TIME CONNECTIVITY CHECK 8 LxCLKOUT CYCLES NEXT TRANSFER ACKNOWLEDGE LxCLKIN NEXT TRANSFER BEGINS Lx[7:0] D0 D1 D2 D3 D4 D15 D0 D1 D2 D3 03198-0-016 Figure 29. LxCLKIN to LxCLKOUT Data Switching Characteristics LxCLKOUT Lx[7:0] 03198-0-017 t t FDLCLKDAT RDLCLKDAT Figure 30. LxCLKOUT to Lx[7:0] Data Switching Characteristics CLK RD (DS) tHC tSC tHWR WR (R/W) CS tSAM tHAM A[2:0] VALID ADDRESS tSAM tHAM D[7:0] VALID DATA tDRDY RDY (DTACK) tACC NOTES 12.. ttFAARCCOCCM AR CEFQEC EUOSIFRS EW TSRI MA TE MO DA REXEPIM EOUNFMD RS OD OYFN .9 TCHLEK APDEDRRIOEDSSS. ACCESSED. ACCESS TIME IS MEASURED 03198-0-018 Figure 31. INM Microport Write Timing Requirements Rev. 0 | Page 20 of 76

AD6652 CLK tSC tHC RD (DS) WR (RW) CS tSAM A[2:0] VALID ADDRESS tHA D[7:0] VALID DATA tDRDY RDY (DTACK) tACC NOTES 12..ttFAARCCOCCM AR CEFEQC EUOSIFRS EW TSRI MA TE MO D AREXEPI MEONUFDM RS DO OYFN. 1 3T HCEL KA DPDERRIEOSDSS A.CCESSED. ACCESS TIME IS MEASURED 03198-0-019 Figure 32. INM Microport Read Timing Requirements CLK tSC tHC tHDS DS (RD) tHRW RW (WR) CS tSAM tHAM A[2:0] VALID ADDRESS tSAM tHAM D[7:0] VALID DATA tDDTACK DTACK (RDY) tACC NOTES 12..ttFAARCCOCCM AR CEFQEC EUOSIFRS ED TSSI M ATE OM DATEHXPEIME FUNEMD OS O FOF DN 9T TCAHLCEKK A.PDEDRRIOEDSSS. ACCESSED. ACCESS TIME IS MEASURED 03198-0-020 Figure 33. MNM Microport Write Timing Requirements Rev. 0 | Page 21 of 76

AD6652 CLK tSC tHC tHDS DS (RD) R/W (WR) CS tSAM A[2:0] VALID ADDRESS tHA D[7:0] VALID DATA tDDTACK DTACK (RDY) tACC NOTES 12.. ttFAARCCOCC MAR CETQCHEUES IFRSEE TSOI MFA E DM SDA ETXPOIME TUNHMDES O FOFEN 1O 3TF HC DELT KAA DPCDEKRR.IEOSDSS A.CCESSED. ACCESS TIME IS MEASURED 03198-0-021 Figure 34. MNM Microport Read Timing Requirements Rev. 0 | Page 22 of 76

AD6652 TERMINOLOGY Crosstalk ADC EQUIVALENT CIRCUITS Coupling onto one channel being driven by a (−0.5 dBFS) signal AVDD when the adjacent interfering channel is driven by a full-scale signal. Measurement includes all spurs resulting from both direct coupling and mixing components. IF Sampling (Undersampling) Due to the effects of aliasing, an ADC is not necessarily limited tamopu pNsetya qbru ei nitsa ttk hseaenm f itprosl itln iNmgy.i Ftq rutheiqsetu bzeaonnncdeiew (sdi adcbt htoo vo Sef a Ntmhyepq lsueai msRta patlreee/d 2a )sl.ii agCsnaeardle saon d 03198-0-022 Figure 35. Analog Input Circuit that it does not overlap Nyquist zones and alias onto itself. IF sampling performance is limited by the bandwidth of the input SHA (sample-and-hold amplifier) and clock jitter. (Jitter adds AVDD more noise at higher input frequencies.) Nyquist Sampling (Oversampling) Oversampling occurs when the frequency components of the analog input signal are below the Nyquist frequency (F /2), clock and requires that the analog input frequency be sampled at least two samples per cycle. Out-of-Range Recovery Time 03198-0-023 Out-of-range recovery time is the time it takes for the analog- Figure 36. Digital Input to-digital converter (ADC) to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% VDD below positive full scale. Processing Gain When the tuned channel occupies less bandwidth than the input signal, this rejection of out-of-band noise is referred to as processing gain. By using large decimation factors, this process- iTnhge g faoilnlo cwanin igm epqruoavteio tnh ec aSnN bRe oufs tehde t Ao DesCti mbya t2e0 p droBc oers sminogr ge.a in: 03198-0-024 Figure 37. Digital Output ⎡ Sample_Rate 2 ⎤ Processing_Gain=10log⎢ ⎥ ⎣Filter_Bandwidth⎦ Signal-to-Noise Ratio (SNR) The ratio of the rms value of the measured input signal to the rms sum of all other spectral components within the pro- grammed DDC filter bandwidth, excluding the first six harmonics and dc. The value for SNR is expressed in decibels (dB). Two-Tone IMD Rejection The ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product; reported in dBc. Rev. 0 | Page 23 of 76

AD6652 THEORY OF OPERATION The AD6652 has two analog input channels, four digital filter- ADC ARCHITECTURE ing channels, and two digital output channels. The IF input The AD6652 front-end consists of two high performance, 12-bit signal passes through several stages before it appears at the ADCs, preceded by differential sample-and-hold amplifiers output port(s) as a well-filtered, decimated digital baseband (SHA) that provide excellent SNR performance from dc to signal: 200 MHz. A flexible, integrated voltage reference allows analog • 12-bit A/D conversion inputs up to 2 V p-p. Each channel is equipped with an overrange pin that toggles high whenever the analog input • Frequency translation from IF to baseband using exceeds the upper or lower reference voltage boundary. ADC quadrature mixers and NCOs outputs are internally routed to the input matrix of the DDC • Second-order resampling decimating CIC FIR filter stage for channel distribution. The ADC data outputs are not (rCIC2) directly accessible to the user. • Fifth-order decimating CIC FIR filter (CIC5) Each sample-and-hold amplifier (SHA) is followed by a pipe- • RAM coefficient decimating FIR filter (RCF) lined switched capacitor ADC. The pipelined ADC is divided • Automatic gain control (AGC) into three sections, consisting of a 4-bit first stage followed by • 2× interpolation and channel interleave eight 1.5-bit stages and a final 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding Any stage can be bypassed with the exception of the ADC front stages. The quantized outputs from each stage are combined end. Any combination of processing channels can be combined into a final 12-bit result in the digital correction logic. The or interleaved after the RCF stages to achieve demanding pipelined architecture permits the first stage to operate on a filtering objectives that are not possible with just one channel. new input sample while the remaining stages operate on the In the following sections, each stage is examined to allow the preceding samples. Sampling occurs on the rising edge of the user to fully utilize the AD6652’s capabilities. clock. The dual ADC design is useful for diversity reception of signals, Analog Input Operation where the ADCs are operating identically on the same carrier The analog inputs to the AD6652 are differential switched but from two separate antennae. The ADCs can also be capacitor SHAs that have been designed for optimum perform- operated with independent analog inputs. The user can sample ance while processing differential input signals. The AD6652 any fs/2 frequency segment from dc to 100 MHz using accepts inputs over a wide common-mode range; however, an appropriate low-pass or band-pass filtering at the ADC inputs input common-mode voltage V , one-half of AVDD, is with little loss in ADC performance. Operation to 200 MHz CM recommended to maintain optimal performance and to analog input is permitted, but at the expense of increased ADC minimize signal-dependent errors. distortion. Referring to Figure 38, the clock signal alternatively switches the In nondiversity applications, up to four GSM/EDGE-type SHA between sample mode and hold mode. When the SHA is carriers can be concurrently processed from the ADC stage. switched into sample mode, the signal source must be capable Wideband signals, such as WCDMA/CDMA2000, require the of charging the sample capacitors and settling within one-half power of two AD6652 processing channels per carrier to of a clock cycle. A small resistor in series with each input can adequately remove adjacent channel interference. When help reduce the peak transient current required from the output diversity techniques are employed, the number of carriers that stage of the driving source. Also, a small shunt capacitor can be can be processed is halved due to the dual processing require- placed across the inputs to provide dynamic charging currents. ment of diversity reception. This passive network creates a low-pass filter at the ADC’s Flexible channel multiplexing in the digital downconverter input; therefore, the precise values are dependent upon the (DDC) stage allows one to four channels to be interleaved onto application. In IF undersampling applications, any shunt capaci- one output port. Four synchronization input pins allow startup, tors should be removed. In combination with the driving source frequency hop, and AGC functions to be precisely orchestrated impedance, the shunt capacitors would limit the input with other devices. The NCO’s phase can be set to produce a bandwidth. known offset relative to another channel or device. Programming and control of the AD6652 is accomplished using an 8-bit parallel interface. Rev. 0 | Page 24 of 76

AD6652 This is especially true in IF undersampling applications in For best dynamic performance, the source impedances driving which input frequencies in the range of 70 MHz to 200 MHz are the differential analog inputs should be matched such that being sampled. For these applications, differential transformer common-mode settling errors are symmetrical. These errors are coupling is the recommended input configuration, as shown in reduced by the common-mode rejection of the ADC. Figure 39. Transformer T1 is a center-tapped, 1:4 impedance H ratio broadband RF transformer. The signal characteristics must be considered when selecting a transformer. Most RF S S transformers saturate at frequencies below a few MHz, and 5pF excessive signal power can also cause core saturation, which VINA+ leads to distortion. S = SAMPLE H = HOLD AVDD S T1 50Ω 5pF VINA VINA– 10pF AD6652 1V p-p 49.9Ω S 50Ω VINB H 03198-0-025 1kΩ10pF AGND Figure 38. Switched-Capacitor SHA Input for One ADC Channel 0.1µF 1kΩ 03198-0-028 The SHA should be driven from a source that keeps the signal Figure 39. Differential AC-Coupled Input for One Channel of the AD6652 peaks within the allowable range for the selected reference ADC Voltage Reference voltage. The minimum and maximum common-mode input A stable and accurate 0.5 V voltage reference is built into the levels are defined as follows: AD6652. The input span of the ADC tracks reference voltage VCM = VREF/2 changes linearly. An internal differential reference buffer creates MIN VCM = (AVDD + VREF)/2 positive and negative reference voltages, REFT and REFB, MAX respectively, that define the span of the ADC core. The output The minimum common-mode input level allows the AD6652 to common mode of the reference buffer is set to midsupply, and accommodate ground-referenced inputs. the REFT and REFB voltages and span are defined as follows: Although optimum performance is achieved with a differential REFT = 1/2 (AVDD + VREF) input, a single-ended source can be driven into VIN+ or VIN−. REFB = 1/2 (AVDD − VREF) In this configuration, one input accepts the signal, while the Span = 2 × (REFT − REFB) = 2 × VREF opposite input should be set to midscale by connecting it to an appropriate reference. For example, a 2 V p-p signal can be As shown by the equations above, the REFT and REFB voltages applied to VIN+, while a 1 V reference is applied to VIN−. The are symmetrical about the midsupply voltage and, by definition, AD6652 then accepts a signal varying between 2 V and 0 V. In the input span is twice the value of the VREF voltage. Proper the single-ended configuration, distortion performance might operation of the AD6652 requires that VREF be no less than degrade significantly, compared to the differential case. 0.5 V and no greater than 1.0 V. However, the effect is less noticeable at lower analog input The internal voltage reference can be pin-strapped to fixed frequencies. values of 0.5 V or 1.0 V, or adjusted within the same range, as Differential Input Configurations discussed in the Internal Reference Connection section. Maxi- Optimum performance is achieved while driving the AD6652 mum SNR performance is achieved with the reference set to the inputs in a differential input configuration. For baseband largest input span of 2 V p-p. The relative SNR degradation is applications to Nyquist, the AD8138 Differential Driver 3 dB when changing from 2 V p-p mode to 1 V p-p mode. provides excellent performance and a flexible interface to the If operation using an external reference voltage is desired, it can ADC The output common-mode voltage of the AD8138 is be substituted for the internal reference, as detailed in the easily set to one-half of AVDD, and the driver can be configured External Reference Operation section. in a Sallen-Key filter topology to provide band limiting of the input signal. At input frequencies above Nyquist, the performance of most amplifiers is not adequate to achieve the true performance of the AD6652 ADC stage. Rev. 0 | Page 25 of 76

AD6652 Internal Reference Connection In all reference configurations, REFT and REFB drive the A/D A comparator within the AD6652 detects the potential at the conversion core and establish its input span. The input range of SENSE pin and configures the reference into four possible the ADC always equals twice the voltage at the reference pin for states, which are summarized in Table 11. If SENSE is grounded, either an internal or an external reference. the reference amplifier switch is connected to the internal The reference amplifier switch is located near the bottom left. resistor divider (see Figure 40), setting VREF to a FIXED 1 V The SENSE pin is shown connected to ground, which sets VREF reference output. Connecting the SENSE pin directly to VREF to 1 V. Decoupling capacitors must be duplicated for the switches the reference amplifier output to the SENSE pin, Channel B ADC core, if it is used. The Channel B ref amp and completing the loop and providing a fixed 0.5 V reference ADC core are identical to those of Channel A, but are not output. If a resistor divider is connected, as shown in Figure 41, shown. the switch is again set to the SENSE pin. This puts the reference amplifier in a noninverting mode with the VREF programmable output defined as follows: VREF = 0.5 × (1 + R2/R1) Table 11. Reference SENSE Operation Selected Mode SENSE Voltage Resulting VREF (V) Resulting Differential Span (V p-p) External Reference AVDD External Reference 2 × External Reference Internal Fixed Reference VREF 0.5 1.0 Programmable Reference 0.2 V to VREF 0.5 × (1 + R2/R1) 2 × VREF (See Figure 42) Internal Fixed Reference AGND to 0.2 V 1.0 2.0 VINA+ VINA– VINA+ REFT_A VINA– REFT_A 0.1µF 0.1µF RAEMFP A CCAOHD CRAE 0.1µF RAEMFP A CAHD CA 0.1µF 10µF CORE 10µF REFB_A REFB_A TO CH B 0.1µF WHERE R1 + R2 = TO CH B 0.1µF REF AMP 10kΩ TO 20kΩ REF AMP VREF VREF 0.5V VREF VREF 0.5V 0.1µF 10µF RINT 0.1µF 10µF RINT R2 SELECT SELECT LOGIC LOGIC SENSE SENSE R1 RINT 03198-0-029 RINT 03198-0-030 Figure 40. Fixed Internal Reference Configuration Figure 41. Programmable Reference Configuration Rev. 0 | Page 26 of 76

AD6652 External Reference Operation 1.2 An external reference voltage can be used to enhance the gain 1.0 accuracy of the ADC or improve thermal drift characteristics. When multiple ADCs track one another, a single reference VREF = 1V (internal or external) might be necessary to reduce gain- %) 0.8 matching errors to an acceptable level. A high-precision OR ( VREF = 0.5V R 0.6 external reference can also be selected to provide lower gain and R E F offset temperature drift. E R V 0.4 When the SENSE pin is tied to AVDD as in Figure 42, the internal reference is disabled, allowing the use of an external 0.2 reference. An internal reference buffer loads the external rgaenefndee rRreanEtcFeesB wt, hfioethr p taohnsei teAiqvDue iCavna cldeo nrnete . 7gTa khtiΩev e iln ofpuaudllt.- sTscphaaelne i nriset feaerlrnweanalyc bse ust,wf fReicEre Fs ttTihl le 0–40 –30 –20 –10 0 TE1M0PE2R0ATU30RE (4°0C) 50 60 70 80 90 03198-0-075 value of the reference voltage; therefore, the external reference Figure 43. Typical VREF Drift must be limited to a maximum of 1 V. 0.05 If the internal reference of the AD6652 is used to drive multiple 0 ICs, the loading on VREF by the other converters must be considered. Figure 44 shows how the internal reference voltage –0.05 is affected by loading. 0.5V ERROR %) VINA+ ROR (–0.10 VINA– REFT_A RE 1V ERROR –0.15 0.1µF RAEMFP A CAHD CA 0.1µF –0.20 CORE 10µF TROE FC AHM BP REFB_0A.1µF –0.250 0.5 1.0 LOA1D.5 (mA) 2.0 2.5 3.0 03198-0-076 0.5V TO 1.0V Figure 44. VREF Accuracy vs. Load EXTERNAL REFERENCE IN VREF VREF 0.5V RINT 0.1µF 10µF SELECT Shared Reference Mode LOGIC SENSE The shared reference mode allows the user to connect the +3.0V references from the dual ADCs together for superior gain and offset matching performance. If the ADCs are to function RINT 03198-0-031 iinnddeeppeennddeennttllyy, athned rceafner pernocvei ddee csouuppelriinogr sishooluatldio bne b tertewateeedn the Figure 42. External Reference Operation with Connections dual ADC channels. To enable shared reference mode, the Shown for Channel A Only SHRDREF pin must be tied high and the differential references must be externally shorted together, that is, REFTA must be shorted externally to REFTB and REFBA must be shorted externally to REFBB. Rev. 0 | Page 27 of 76

AD6652 Clock Input Considerations modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the Typical high speed ADCs use both clock edges to generate a ACLK clock is generated from another type of source (by variety of internal timing signals, and as a result can be sensitive gating, dividing, or other methods), re-time it by the original to ACLK clock duty cycle. Commonly a 5% tolerance is clock at the last step. required on the clock duty cycle to maintain dynamic perform- ance characteristics. The AD6652 contains a clock duty cycle ADC Power-Down Mode stabilizer that re-times the nonsampling edge, providing an The power dissipated by the AD6652 front-end ADC is propor- internal clock signal with a nominal 50% duty cycle. Duty cycle tional to its sampling rate. Normal ADC operation requires that stabilizing is engaged by setting DUTYEN to logic high. This both PDWN pins be set to logic low. The ADC can be placed in allows a wide range of ACLK clock input duty cycles without a power-down mode by setting both PDWN pins to logic high. affecting the performance of the AD6652 ADC stage. Low power dissipation in power-down mode is achieved by shutting down the reference buffers and biasing networks of The duty cycle stabilizer uses a delay-locked loop (DLL) to both ADC channels. Both power-down pins must be driven create the nonsampling edge. As a result, any changes to the together either high or low for proper ADC operation. sampling frequency require approximately 2 ms to 3 ms to allow the DLL to acquire and lock to the new rate. For maximum power savings, the ACLK and analog input(s) should remain static while in standby mode, resulting in a High speed, high resolution ADCs are sensitive to the quality of typical power consumption of 1 mW for the ADC. If the clock the clock input. The degradation in SNR at a given full-scale inputs remain active while in standby mode, typical power input frequency (f ) due only to aperture jitter (t ) can be INPUT A consumption for the ADC is 12 mW. calculated with the following equation: ADC Wake-Up Time SNR degradation = 20 × log10 [1/2 × p × f × t ] INPUT A The decoupling capacitors on REFT and REFB are discharged In the equation, the rms aperture jitter, t , represents the root- when entering standby mode, and then must be recharged when A sum square of all jitter sources, which include the clock input, returning to normal operation. As a result, the wake-up time is analog input signal, and ADC aperture jitter specification. related to the time spent in standby mode. Shorter standby Undersampling applications are particularly sensitive to jitter. cycles result in proportionally shorter wake-up times. With the recommended 0.1 µF and 10 µF decoupling capacitors on REFT To minimize clock jitter, treat the ACLK clock input as an and REFB, it takes approximately 1 s to fully discharge the analog signal. Power supplies for clock drivers should be reference buffer decoupling capacitors, and 5 ms to restore full separated from the ADC output driver supplies to avoid operation. Rev. 0 | Page 28 of 76

AD6652 DIGITAL DOWNCONVERTER ARCHITECTURE OVERVIEW DATA INPUT MATRIX RAM COEFFICIENT FILTER The digital downconverter (DDC) section features dual high The RAM coefficient filter (RCF) stage is a sum-of-products speed 12-bit input ports that are capable of crossbar multiplex- FIR filter with programmable 20-bit coefficients, and decima- ing of data to the four processing channels that follow the input tion rates programmable from 1 to 256 (1 to 32 in practice). matrix. In addition, a third input option to the matrix is Each RAM coefficient FIR filter (RCF in Figure 1) can handle a available to facilitate BIST (built-in self-test). This option is a maximum of 160 taps. Two or more RCF stages can be com- pseudorandom noise (PN) sequence. The dual input ports bined using flexible channel configuration to increase the permit diversity reception of a carrier, or they can be treated as processing power beyond the 160 tap maximum. unrelated and independent inputs. Either input port or the PN The RCF outputs of each channel can be directly routed to one sequence can be routed to any or all four tuner channels. This or both output ports or to an AGC stage, where selected DDC flexibility allows up to four signals to be processed simultane- channels can be interleaved and interpolated in a half-band ously. Refer to the DDC Input Matrix section for a more filter, if desired. complete description. INTERPOLATING HALF-BAND FILTERS AND AGC NUMERICALLY CONTROLLED OSCILLATOR Processed RCF data can also be routed to two half-band Frequency translation is accomplished with a 32-bit complex interpolation stages, where up to four channels can be numerically controlled oscillator (NCO). Each of the four combined (interleaved), interpolated by a factor of two, and processing channels contains a separate NCO. Real data automatic gain control (AGC) applied. Each AGC stage has a entering this stage is separated into in-phase (I) and quadrature dynamic range of 96.3 dB. These stages can be bypassed (Q) components. This stage translates the input signal from a independently of each other. The outputs from the two AGC digital intermediate frequency (IF) to digital baseband. Phase stages are routed to both output port multiplexers. Each output and amplitude dither can be enabled on-chip to improve has a link port to permit seamless data interface with DSP spurious performance of the NCO. A phase-offset word is devices such as the TigerSHARC. A multiplexer for each port available to create a known phase relationship between multiple selects one of the six data sources to appear at the device AD6652s or between channels. parallel or link output pins. SECOND-ORDER rCIC FILTER The overall filter response for the AD6652 is the composite of Following frequency translation is a resampling, fixed all decimating and interpolating stages. Each successive filter coefficient, high speed, second-order, resampling cascade stage is capable of narrower transition bandwidths, but requires integrator comb (rCIC2) filter, which reduces the sample rate a greater number of CLK cycles to calculate the output. More based on the ratio between the decimation and interpolation decimation in the first filter stage helps to minimize overall registers. The resampler allows for noninteger relationships power consumption. between the master clock and the output data rate. This stage can be bypassed by setting the decimation/interpolation ratio Figure 45 illustrates the basic function of the AD6652, that is, to to 1. select and filter a single carrier from a wide input spectrum and to down-convert it to baseband data. Figure 46 shows examples FIFTH-ORDER CIC FILTER of the combined filter response of the rCIC2, CIC5, and RCF for The next stage is a fifth-order cascaded integrator comb (CIC5) narrowband and wideband carriers. filter, whose response is defined by the decimation rate. The purpose of these filters is to reduce the data rate to the final filter stage and to provide antialias filtering. The reduced data rate allows the RAM coefficient filter (RCF) stage to calculate more taps per output. Rev. 0 | Page 29 of 76

AD6652 WIDEBAND INPUT SPECTRUM (–fSAMPLE/2 TO +fSAMPLE/2) SIGNAL OF INTEREST IMAGE SIGNAL OF INTEREST –fS/2 –3fS/8 –5fS/16 –fS/4 –3fS/16 –fS/8 –fS/16 DC fS/16 fS/8 3fS/16 fS/4 5fS/16 3fS/8 fS/2 WIDEBAND INPUT SPECTRUM (FOR EXAMPLE, 30MHz FROM HIGH SPEED ADC) AFTER FREQUENCY TRANSLATION NCO TUNES SIGNAL TO BASEBAND –fS/2 –3fS/8 –5fS/16 –fS/4 FRE–Q3UfSE/1N6CY TR–AfNS/S8LATIO–Nf S(/F1O6R EXAMDPCLE, SINGfSL/1E6 1MHz CfHS/A8NNEL T3UfSN/1E6D TO BfASS/4EBAND5)fS/16 3fS/8 fS/2 03198-0-032 Figure 45. AD6652 Frequency Translation of Wideband Input Spectrum 20 10 0 0 –10 –20 –30 –20 –40 –50 –40 –60 c c dB dB–70 –60 –80 –90 –100 –80 –110 –120 –100 –130 –140 –12–01.53 104 –1.03 104 –5000 kH0z 5000 1.03 104 1.53 104 –150 –1000 –800 –600 –400 –200 kH0z 200 400 600 800 1000 03198-0-033 Figure 46. Filter Response (left) Meets UMTS (Wideband) Specifications. Narrower Filter (right) Designed for EDGE Application (65 MSPS ADC Conversion Rate and 541.6 kSPS DDC Output Rate) Rev. 0 | Page 30 of 76

AD6652 CONTROL REGISTER AND MEMORY MAP ADDRESS NOTATION Table 12. Crossbar-Switched Routing of the Two 12-Bit ADC The following sections make frequent references to program- Data Streams (A and B) Using the DDC Input Matrix mable registers and the memory mapping structure of the AD6652. A good overview of the control registers and memory Channel 3 Channel 2 Channel 1 Channel 0 mapping structure is found beginning in the External Memory A A A A Map section. The following conventions are used in this A A A B addressing scheme: A A B A A A B B • Control register addresses that begin with 0x indicate that A B A A the address that follows is in hexadecimal notation. A B A B A B B A • All hexadecimal addresses are 8 bits wide, and each address A B B B can accommodate register data that is 20 bits wide; B A A A however, many of the available 20 bits per address are B A A B unused. B A B A B A B B • A colon following an address indicates the specific bit B B A A number(s), in decimal format, of the function that is being B B A B described. B B B A • Eight, 3-bit external memory map addresses are shown in B B B B decimal format in Table 22. Each of these addresses can accommodate 8 bits of register data. DDC DATA LATENCY Decimal Addressing Example: 7:4 indicates that this is an The overall signal path latency from DDC input to output can external memory address (no 0x prefix) and that the binary be expressed in high speed clock cycles. Use the following address is 111, because only 3 external address bits are assigned. equation to calculate the latency: Also, only Bit 4 of the 8-bit data field is described or referred to. T = M (M + 7) + N + 26 Hex Addressing Example: 0x0A:7–0 indicates that the binary latency rCIC2 CICS taps address is 00001010 and that Bits 7 through 0 are involved with where: the function being described. Because this address begins with 0x, the user knows that it is not an external memory address, MrCIC2 and MCIC5 are decimation values for the rCIC2 and CIC5 and can be either an individual channel address register or an filters, respectively. output port control register, depending upon how it was routed N is the number RCF taps chosen. using the external memory address registers. taps GAIN SWITCHING The largest 8-bit address that is used in the hexadecimal address scheme is A9 or 169 decimal. This might not seem to be enough The AD6652 includes circuitry that is useful in applications in memory addressing capacity, but, because addresses are re-used which large dynamic range input signals exist. This circuitry with the external memory mapping scheme, there is no shortage allows digital thresholds to be set such that an upper and a of address capability. lower threshold can be programmed. DDC INPUT MATRIX One use of this circuitry is to detect when an ADC is about to reach full scale with a particular input condition. The results The digital downconverter stages feature dual high speed provide a flag can quickly insert an attenuator to prevent ADC crossbar-switched input ports that allow the most flexibility in overdrive. If 18 dB (or any arbitrary value) of attenuation (or routing the two ADC data streams to the four receive process- gain) is switched in, then the signal dynamic range of the ing channels. Crossbar switching means that any of the four system is increased by 18 dB. The process begins when the input processing channels can receive data from either Port A or signal reaches the upper programmed threshold. In a typical Port B for a total of 16 possible combinations, as shown in application, this might be set 1 dB (user definable) below full Table 12. Input port routing is selected in each NCO’s control scale. When this input condition is met, the appropriate LI (LIA, register at 0x88:6. LIA, LIB or LIB) signal associated with either the A or B input port is made active. This can be used to switch the gain or attenuation of the external circuit. The LI line stays active until Rev. 0 | Page 31 of 76

AD6652 the input condition falls below the lower programmed used with an analog VGA. To simplify the use of this feature, the threshold. AD6652 includes two separate gain settings, one when this line is inactive (rCIC2_QUIET[4:0] stored in Bits 9:5 of 0x92 To provide hysteresis, a dwell time register (see Table 28) is register) and the other when active (rCIC2_LOUD[4:0] stored available to hold off switching of the control line for a in Bits 4:0 of 0x92 register). This allows the digital gain to be predetermined number of clocks. Once the input condition is adjusted to the external changes. In conjunction with the gain below the lower threshold, the programmable counter begins setting, a variable hold-off is included to compensate for the counting high speed clocks. As long as the input signal stays pipeline delay of the ADC and the switching time of the gain below the lower threshold for the number of high speed clock control element. Together, these two features provide seamless cycles programmed, the attenuator is removed on the terminal gain switching. count. However, if the input condition goes above the lower rCIC2_LOUD[4:0] and rCIC2_QUIET[4:0] threshold with the counter running, it is reset and must fall below the lower threshold again to initiate the process. This These 5-bit registers contain scale values to compensate for the prevents unnecessary switching between states. rCIC2 gain and external attenuator gain (if used). If no external attenuator is used, both the rCIC2_QUIET and rCIC2_LOUD Threshold settings for LI are illustrated in Figure 47. When the registers contain the same value. These 5-bit scale values are input signal goes above the upper threshold, the appropriate LI stored in the rCIC2 scale register (0x92) and the scaling is signal becomes active. Once the signal falls below the lower applied before the data enters the rCIC2 resampling filter. threshold, the counter begins counting. If the input condition goes above the lower threshold, the counter is reset and starts Both DDC input ports of the AD6652 have independent gain again, as shown in the figure. Once the counter has terminated control circuits, allowing each respective LI pin to be pro- to 0, the LI line goes inactive. grammed to different set points. Note that the input gain control circuits are wideband and are implemented prior to any COUNTER HIGH RESTARTS filtering elements to minimize loop delays. Any of the four UPPER THRESHOLD DDC processing channels can be set to monitor either of the SSA DWELL TIME LOWLOWER DDC input ports. TI THRESHOLD N A The chip also provides appropriate scaling of the internal data, M based on the attenuation associated with the LI signal. In this TIME 03198-0-034 tmharonungehr,o duatt ath teo pthroec DesSsP, m maakiinntga iint st oat caollryr iencdt espcaelned veanlut.e T he AD6652 includes a programmable pipeline delay that can be Figure 47. Threshold Settings for LI used to compensate for the inherent 7-clock pipeline delay The LI line can be used for a variety of functions. It can be used associated with the front-end ADC. This feature promotes to set the controls of an attenuator, DVGA, or integrated and smoother switching among gain settings. Rev. 0 | Page 32 of 76

AD6652 NUMERICALLY CONTROLLED OSCILLATOR FREQUENCY TRANSLATION TO BASEBAND The NCO can be set up to update its frequency immediately upon receipt of a HOP_SYNC or START_SYNC, with no This processing stage comprises a digital tuner consisting of hold-off count, by setting the hold-off count value to 1. Setting two multipliers, I and Q, and a 32-bit complex numerically the hold-off count to zero prevents any frequency updates. controlled oscillator (NCO). Each channel of the AD6652 has an independent NCO. The NCO serves as a quadrature local PHASE OFFSET oscillator capable of producing an NCO frequency between The phase offset register (0x87) adds a programmable offset to /2 and /2 with a resolution of CLK/232 in the complex −CLK +CLK the phase accumulator of the NCO. This 16-bit register is inter- mode. The worst-case spurious signal from the NCO is better preted as a 16-bit unsigned integer. A 0x0000 in this register than −100 dBc for all output frequencies. corresponds to no offset, and a 0xFFFF corresponds to an offset The NCO frequency programmed in Registers 0x85 and 0x86 is of 2π radians. This register allows multiple NCOs to be interpreted as a 32-bit unsigned integer. Use the following synchronized to produce outputs with constant and known equation to calculate the NCO frequency: phase differences. NCO CONTROL REGISTER NCO_FREQ=232×⎜⎛ f ⎟⎞ ⎝CLK⎠ Use the NCO control register located at 0x88 to configure the features of the NCO, which are controlled on a per channel where: basis. These features are described in the following sections. NCO_FREQ is a decimal number equal to the 32-bit binary Bypass number to be programmed at 0x85 and 0x86. To bypass the NCO of the AD6652, set Bit 0 of 0x88 high. When the NCO is bypassed, down-conversion is not performed, and f is the desired NCO output frequency in Hz. the AD6652 channel functions simply as a real filter on complex CLK is the AD6652 DDC master clock rate (in Hz). data. This feature is useful for baseband sampling applications, where the A input is connected to the I signal path within the NCO SHADOW REGISTER filter and the B input is connected to the Q signal path. Bypass- A shadow register generally precedes an active register. It holds ing the NCO might be desired, if the digitized signal has already the next number to be used by the active register whenever that been converted to baseband in prior analog stages or by other function’s hold-off counter causes the active register to be digital preprocessing. updated with the new value. Active registers are also updated Phase Dither with the contents of a shadow register any time the channel is The AD6652 provides a phase dither option for improving the brought out of sleep mode. spurious performance of the NCO. To enable phase dither, set The NCO shadow register is updated during normal program- Bit 1 of Register 0x88, which causes discrete spurs due to phase ming of the registers through the microport or serial input port. truncation in the NCO to be randomized. The energy from The active frequency register can receive update data only from these spurs is spread into the noise floor and spurious free the NCO shadow register. When software reads back an NCO’s dynamic range is increased at the expense of slight decreases in frequency, it is reading back the active frequency register and the SNR. The choice of whether to use phase dither in a system not the shadow register. depends ultimately on the system goals. If lower spurs are desired at the expense of a slightly raised noise floor, then phase NCO FREQUENCY HOLD-OFF REGISTER dither should be employed. If the lowest noise floor is desired When the NCO frequency registers are written, data is actually and higher spurs can be tolerated or filtered by subsequent passed to a shadow register. Data can be moved to the active stages, then phase dither is not needed. register by one of two methods: when the channel comes out of Amplitude Dither sleep mode or when a SYNC hop occurs. As a result of either Amplitude dither can also be used to improve spurious event, a count-down counter is loaded with an NCO frequency performance of the NCO. To enable amplitude dither, set Bit 2 hold-off value. The 16-bit unsigned integer counter (0x84) of 0x88, which causes amplitude quantization errors to be starts counting down at the DDC CLK rate and, when it reaches randomized within the angular-to-Cartesian conversion stage one, the new frequency value in the shadow register is written to of the NCO. This option reduces spurs at the expense of a the active NCO frequency register. slightly raised noise floor and slightly reduced SNR. Amplitude dither and phase dither can be used together, separately, or not at all. Rev. 0 | Page 33 of 76

AD6652 Clear Phase Accumulator on Hop Sync Pin Select When Bit 3 is logic high, the NCO phase accumulator is cleared Bits 7 and 8 of the NCO control register determine which (set to all zeros) at the beginning of the next frequency change. external sync pin (if any) is assigned to the channel of interest. This ensures a consistent phase of the NCO on each hop by The AD6652 has four sync pins: SYNCA, SYNCB, SYNCC, and defeating the phase continuous feature. The NCO phase offset is SYNCD. Any sync pin can be assigned to any or all four receiver unaffected by this setting. If phase continuous hopping is channels of the AD6652; however, a channel can have only one desired, this bit should be cleared so that the last phase in the sync pin assigned to it. The sync pin(s) must also be enabled in NCO phase register becomes the beginning phase for the new the PIN_SYNC control register at Address 4 of the external frequency. memory map. Table 13 shows the bit values used to select a specific external sync pin. Reserved Bits Table 13. Programming Channel Address Register (CAR) Bits 4 and 5 are reserved and should be written to Logic 0. Bits to Choose a Sync Pin for a Selected NCO Input Select Address/Bit 0x88:8 Address/Bit 0x88:7 Selected Sync Pin Bit 6 of the NCO control register at Address 0x88 controls input 0 0 SYNCA port selection. If this bit is set high, then Input Port B is 0 1 SYNCB connected to the selected filter channel. If this bit is cleared, 1 0 SYNCC then Input Port A is connected to the selected filter channel. 1 1 SYNCD Rev. 0 | Page 34 of 76

AD6652 SECOND-ORDER rCIC FILTER The rCIC2 filter is a second-order resampling cascaded 2 ⎛ ⎛ M × f ⎞⎞ integrator comb filter. The resampler is implemented using a ⎜sin⎜π rCIC2 ⎟⎟ unique technique, which does not require the use of a high- 1 ⎜ ⎜⎝ LrCIC2 × fSAMP ⎟⎠⎟ H(f)= × ⎜ ⎟ speed clock, thus simplifying the design and saving power. The 2SrCIC2 ×L ⎜ ⎛ f ⎞ ⎟ resampler allows for noninteger relationships between the DDC rCIC2 ⎜⎜⎝ sin⎜⎜⎝π fSAMP ⎟⎟⎠ ⎟⎟⎠ CLK and the output data rate. This allows easier implementa- tion of systems that are either multimode or require a master Use these equations along with the following filter transfer clock that is not a multiple of the data rate to be used. equations to calculate the gain and pass-band droop of the rCIC2. Excessive pass-band droop can be compensated for in Interpolation up to 512 and decimation up to 4096 is allowed in the RCF stage by peaking the pass-band by the inverse of the the rCIC2. The resampling factor for the rCIC2 (L) is a 9-bit roll-off. integer. When combined with the decimation factor M, a 12-bit number, the total rate-change can be any fraction in the form of rCIC2 SCALE FACTOR L The scale factor, SrCIC2, is a programmable unsigned 5-bit R = rCIC2 M between 0 and 31, which serves as an attenuator that can reduce R ≤1 the gain of the rCIC2 in 6 dB increments. For the best dynamic rCIC2 range, set S to the least attenuation without creating an rCIC2 The only constraint is that the ratio L/M must be less than or overflow condition. This can be safely accomplished using the equal to one. This implies that the rCIC2 decimates by 1 or following equation, where input_level is the largest fraction of more. full scale possible at the input to the AD6652 (normally 1). The S scale factor is always used whether or not the rCIC2 is rCIC2 Resampling is implemented by apparently increasing the input bypassed. sample rate by the factor L, using zero stuffing for the new data samples. Following the resampler is a second-order cascaded The S value must be less than 32 or the interpolation and rCIC2 integrator comb filter. Filter characteristics are determined only decimation rates must be adjusted to validate this equation. The by the fractional rate-change (L/M). ceil function denotes the next whole integer, and the floor function denotes the current whole integer. For example, the The filter can process signals at the full rate of the input port ceil(4.2) is 5 while the floor(4.2) is 4. When S has been rCIC2 (65 MHz). The output rate of this stage is given by the following determined for all channels, it must be programmed at 0x92 equation: [9:5] of each channel address register. The same value should also be programmed at 0x92[4:0] to accommodate a redundant L f rCIC2 SAMP f = hardware feature. SAMP2 M rCIC2 The gain and pass-band droop of the rCIC2 should be calcu- where: lated by the previous equations, as well as the rCIC2 filter transfer equations. Excessive pass-band droop can be compen- L and M are unsigned integers. rCIC2 rCIC2 sated for in the RCF stage by peaking the pass-band by the L , the interpolation rate, can be from 1 to 512. rCIC2 inverse of the roll-off. M , the decimation, can be between 1 and 4096. rCIC2 The stage can be bypassed by setting the decimation to 1/1. The ⎡ ⎛ ⎛ M ⎞ ⎞⎤ ⎢ ⎜M + floor⎜ rCIC2 ⎟× ⎟⎥ ferqeuqauteionncsy: response of the rCIC2 filter is given by the following S =ceil⎢⎢log ⎜⎜ rCIC2 ⎜⎝ LrCIC2 ⎟⎠ ⎟⎟⎥⎥ rCIC2 ⎢ 2⎜⎛ ⎛M ⎞⎞⎟⎥ ⎜⎛1−z MrCIC2 ⎟⎞2 ⎢⎢⎣ ⎜⎜⎝⎜⎜⎝2×MrCIC2−LrCIC2×floor ⎜⎜⎝ LrrCCIICC22 +1⎟⎟⎠⎟⎟⎠⎟⎟⎠⎥⎥⎦ H(z)= 1 × ⎜ LrCIC2 ⎟ 2SrCIC2 ×L ⎜ 1−z−1 ⎟ rCIC2 ⎜ ⎟ ⎜ ⎟ ⎝ ⎠ Rev. 0 | Page 35 of 76

AD6652 rCIC2 OUTPUT LEVEL consumed in subsequent stages. It should also be noted that there is more than one way to get the decimation by 4. A After the proper scaling factor has been determined, the output decimation of 4 is the same as an L/M ratio of 0.25. Thus, any level from the rCIC2 stage can be determined using the integer combination of L/M that yields 0.25 works (1/4, 2/8, or following equation: 4/16). However, for the best dynamic range, use the simplest (M 2) ratio. For example, 1/4 gives better performance than 4/16. OL = rCIC2 ×input_level rCIC2 L × 2SrCIC2 Table 14. SSB rCIC2 Alias Rejection Table (fSAMP = 1) rCIC2 Bandwidth Shown in Percentage of f SAMP where: MrCIC2/ L rCIC2 −50 dB −60 dB −70 dB −80 dB −90 dB −100 dB input_level is normally full scale (or 1) from the ADC to the 2 1.79 1.007 0.566 0.318 0.179 0.101 rCIC2 stage. 3 1.508 0.858 0.486 0.274 0.155 0.087 OL is the output level from the rCIC2 stage expressed as a 4 1.217 0.696 0.395 0.223 0.126 0.071 rCIC2 5 1.006 0.577 0.328 0.186 0.105 0.059 fraction of the input_level. OL is used later in the CIC5 rCIC2 6 0.853 0.49 0.279 0.158 0.089 0.05 stage-level calculations. 7 0.739 0.425 0.242 0.137 0.077 0.044 rCIC2 REJECTION 8 0.651 0.374 0.213 0.121 0.068 0.038 9 0.581 0.334 0.19 0.108 0.061 0.034 Table 14 illustrates the amount of bandwidth in percentage of 10 0.525 0.302 0.172 0.097 0.055 0.031 the data rate into the rCIC2 stage. The data in this table can be 11 0.478 0.275 0.157 0.089 0.05 0.028 scaled to any other allowable sample rate up to 65 MHz. The 12 0.439 0.253 0.144 0.082 0.046 0.026 table can be used as a tool to decide how to distribute the 13 0.406 0.234 0.133 0.075 0.043 0.024 decimation between rCIC2, CIC5, and the RCF. 14 0.378 0.217 0.124 0.07 0.04 0.022 15 0.353 0.203 0.116 0.066 0.037 0.021 Example Calculations: 16 0.331 0.19 0.109 0.061 0.035 0.02 Goal: Implement a filter with an input sample rate of 10 MHz, requiring 100 dB of alias rejection for a ±7 kHz pass band. DECIMATION AND INTERPOLATION REGISTERS rCIC2 decimation values are stored in Register 0x90. This 12-bit Solution: First determine the percentage of the sample rate that register contains the decimation value minus 1. The interpola- is represented by the pass band, as follows: tion portion is stored in Register 0x91. This 9-bit value holds 7kHz the interpolation value minus one. BW =100 × = 0.07 fraction 10MHz rCIC2 SCALE REGISTER Then find the −100 dB column on the right of the table and Register 0x92 contains the scaling information for the rCIC2. look down this column for a value greater than or equal to the The primary function is to store the scale value computed in the pass-band percentage of the clock rate. Then look across to the previous sections. extreme left column and find the corresponding rate change Bits 4–0 of this register should be written with the same values factor (M /L ). Referring to the table, notice that for a rCIC2 rCIC2 as those written to Bits 9–5 to accommodate a redundant M /L of 4, the frequency having −100 dB of alias rCIC2 rCIC2 internal hardware feature. rejection is 0.071%, which is slightly greater than the 0.07% calculated. Therefore, for this example, the maximum bound on Bits 9–5 (S ) contain the 5-bit scaling factor for rCIC2. rCIC2 rCIC2 rate change is 4. A higher chosen M /L means less rCIC2 rCIC2 alias rejection than the 100 dB required. Bits 11–10 are reserved and must be written low. An M /L of less than 4 would still yield the required In applications that do not require the features of the rCIC2, rCIC2 rCIC2 rejection; however, power consumption can be minimized by bypass it by setting the L/M ratio to 1/1. This effectively decimating as much as possible in this rCIC2 stage. Decimation bypasses all circuitry of the rCIC2 except the scaling, which is in rCIC2 lowers the data rate, and, therefore, reduces power still effectual. Rev. 0 | Page 36 of 76

AD6652 FIFTH-ORDER CIC FILTER The fourth signal processing stage, CIC5, implements a sharper The CIC5 stage can protect a much wider band to any given fixed-coefficient, decimating filter than rCIC2. The input rate to rejection than rCIC2. this filter is f . The maximum input rate is given by the SAMP2 Given the desired filter characteristics, Table 15 can help in the following equation. N equals two for diversity channel real CH calculation of an upper bound on decimation, M . input mode; otherwise, N equals one. To satisfy this equation, CIC5 CH increase M or reduce N . Table 15. SSB CIC5 Alias Rejection Table (f = 1) rCIC2 CH SAMP2 MCIC5 −50 dB −60 dB −70 dB −80 dB −90 dB −100 dB f f ≤ CLK 2 10.277 8.078 6.393 5.066 4.008 3.183 SAMP2 N 3 7.924 6.367 5.11 4.107 3.297 2.642 CH 4 6.213 5.022 4.057 3.271 2.636 2.121 The decimation ratio, MCIC5, can be programmed from 2 to 32 5 5.068 4.107 3.326 2.687 2.17 1.748 (all integer values). The frequency response of the filter is given 6 4.267 3.463 2.808 2.27 1.836 1.48 by the following equations. Use these equations to calculate the 7 3.68 2.989 2.425 1.962 1.588 1.281 gain and pass-band droop of CIC5. Both parameters can be 8 3.233 2.627 2.133 1.726 1.397 1.128 9 2.881 2.342 1.902 1.54 1.247 1.007 compensated for in the RCF stage. 10 2.598 2.113 1.716 1.39 1.125 0.909 1 ⎛1−z−MCIC5 ⎞5 11 2.365 1.924 1.563 1.266 1.025 0.828 H(z)= × ⎜ ⎟ 12 2.17 1.765 1.435 1.162 0.941 0.76 2SCIC5+5 ⎜⎝ 1−z−1 ⎟⎠ 13 2.005 1.631 1.326 1.074 0.87 0.703 14 1.863 1.516 1.232 0.998 0.809 0.653 ⎛ ⎛ M × f ⎞⎞5 15 1.74 1.416 1.151 0.932 0.755 0.61 ⎜sin⎜π CIC5 ⎟⎟ 16 1.632 1.328 1.079 0.874 0.708 0.572 H(f)= 1 ×⎜⎜ ⎜⎝ fSAMP2 ⎟⎠⎟⎟ 17 1.536 1.25 1.016 0.823 0.667 0.539 2SCIC5+5 ⎜ ⎛ f ⎞ ⎟ 18 1.451 1.181 0.96 0.778 0.63 0.509 ⎜ sin⎜⎜π ⎟⎟ ⎟ 19 1.375 1.119 0.91 0.737 0.597 0.483 ⎝ ⎝ fSAMP2 ⎠ ⎠ 20 1.307 1.064 0.865 0.701 0.568 0.459 21 1.245 1.013 0.824 0.667 0.541 0.437 The scale factor, S , is a programmable unsigned integer CIC5 22 1.188 0.967 0.786 0.637 0.516 0.417 between 0 and 20. It serves to control the attenuation of the data 23 1.137 0.925 0.752 0.61 0.494 0.399 into the CIC5 stage in 6 dB increments. For the best dynamic 24 1.09 0.887 0.721 0.584 0.474 0.383 range, set SCIC5 to the least attenuation without creating an 25 1.046 0.852 0.692 0.561 0.455 0.367 overflow condition. This can be safely accomplished using the 26 1.006 0.819 0.666 0.54 0.437 0.353 following equation, where OL is the largest fraction of full 27 0.969 0.789 0.641 0.52 0.421 0.34 rCIC2 scale possible at the input to this filter stage. This value is output 28 0.934 0.761 0.618 0.501 0.406 0.328 from the rCIC2 stage, then pipelined into the CIC5. 29 0.902 0.734 0.597 0.484 0.392 0.317 30 0.872 0.71 0.577 0.468 0.379 0.306 ( ( )) S =ceil log M 5 ×OL −5 31 0.844 0.687 0.559 0.453 0.367 0.297 CIC5 2 CIC5 rCIC2 32 0.818 0.666 0.541 0.439 0.355 0.287 (M 5) OL = CIC5 ×OL CIC5 2SCIC5+5 rCIC2 +10 The output rate of this stage is given by the following equation: –10 –30 f f = SAMP2 –50 SAMP5 MCIC5 dB –70 –90 CIC5 REJECTION –110 Table 15 lists the amount of bandwidth in percentage of the –130 iatnhnped uC at IlriCaast5e ri etsh j6eac5tt cMioannH sbzp ewe pchriefointce atcthtieoe dnr Csw. ITiCthh2e vd maercaiioxmuimsa tdueems cb iimyn 1pa.tu iAto srn ai ntrea ttihenset o –150 –2 MU–L1TIPLESOFC0IC5OUTPUTR1ATE 2 03198-0-035 previous rCIC2 table (Table 14), these are the single-sideband Figure 48. Double Side-Band Graph Showing CIC5 Filter Response bandwidth characteristics of the CIC5. and Alias Rejection of −100 dB Rev. 0 | Page 37 of 76

AD6652 RAM COEFFICIENT FILTER The final signal processing stage is a sum-of-products decimat- The RCF coefficients are located in addresses 0x00 to 0x7F and ing filter with programmable coefficients. A simplified block are interpreted as 20-bit twos complement numbers. When diagram is shown in Figure 49. The data memories I-RAM and writing the coefficient RAM, the lower addresses are multiplied Q-RAM store the 160 most recent complex samples from the by relatively older data from the CIC5, and the higher coeffi- previous filter stage with 20-bit resolution. The coefficient cient addresses are multiplied by relatively newer data from the memory, CMEM, stores up to 256 coefficients with 20-bit CIC5. The coefficients need not be symmetric, and the resolution. On every CLK cycle, one tap for I and one tap for Q coefficient length, N , can be even or odd. If the coefficients taps are calculated using the same coefficients. The RCF output are symmetric, then both sides of the impulse response must be consists of 24 bits of I data and 24 bits of Q data. written into the coefficient RAM. I IN 160× 20B Σ I OUT Although the base memory for coefficients is only 128 words I-RAM long, the actual length is 256 words long. There are two pages, each of 128 words long. The page is selected by Bit 8 of 0xA4. 256× 20B Although this data must be written in pages, the internal core C-RAM handles filters that exceed the length of 128 taps. Therefore, the Q IN 16Q0-R× A2M0B Σ Q OUT 03198-0-036 f(u16ll0 l etnapgtsh). o f the data RAM can be used as the filter length Figure 49. RAM Coefficient Filter Block Diagram The RCF stores the data from the CIC5 into a 160 × 40 RAM. RCF DECIMATION REGISTER 160 × 20 is assigned to I data and 160 × 20 is assigned to Q data. The RCF uses the RAM as a circular buffer, so that it is difficult Use each RCF channel to decimate the data rate. The decima- to know in which address a particular data element is stored. tion register is an 8-bit register that can decimate from 1 to 256. The RCF decimation is stored in 0xA0 in the form of M − 1. RCF When the RCF calculates a filter output, it starts by multiplying The input rate to the RCF is f . SAMP5 the oldest value in the data RAM by the first coefficient, which is pointed to by the RCF coefficient offset register (0xA3). This RCF DECIMATION PHASE value is accumulated with the products of newer data words Use the RCF decimation phase to synchronize multiple filters multiplied by the subsequent locations in the coefficient RAM within a chip. This is useful when using multiple channels until the coefficient address RCF + N − 1 is reached. OFF taps within the AD6652 to implement a polyphase filter, requiring Table 16. Three-Tap Filter that the resources of several filters be paralleled. In such an Coefficient Address Impulse Response Data application, two RCF filters would be processing the same data from the CIC5. However, each filter is delayed by one-half the 0 h(0) N(0) oldest decimation rate, thus creating a 180° phase difference between 1 h(1) N(1) the two halves. The AD6652 filter channel uses the value stored 2 = (Ntaps − 1) h(2) N(2) newest in this register to preload the RCF counter. Therefore, instead of The RCF coefficient offset register has two purposes. The main starting from 0, the counter is loaded with this value, thus purpose of this register is for rapid filter changes, by allowing creating an offset in the processing that should be equivalent to multiple filters to be loaded into memory and then selected the required processing delay. This data is stored in 0xA1 as an simply by changing the offset as a pointer. The other use of this 8-bit number. register is to form part of symbol timing adjustment. If the desired filter length is padded with zeros on the ends, then the RCF FILTER LENGTH starting point can be adjusted to form slight delays in when the The maximum number of taps this filter can calculate, N , is taps filter is computed with reference to the high speed clock. This given by the following equation. The value N − 1 is written to taps allows for vernier adjustment of the symbol timing. Course the channel register within the AD6652 at address 0xA2. adjustments can be made with the RCF decimation phase. N ≤min⎜⎛ fCLK × MRCF ,160⎟⎞ The output rate of this filter is determined by the output rate of taps ⎝⎜ fSAMP5 ⎟⎠ the CIC5 stage and MRCF, as follows: f where min indicates that Ntaps is the lesser of the two values, f = SAMP5 SAMPR separated by the comma, that appear within the brackets. MRCF Rev. 0 | Page 38 of 76

AD6652 RCF OUTPUT SCALE FACTOR AND CONTROL For an RCF scale of 0, the scaling factor is equal to −18.06 dB, REGISTER and for a maximum RCF scale of 15, the scaling factor is equal to +72.25 dB. Register 0xA4 is a compound register used to configure several aspects of the RCF register. Use Bits 3–0 to set the scale of the If Bit 7 is set, the same exponent is used for both the real and fixed-point output mode. This scale value can also be used to imaginary (I and Q) outputs. The exponent used is the one that set the floating-point outputs in conjunction with Bit 6 of this prevents numeric overflow at the expense of small signal register. accuracy. However, this is seldom a problem, because small numbers would represent 0 regardless of the exponent used. Bits 4 and 5 determine the output mode. Mode 00 sets the chip up in fixed-point mode. The number of bits is determined by Bit 8 is the RCF bank select bit used to program the register. the serial port configuration. When this bit is 0, the lowest block of 128 is selected (taps 0 to 127). When high, the highest block is selected (taps 128 to 255). Mode 01 selects floating-point mode 8 + 4. In this mode, an It should be noted that while the chip is computing filters, 8-bit mantissa is followed by a 4-bit exponent. In mode 1x (x is Tap 127 is adjacent to Tap 128 and there are no paging issues. don’t care), the mode is 12 + 4, or 12-bit mantissa and 4-bit exponent. Bit 9 selects where the input to each RCF originates. If Bit 9 is Table 17. Output Mode Formats clear, then the RCF input comes from the CIC5 normally Format Value associated with the RCF. However, if the bit is set, then the input Floating Point 12 + 4 1x comes from CIC5 Channel 1. The only exception is Channel 1, Floating Point 8 + 4 01 which uses the output of CIC5 Channel 0 as its alternate. Using Fixed Point 00 this feature, each RCF can either operate on its own channel data or be paired with the RCF of Channel 1. The RCF of Normally, the AD6652 determines the exponent value that Channel 1 can also be paired with Channel 0. This control bit is optimizes numerical accuracy. However, if Bit 6 is set, the value used with polyphase distributed filtering. stored in Bits 3–0 is used to scale the output. This ensures consistent scaling and accuracy during conditions that might If Bit 10 is clear, the AD6652 channel operates in normal mode. warrant predictable output ranges. If Bits 3–0 are represented by However, if Bit 10 is set, then the RCF is bypassed to Channel RCF scale, the scaling factor in dB is given by BIST. See the User-Configurable Built-In Self-Test (BIST) section for more details. ScalingFactor=(RCFScale − 3)× 20log (2) dB 10 Rev. 0 | Page 39 of 76

AD6652 INTERPOLATING HALF-BAND FILTERS two on the combined data from those channels. For one channel The AD6652 has two interpolating half-band FIR filters that running at twice the chip rate, the half-band can be used to immediately precede the two digital AGCs and follow the four output channel data at four times the chip rate. The frequency RCF channel outputs. Each interpolating half-band takes response of the interpolating half-band FIR is shown in 16-bit I and 16-bit Q data from the preceding RCF and outputs Figure 50. 16-bit I and 16-bit Q to the AGC. The half-band and AGC operate independently of each other, so the AGC can be SPECTRUM OF HALF-BAND 0 bypassed, in which case the output of the half-band is sent directly to the output data port. The half-band filters also –10 operate independently of each other—either one can be enabled –20 or disabled. The control register for Half-Band A is at Address F|) E 0x08 and for Half-Band B is at Address 0x09. CO–30 _ M U Half-band filters also perform the function of interleaving data R–40 T C from various RCF channel outputs prior to the actual function E P–50 S of interpolation. Interleaving of data is allowed even when the B(| half-band filter is bypassed. This allows the implementation of a d–60 polyphase filter by combining the processing power of multiple –70 channels to act upon a single carrier. This is accomplished by appropriate phasing of the processing channels using one of the –80 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 f•o lRloCwFin pgh maseet dheocdism: ation MULTIPLNiE fS3Cf OSHAIFPM CPHIP RATE ffCSHAIMPP 03198-0-037 • Start hold-off counter Figure 50. Interpolating Half-Band Frequency Response For example, if two channels of the AD6652 are used to process The SNR of the interpolating half-band is around −149.6 dB. one CDMA2000 carrier, RCF filters for both the channels The highest error spurs due to fixed-point arithmetic are should be 180° out of phase. This can be done using RCF phase around −172.9 dB. The coefficients of the 13-tap interpolating decimation or an appropriate start hold-off counter followed by half-band FIR are given in Table 18. appropriate NCO phase offsets. Table 18. Half-Band Coefficients Half-band A can listen to all four channels: Channels 0, 1, 2, and 0 14 0 −66 0 309 512 309 0 −66 0 14 0 3; Channel 0 and 1; or only Channel 0. Half-band B can listen to Channels 2 and 3, or only Channel 2. Each half-band interleaves the channels specified in its control register and interpolates by Rev. 0 | Page 40 of 76

AD6652 AUTOMATIC GAIN CONTROL Two datapaths to the AGC loop are provided: one before the The AD6652 is equipped with two independent automatic gain clipping circuitry and one after the clipping circuitry, as shown control (AGC) loops for direct interface with a Rake receiver. in Figure 51. For desired signal level mode, only the I/Q path Each AGC circuit has 96 dB of range. It is important that the before the clipping is used. For desired clipping level mode, the decimating filters of the AD6652 preceding the AGC reject difference of the I/Q signals before and after the clipping undesired signals, so that each AGC loop is operating on only circuitry is used. the carrier of interest and carriers at other frequencies do not affect the ranging of the loop. I I CLIP GAIN PROGRAMMABLE The AGC compresses the 23-bit complex output from the 23 BITS MULTIPLIER BIT WIDTH Q Q interpolating half-band filter into a programmable word size of CLIP USED ONLY FOR 4 to 8, 10, 12, or 16 bits. Because the small signals from the DESIRED – CLIPPING LEVEL lower bits are pushed into higher bits by adding gain, the MODE 2x – clipping of the lower bits does not compromise the SNR of the signal of interest. The AGC strives to maintain a constant mean output power despite input signal fluctuations. This permits MEAN SQUARE (I + jQ) operation in environments where the dynamic range of the AVERAGE 1– 16384 SAMPLES signal exceeds the dynamic range of the output resolution. DECIMATE 1– 4096 SAMPLES SQUARE ROOT The AGCs and the interpolation filters need not be linked LOG2(X) together. Either can be selected without the other. The AGC – sceocnttiroonl cwaonr db.e W byhpeans sbeydp, aisf sdeeds, itrheed ,I b/Qy sdeatttian igs Bstiitl l0 c olifp tpheed A toG aC 1– (1 + PK)×× zz––11 + P× z–2 EKPR PGROAOLINRE + R DESIRED 03198-0-038 desired number of bits, and a constant gain can be provided Figure 51. Block Diagram of the AGC through the AGC gain multiplier. Three sources of error can be introduced by the AGC function: DESIRED SIGNAL LEVEL MODE underflow, overflow, and modulation. Underflow is caused by truncation of bits below the output range. Overflow is caused by In this mode of operation, the AGC strives to maintain the clipping errors when the output signal exceeds the output range. output signal at a programmable set level. This mode of opera- Modulation error occurs when the output gain varies during the tion is selected by writing AGC control word (0x0A:4, and reception of data. 0x12:4) to Logic 0. First, the loop finds the square (or power) of the incoming complex data signal by squaring I and Q and Set the desired signal level based on the probability-density adding them. This operation is implemented in exponential function of the signal, so that the errors due to underflow and domain using 2x. overflow are balanced. Set the gain and damping values of the loop filter so that the AGC is fast enough to track long-term The AGC loop has average and decimate blocks that operate on amplitude variations of the signal that might cause excessive power samples before the square root operation, as shown in underflow or overflow, but slow enough to avoid excessive loss Figure 51. The average block can be programmed to average of amplitude information due to the modulation of the signal. 1 to 16,384 power samples, and the decimate block can be pro- grammed to update the AGC once every 1 to 4096 samples. The AGC LOOP limitations on the averaging operation are that the number of The AGC loop is implemented using a log-linear architecture. It averaged power samples must be an integer multiple of the performs four basic operations: power calculation, error calcu- decimation value, and the only allowable multiple values are lation, loop filtering, and gain multiplication. The AGC can be 1, 2, 3, or 4. configured to operate in one of the following modes: The averaging and decimation effectively mean that the AGC • Desired signal level mode can operate over averaged power of 1 to 16,384 output samples. The choice of updating the AGC once every 1 to 4096 samples • Desired clipping level mode as set by Bit 4 of AGC control and operating on average power facilitates the implementation word (0x0A, 0x12) of a loop filter with slow time constants, where the AGC error converges slowly and makes infrequent gain adjustments. It The AGC adjusts the gain of the incoming data according to would also be useful where the user wants to keep the gain how far its level is from the desired signal level or desired scaling constant over a frame of data (or a stream of symbols). clipping level, depending on the mode of operation selected. Rev. 0 | Page 41 of 76

AD6652 Because the number of average samples must be an integer Set this programmable request signal level, R, according to the multiple of the decimation value, only the multiple number 1, 2, output signal level desired. The request signal level R is 3, or 4 is programmed. This number is programmed in Output programmable from 0 to −23.99 dB in steps of 0.094 dB. The Port Control Registers 0x10:1–0 and 0x18:1–0. These averaged request signal level should also compensate for error, if any, due samples are then decimated with decimation ratios programma- to the CIC scaling, as explained previously. Therefore, the ble from 1 to 4096. This 12-bit decimation ratio is defined in request signal level is offset by the amount of error induced in Registers 0x11 and 0x19. CIC, given by The average and decimate operations are linked together and Offset=20× log (M ×N )−S × 6.02 10 CIC avg CIC implemented using a first-order CIC filter and FIFO registers. The gain and bit growth associated with CIC filters depends on where the offset is in dB. the decimation ratio. To compensate for the gain associated Continuing with the previous example, this offset is given by with these operations, attenuation scaling is provided before the CIC filter. Offset = 72.24 − 69.54 = 2.7 dB This scaling operation accounts for the division associated with So the request signal level is given by the averaging operation as well as the traditional bit growth in CIC filters. Because this scaling is implemented as a bit shift ⎡(DSL − Offset)⎤ operation, only coarse scaling is possible. Fine scaling is imple- R= ceil ⎢ ⎥ × 0.094 ⎣ 0.094 ⎦ mented as an offset in the request level, explained later in this section. The attenuation scaling, SCIC, is programmable from 0 to where: 14 using four bits of 0x10 and 0x18 of the output port control registers, and is given by R is the request signal level. DSL (desired signal level) is the output signal level that the user S =ceil[log (M × N )] desires. CIC 2 CIC avg where: Therefore, in the previous example, if the desired signal level is −13.8 dB, the request signal level, R, is programmed to be MCIC is the decimation ratio (1 to 4096). −16.54 dB. N is the number of averaged samples programmed as a avg multiple of decimation ratio (1, 2, 3, or 4). The AGC provides a programmable second-order loop filter. Ceil is MathCad-speak for rounding up to the next whole The programmable parameters, gain K and pole P, completely number. define the loop filter characteristics. The error term after subtracting the request signal level is processed by the loop For example, if a decimation ratio MCIC is 1000 and Navg is filter, G(z). The open loop poles of the second-order loop filter selected to be 3 (decimation of 1000 and averaging of 3000 are 1 and P, respectively. The loop filter parameters, pole P and samples), then the actual gain due to averaging and decimation gain K, allow adjustment of the filter time constant, which is 3000 or 69.54 dB ( = log2(3000)). Because attenuation is determines the window for calculating the peak-to-average implemented as a bit shift operation, only multiples of 6.02 dB ratio. attenuations are possible. S , in this case, is 12 corresponding CIC to 72.24 dB. This way, S scaling always attenuates more than is The open loop transfer function for the filter, including the gain CIC sufficient to compensate for the gain changes in average and parameter is as follows: decimate sections and, therefore, prevents overflows in the AGC Kz−1 loop. But it is also evident that the CIC scaling is inducing a G(z)= gain error (difference between gain due to CIC and attenuation 1−(1+P)z−1+Pz−2 provided) of up to 6.02 dB. This error should be compensated If the AGC is properly configured (in terms of offset in request for in the request signal level, as explained below. level), then there are no gains except the filter gain K. Under Logarithm to the Base 2 is applied to the output from the aver- these circumstances, a closed loop expression for the AGC loop age and decimate section. These decimated power samples (in is possible and is given by logarithmic domain) are converted to rms signal samples by G(z) Kz−1 applying a square root. This square root is implemented using a G (z)= = simple shift operation. The rms samples so obtained are sub- closed 1+G(z) 1+(K−1−P)z−1+Pz−2 tracted from the request signal level, R, specified in Registers The gain parameter K and pole P are programmable through (0x0B, 0x14), leaving an error term to be processed by the loop registers (0x0E and 0x0F, respectively, for AGC Channel A and filter, G(z). Channel B) from 0 to 0.996 in steps of 0.0039 using 8-bit Rev. 0 | Page 42 of 76

AD6652 representation. Though the user defines the open loop pole P The products of the gain multiplier are the AGC scaled outputs, and gain K, they directly impact the placement of the closed which have 19-bit representation. These are in turn used as I loop poles and filter characteristics. These closed loop poles P, and Q for calculating the power and AGC error and loop 1 P are the roots of the denominator of the above closed loop filtered to produce signal gain for the next set of samples. These 2 transfer function and are given by AGC scaled outputs can be programmed to have 4-, 5-, 6-, 7-, 8-, 10-, 12-, or 16-bit widths using the AGC control word (0x0A, (1+P−K)+ (1+P−K)2 −4P 0x12). The AGC scaled outputs are truncated to the required bit P ,P = 1 2 2 widths using the clipping circuitry shown in Figure 51. Open Loop Gain Setting Typically the AGC loop performance is defined in terms of its time constant or settling time. In such a case, set the closed loop If filter gain K occupies only one LSB or 0.0039, then, during poles to meet the time constants required by the AGC loop. The the multiplication with error term, errors of up to 6.02 dB could following relation between time constant and closed loop poles be truncated. This truncation is due to the lower bit widths can be used for this purpose: available in the AGC loop. If filter gain K is the maximum value, truncated errors are less than 0.094 dB (equivalent to 1 LSB of ⎡ M ⎤ error term representation). Generally, a small filter gain is used P = exp ⎢ CIC ⎥ 1,2 ⎢⎣samplerate × τ1,2⎥⎦ to achieve a large time constant loop (or slow loops), but, in this case, it would cause large errors to go undetected. Due to this where: peculiarity, the designers recommend that, if a user wants slow AGC loops, they should use fairly high values for filter gain K τ1,2 are the time constants corresponding to the poles P1,2. and then use CIC decimation to achieve a slow loop. In this way, exp denotes the inverse of the natural log. the AGC loop makes large infrequent gain changes compared to small frequent gain changes, as in the case of a normal small- The time constants can also be derived from settling times as gain loop filter. However, though the AGC loop makes large follows: infrequent gain changes, a slow time constant is still achieved and there is less truncation of errors. 2%settlingtime 5%settlingtime τ= or 4 3 Average Samples Setting Though it is complicated to express the exact effect of the where: number of averaging samples, thinking intuitively, it has a M (CIC decimation) is from 1 to 4096. smoothing effect on the way the AGC loop attacks a sudden CIC settling time or time constant is chosen by the user. increase or a spike in the signal level. If averaging of four sample rate is the combined sample rate of all the interleaved samples is used, the AGC attacks a sudden increase in signal channels coming into the AGC/half-band interpolated filters. level more slowly compared to no averaging. The same applies to the manner in which the AGC attacks a sudden decrease in If two channels are being used to process one carrier of UMTS the signal level. at 2× chip rate, then each channel works at 3.84 MHz and the Desired Clipping Level Mode combined sample rate coming into the half-band interpolated filters is 7.68 MSPS. Use this rate in the calculation of poles in As noted previously, each AGC can be configured so that the the previous equation, if half-band interpolating filters are loop locks onto a desired clipping level or a desired signal level. bypassed. Select desired clipping level mode by setting Bit 4 of the individual AGC control words (0x0A, 0x12). For signals that The loop filter output corresponds to the signal gain that is tend to exceed the bounds of the peak-to-average ratio, the updated by the AGC. Because all computation of the samples in desired clipping level option provides a way to keep from the loop filter is done in logarithmic domain (to the base 2), the truncating those signals and still provide an AGC that attacks signal gain is generated using the exponent (power of 2) of the quickly and settles to the desired output level. The signal path loop filter output. for this mode of operation is shown with broken arrows in Figure 51, and the operation is similar to the desired signal level The gain multiplier gives the product of the signal gain with mode. both the I and Q data entering the AGC section. This signal gain is applied as a coarse 4-bit scaling and then a fine scale First, the data from the gain multiplier is truncated to a lower 8-bit multiplier. Therefore, the applied signal gain is between resolution (4, 5, 6, 7, 8, 10, 12, or 16 bits) as set by the AGC 0 dB and 96.296 dB in steps of 0.024 dB. Initial value for signal control word. An error term (both I and Q) is generated that is gain is programmable using Register 0x0D for AGC A and the difference between the signals before and after truncation. Register 0x15 for AGC B. This term is passed to the complex squared magnitude block, Rev. 0 | Page 43 of 76

AD6652 for averaging and decimating the update samples and taking number that corresponds to the number of CLK cycles that will their square root to find rms samples, as in desired signal level be counted ( a known delay) before a new CIC decimated value mode. In place of the request desired signal level, a desired is updated. Writing a logic high to the proper pin sync pin clipping level is subtracted, leaving an error term to be proc- triggers the AGC hold-off counter with a one-shot pulse every essed by the second-order loop filter. The rest of the loop time the pin is written high. Once triggered, the counter counts operates the same way as the desired signal level mode. This down to a value of one and then causes a start of decimation for way, the truncation error is calculated and the AGC loop a new update sample. operates to maintain a constant truncation error level. Note: Setting the hold-off count to zero disables the hold-off Apart from Bit 4 of the AGC control words, the only register counter. Setting the hold-off count to one provides the smallest setting changes compared to the desired signal level mode is delay. that the desired clipping level is stored in the AGC desired level If the user chooses not to use pin sync signals, the user can use registers (0x0C, 0x15) instead of the request signal level (as in the Sync Now command through the microport. Each AGC desired signal level mode). control register has a sync now bit in Registers 0x0A:3 and SYNCHRONIZATION 0x12:3 that, when written high, performs an immediate start of decimation for a new update sample. This bit has a one-shot In instances where the AGC output is connected to a Rake characteristic and does not need to be reset in order to respond receiver, a signal from the Rake receiver can synchronize the to a new logic high being written to it. Use of the sync now bit average-and-update section of the AD6652 to update the bypasses the AGC hold-off counters and performs sync average power for AGC error calculation and loop filtering. This functions without delay. external signal synchronizes the AGC changes to the Rake receiver and makes sure that the AGC gain word does not Each Pin Sync logic high initiates a new trigger event for the change over a symbol period and, therefore, more accurate hold-off counter unless First Sync Only of the AGC’s control estimation. The external synchronization signal is connected to register (Bit 1) is set to logic high. When high, only the first sync one or more of the pin sync pins (A, B, C, or D). signal is recognized and any others disregarded until First Sync Only is reset. Pin synchronization requires the use of an AGC hold-off counter. The hold-off counter of AGC A shares the pin sync that Along with updating a new decimation value, the CIC filter the user has assigned to DDC processing Channel 0. Therefore, accumulator can be reset if the Init on Sync bit (Bit 2) of the the user must attach the external sync signal to the pin sync AGC control register is set. Init on Sync is triggered by either chosen for DDC Channel 0. Likewise, the hold-off counter of sync signal, pin sync, or sync now. AGC B shares the pin synch that the user has assigned to DDC processing Channel 2. Therefore, the user must attach the Addresses 0x0A to 0x11 have been reserved for configuring external sync signal to the pin sync that will be assigned to AGC A, and Addresses 0x12 to 0x19 have been reserved for DDC Channel 2. configuring AGC B. The register specifications are detailed in Table 29. The hold-off counter register, 0x0B and 0x13 for AGC A and AGC B, respectively, must be programmed with a 16-bit Rev. 0 | Page 44 of 76

AD6652 USER-CONFIGURABLE BUILT-IN SELF-TEST (BIST) The AD6652 includes two built-in test features to test the 2. Configure the channels to be tested as required for the integrity of each channel. The first is a RAM BIST (built-in self- application. This might require setting the NCO test), which is intended to test the integrity of the high speed parameters, the decimation rates, scalars, and RCF random access memory within the AD6652. The second is coefficients. channel BIST, which is designed to test the integrity of the main 3. Program the start hold-off counter, 0x83, to a value of 1 in signal paths of the AD6652. The BIST functions are independ- the channel address registers of the channels to be tested. ent of each other and can be operated simultaneously. RAM BIST 4. Program Channel Address Registers 0xA5 and 0xA6 to all 0s for the channels to be tested. Use the RAM BIST to validate functionality of the on-chip RAM. This feature provides a simple pass/fail test, which gives 5. Enable the channel BIST located at 0xA7 by programming confidence that the channel RAM is operational. Follow these Bits 19–0 to the number of RCF outputs to observe. steps to perform this test: 6. For External Address Register 5:3–0, program the desired 1. Put the channels to be tested into sleep mode via the SYNC CH bits to logic high to select which channels will External Address Register 0x01. receive a start soft-sync signal. 2. Program the RAM BIST enable bit in the RCF Register 7. External Address Register 5:4 should be programmed high 0xA8 of the channel address registers to logic high. Wait at to emit a one-shot soft sync pulse for the start function. least 1600 clock cycles, then perform Step 3. 8. Reset External Address Register 5:6 to 0 to allow user- 3. Read back Register 0xA8 (see Table 19). If Bit 0 is high, the provided test vectors. The internal pseudorandom number test is not yet complete. If Bit 0 is low, the test is complete generator can also be selected to generate a PN data input and Bits 1 and 2 indicate the condition of the internal sequence by setting Bit 7 high. RAM. If Bit 1 is high, then CMEM is bad. If Bit 2 is high, 9. For External Address Register 5, an internal negative full- then DMEM is bad. scale sine wave is output at the NCO frequency, when Bit 6 Table 19. BIST Register 0xA8 is set to 1 and Bit 7 is cleared. 3-Bit Data Coefficient MEM Data MEM xx1 Test incomplete Test incomplete 10. When the SOFT_SYNC control register is written with the 000 PASS PASS above parameters, the selected channels become active 010 FAIL PASS with the programmed attributes. 100 PASS FAIL 11. If the user is providing external vectors, then the chip can 110 FAIL FAIL be brought out of sleep mode by one of the other methods. 12. After a sufficient amount of time, the channel BIST CHANNEL BIST Signature Registers 0xA5 and 0xA6 contain a numeric The channel BIST is a thorough test of the selected AD6652 value that can be compared to the expected value for a signal path. With this test mode enabled, it is possible to use known good AD6652 with the exact same configuration. If externally supplied test vectors or an internal pseudonoise (PN) the values are the same, then there is a very low probability data generator. An error signature register in the RCF monitors of an error in the channel. the output data of the channel and is used to determine if the Note: To better visualize these instructions, see Figure 53, Sync proper data exits the RCF. If errors are detected, then each Control Block Diagram; Table 22, the External Memory Map; internal block can be bypassed and another test can be run to and Table 24, the Channel Address Registers Memory Map. debug the fault. The I and Q paths are tested independently. Follow these steps to perform this test: 1. Place the channel(s) to be programmed in sleep mode at External Address 3:3–0. Set the appropriate bits high. Example 3:0 = 1 places Channel 0 in sleep mode. Rev. 0 | Page 45 of 76

AD6652 CHANNEL/CHIP SYNCHRONIZATION mode by writing to the register controlling the sleep function, The AD6652 has been designed to easily synchronize two External Address 3:3–0. common functions: Start and Hop. While the AGC stage can also be synchronized, it is not accommodated using the versatile Before and after a start command is received by one or more soft-sync and pin-sync signals normally associated with channels, the following occurs: AD6652 synchronization. Start and Hop functions are described in detail in the following sections. The synchronization is 1. Just before the start command is issued, while the channel is accomplished with the use of a shadow register and a hold-off in sleep mode, any or all control registers, including filter counter. See Figure 52 for a simplified schematic of the NCO coefficients, can be safely reprogrammed without crashing shadow register and NCO frequency hold-off counter to the AD6652 or creating unwanted output. understand basic operation. Triggering of the hold-off counter 2. When a Start_Sync pulse is received, it transfers the can occur with either a Soft_Sync (via the microport), or a contents of the channel’s start hold-off register, 0x83, to the Pin_Sync (via any of the four AD6652 SYNC pins A, B, C, and counter’s preload inputs and commences counting. When D). Figure 53 details how synchronization signals are managed the count reaches a value of one, the channel is awakened for a single receive processing channel. and initialized with the information from each applicable NCO NCO register for a proper channel startup. However, if the start SHADOW FREQUENCY REGISTER REGISTER preload value is 0, this defeats the start function, and the D0 Q0 D0 Q0 channel remains dormant. Note that start does not affect the AGC hold-off counter. The FROM I0 0x85 AND 32 32 TO NCO counter can be triggered only by setting the sync now bit or by 0x86 NCO PHASE FREQUENCY ACCUMULATOR pin sync signals (see the Automatic Gain Control section). D31 Q31 D31 Q31 What happens if a Start_Sync pulse is received while the channel is awake (actively processing data)? This can actually be a very useful tool to dynamically adjust the RCF phase or NCO HOP timing to allow synchronization of multiple AD6652 ICs. Refer HOLD-OFF REGISTER COUNTER READBACK to the discussions of Registers 0x83 and 0xA1 in the Channel D0 Address Register (CAR) section for further explanation. PRELOAD FROM TC OF Start with No Sync INPUTS FROM 0x84 START HOLD-OFF COUNTER If no synchronization is needed to start multiple channels or multiple AD6652s, use the following method to initialize the D15 device: SOFT SYNC ENB TC PIN SYNC CLK 03198-0-039 1. TEox tperrongarl aAmd dar cehssa n3:n3e–l0, p),u tth ietn i nlo salede apl lm apopdreo (pbriita hteig cho, ntrol Figure 52. NCO Shadow Register and Hold-Off Counter and memory registers to set up the proper channel configuration. There are two types of synchronization stimuli to choose from: Soft_Sync and Pin_Sync. The first method is initiated over the 2. Load the start hold-off counter (0x83) with a 16-bit value microport or serial programming port using a software routine. from 1 to 216 − 1. The second method relies on an external stimulus that is attached to one of the four synchronization input pins (SYNC 3. Set the channel’s sleep bit low (External Address 3:3–0). A, B, C, and D). In both cases, a logic high triggers the synchro- Awakening from sleep involves an internally generated nization process. Both methods can be used simultaneously by start command that performs the same functions as a setting the appropriate qualifiers. software-generated sync pulse. This activates the channel after the hold-off counter reaches a value of one with the START newly programmed or previous parameters. Start refers to the startup of an individual channel or chip, or multiple chips. If a channel is not used, it should be placed in sleep mode to reduce power dissipation. Following a hard reset (low pulse on the AD6652 RESET pin), all channels are placed in sleep mode. Channels can also be manually placed in sleep Rev. 0 | Page 46 of 76

AD6652 AD6652 HARDWARE AND SOFTWARE SYNC START SYNC ENABLE, 0x82:0 AND EXT ADD 4:4 CONTROL FOR ONE PROCESSING CHANNEL SYNCA START EXT ADD 5:4 SOFT SYNC0 EXT ADD 5:0 SYNCB CHANNEL 0 START SYNC PIN SYNC_EN A* SYNCC MULTIPLEXER SYNCA PIN SYNCD TO START HOLD-OFF COUNTER PIN SYNC_EN B* 0x88:8 SELECT LINES FROM NCO SYNCB PIN 0x88:7 CONTROL REGISTER PIN SYNC_EN C* HOP SYNC ENABLE, 0x82:1 AND EXT ADD 4:5 SYNCC PIN SYNCA PIN SYNC_EN D* HOP EXT ADD 5:5 SYNCB SOFT SYNC0 EXT ADD 5:0 CHANNEL 0 HOP SYNCD PIN SYNC SYNCC MULTIPLEXER *FROM EXTERNAL MEMORY ADDRESS REGISTER 4:3-0 SYNCD TO NCO HOLD-OFF COUNTER 0x88:8 NOTE: ALL CIRCUITRY AND SIGNALS ARE IDENTICAL AND REPEATED FOR SELECT LINES EAOARTCHEH EAR CS SCHIHAGANNNNENEDLE T LEO.X AC ESPINTG SLOEF CT HSAYNNNCEx.L S AONFDT ASRYEN CNxO CT OSNHTARROELD SWIGITNHA ALSNY 0x88:7 FCROONMTR NOCLO REGISTER 03198-0-040 Figure 53. Synchronizing Signal Routing Example, Channel 0 ; Note that Multiple Qualifiers Are Required to Enable either a Pin_Sync or a Soft_Sync Signal to Be Routed to a Hop or Start Hold-Off Counter Start with Soft Sync 3. Write the start bit and the applicable channel sync bit(s) The AD6652 includes the ability to synchronize channels or high at External Address 5. This triggers the start hold-off chips using the microport. One action to synchronize is the counters to begin their count. The counters are clocked start of channels or chips. The start update hold-off counter with the AD6652 CLK signal. When it reaches a count of (0x83) in conjunction with the start bit and sync bit (External one, the sleep bits of the selected channels are set low to Address 5) allows this synchronization. The start update hold- turn on the channel with the new or existing operating off counter delays the start of a channel by the 16-bit value parameters. programmed at 0x83 (number of AD6652 CLK periods). Use Note: Each channel has a redundant soft-sync control register at the following method to synchronize the start of multiple Address 0x81. This register mimics the programming as set in channels via microprocessor control: the External Memory Address 5:5–4. The user can control the 1. Place the channels in sleep mode (a hard reset to the soft-sync function of a DDC channel by writing to the 0x81 AD6652 RESET pin forces all four DDC processing register, if it is advantageous to do so in the application. channels into sleep mode). The time from when the DTACK pin goes high (which 2. Write the start hold-off counter(s) (0x83) to a value from 1 acknowledges the receipt of the soft sync command data) to to 216 − 1. If the chip or channels have not been completely when the DDC channel begins processing data is equal to the programmed, write all other registers now. time period set up by the start hold-off counter value at 0x83 plus six CLK cycles. Rev. 0 | Page 47 of 76

AD6652 Start with Pin Sync The time from when the pin sync goes high to when the DDC The AD6652 provides four SYNC pins. A, B, C, and D, which are channel resumes processing is equal to the time period set up by used for very accurate channel synchronization. Each DDC the start hold-off counter value at 0x83 plus 3 CLK cycles. channel can be programmed to respond to any or all four sync HOP pins. Synchronization of start with one of the external sync pins is accomplished with the following method. Refer to Figure 53 Hop is a change from one NCO frequency to a new NCO to assist in following this process. frequency. This can apply to a single channel or multiple channels and can be synchronized via microprocessor control 1. Place the channels to be programmed in sleep mode. The (soft sync) or an external sync signal (pin sync), as described in AD6652 RESET pin places all four DDC processing the following sections. Awakening the channel from sleep mode channels in sleep mode when toggled low momentarily. generates an internal start command that performs both hop and start functions as if a soft-sync or pin-sync had been 2. Write the start hold-off counter(s) (0x83) to a value from 1 received. to 216 − 1. If the chip or channels have not been completely programmed, write all other registers now. Hop with Soft Sync The AD6652 includes the ability to synchronize a change in 3. Set the Start_En bit high (External Address 4:4) and choose NCO frequency of multiple channels or chips using the which Pin Sync_En bits (External Address 4:3–0) are to be microport. The NCO frequency hold-off counter (0x84) in used. Write the bit high to enable it. conjunction with the hop bit and the sync bit (External 4. Set the sync input select bits for each active channel. This is Address 4) allows this synchronization. Basically, the NCO done at Address 0x88:8–7. Table 20 is the truth table for frequency hold-off counter delays the new frequency from these bits. being loaded into the NCO by its value (number of AD6652 CLKs). Use the following method to synchronize a hop in Table 20. Truth Table frequency of multiple channels via microprocessor control: 0x88:8 0x88:7 Sync Pin Selected 0 0 A 1. Write the NCO frequency hold-off counter (0x84) to the 0 1 B appropriate value (greater than 0 and less then 216). 1 0 C 2. Write the NCO Frequency Register(s), 0x85 and 0x86, to 1 1 D the new desired frequency. After programming is complete and when the external signal attached to the selected sync pin goes high, this triggers the start 3. Write the hop bit and the applicable channel sync bit(s) hold-off counter of the chosen channel(s). The hold-off counter high at External Address 5. begins counting using the AD6652 CLK signal. When it reaches This triggers the frequency hold-off counter(s) to begin their a count of 1, the sleep bit of the selected channel(s) is set low to count. The counters are clocked with the AD6652 CLK signal. awaken the channel(s). Each Pin Sync logic high initiates a new When it reaches a count of 1, the new frequency data is trigger event for the hold-off counter unless First Sync Only, transferred from the shadow register to the working register of External Address 4:6 is set to logic high. When high, only the the NCO. Unlike the start function, the channels do not need to first sync signal is recognized and any others are disregarded be placed in sleep mode to achieve a frequency hop. until First Sync Only is reset. Note: Each channel has a redundant soft-sync control register at Note: Each channel has a redundant pin-sync control register at Address 0x81. This register mimics the programming as set in Address 0x82. This register mimics the programming as set in the External Memory Address 5:5–4. The user can control the External Memory Address 4:6–4. The user can control the pin soft-sync function of a DDC channel by writing to the 0x81 sync function of a DDC channel by writing to Registers 0x82 register, if it is advantageous to do so in the application. and 0x88:8–7, if it is advantageous to do so in the application. The time from when the DTACK pin goes high (which acknowledges the receipt of the soft sync command data) to when the DDC channel begins processing data is equal to the time period set up by the frequency or hop hold-off counter value at 0x84 plus 7 CLK cycles. Rev. 0 | Page 48 of 76

AD6652 Hop with Pin Sync When the selected sync pin is sampled high by the AD6652 Just as in the start function, the AD6652 provides four SYNC CLK, this enables the count-down of the NCO frequency pins, A, B, C, and D, which are used for very accurate channel hold-off counter. The counter is clocked with the AD6652 CLK synchronization. Each DDC channel can be programmed to signal. When it reaches a count of 1, the new frequency is respond to any or all four SYNC pins. loaded into the NCO. Each Pin Sync logic high initiates a new trigger event for the hold-off counter unless First Sync Only, Synchronization of hop with one of the external SYNC pins is External Address 4:6 is set to logic high. When high, only the described as follows: first sync signal is recognized and any others are disregarded 1. Write the NCO frequency hold-off counter(s) (0x84) to the until First Sync Only is reset. Unlike the start function, the appropriate value (greater than 0 and less than 216). channels do not need to be placed in sleep mode to achieve a frequency hop. 2. Write the NCO Frequency Register(s), 0x85 and 0x86, to Note: Each channel has a redundant pin-sync control register at the new desired frequency. Address 0x82. This register mimics the programming as set in 3. Set the hop on pin sync bit high and the appropriate sync External Memory Address 4:6–4. The user can control the pin pin enable high at External Address 4. sync function of a DDC channel by writing to the 0x82 and 0x88:8–7 registers, if it is advantageous to do so in the 4. Set the sync input select bits for each active channel. This is application. done at Address 0x88:8–7. The truth table for these bits is the same as for the start with pin sync, in Table 20. The time from when the external signal on the SYNC input pin goes high to when the NCO begins processing data is equal to the time period set up by the NCO frequency hold-off counter (0x84) plus five master clock cycles. Rev. 0 | Page 49 of 76

AD6652 PARALLEL OUTPUT PORTS The AD6652 incorporates two independent 16-bit parallel ports • Interpolated, interleaved, and/or AGC modified Channel B for output data transfer. To minimize package ball count, the data eight LSBs of each 16-bit port are shared with their respective Any of the six sources can be output on any port(s). A port can DSP link port data bits (see Figure 54). This means that an be configured to output parallel data or DSP link data. Output output port can transmit 16-bit parallel data or 8-bit link port port control registers (Table 29) perform these multiplexing and data, but not both. Transmitting both link and parallel data selection tasks. simultaneously requires that the second AD6652 output port be configured for that purpose. Parallel port configuration is specified by accessing Port Control Register Addresses 0x1A and 0x1C for Parallel Ports A R T A LLIINNKK PPOORRTT AA CCLLOOCCKK OINUT athned M B,a rsetespr/eScltaivvee lPy.C PLoKrt Mcloocdke sm saesctteior/ns)l aivs ec omnofidgeu (rdedes ucrsiibnegd t hine O LINK PORT A DATA OR 8 LSB'S port clock control register at Address 0x1E. Note that to access 2 P (OSFH PAARREADL PLIENLS )PORT A DATA /8 these registers, Bit 5 (access port control registers) of External 5 Address 3 (sleep register) must be set. The address is then 6 6 PCLK selected by programming the CAR register at External D Address 6. A PARALLEL PORT A MSB DATA / 8 The parallel ports are enabled by setting Bit 7 of the link control PARALLEL PORT A ACK registers at Addresses 0x1B and 0x1D for Ports A and B, PARALLEL PORT A REQ respectively. Each parallel port is capable of operating in either PARALLEL PORT A / CHANNEL INDICATOR 2 channel mode or AGC mode. These modes are described in PARALLEL PORT A detail in the following sections. I AND Q INDICATOR CHANNEL MODE Parallel port channel mode is selected by setting Bit 0 of Addresses 0x1B and 0x1D for Parallel Ports A and B, respec- tively. In channel mode, I and Q words from each channel are B LINK PORT B CLOCK OUT T LINK PORT B CLOCK IN directed to the parallel port, bypassing the AGC. The specific R channels output by the port are selected by setting Bits 1–4 of O LINK PORT B DATA OR 8 LSB'S Parallel Port Control Register 0x1A (Port A) and 0x1C (Port B). P OF PARALLEL PORT B DATA / 2 (SHARED PINS) 8 Channel mode provides two data formats. Each format requires 5 6 a different number of parallel port clock (PCLK) cycles to 6 PCLK D complete the transfer of data. In each case, each data element is A PARALLEL PORT B MSB DATA / transferred during one PCLK cycle. See Figure 55 and Figure 56, 8 which present channel mode parallel port timing. PARALLEL PORT B ACK PARALLEL PORT B REQ The 16-bit interleaved format provides I and Q data for each PARALLEL PORT B / output sample on back-to-back PCLK cycles. Both I and Q CHANNEL INDICATOR 2 PI AANRDA LQL EINLD PICOARTTO BR 03198-0-041 wtroigrgdesr ceodn osnis tt hoef rthisein fgu lel dpgoer to fw PidCthL Ko fw 1h6e bni tbso. Dtha RtaE oQu tapnudt AisC K are asserted. I data is output during the first PCLK cycle; the Figure 54. Output Port Configuration PAIQ and PBIQ output indicator pins are set high to indicate Each parallel output port has six data sources routed to it (see that I data is on the bus. Q data is output during the subsequent the Functional Block Diagram in Figure 1): PCLK cycle; the PAIQ and PBIQ output indicator pins are low during this cycle. • Noninterpolated RAM coefficient FIR filter output data from Channels 1, 2, 3, and 4 • Interpolated, interleaved, and/or AGC modified Channel A data Rev. 0 | Page 50 of 76

AD6652 AGC MODE PCLKn Parallel port channel mode is selected by clearing Bit 0 of Addresses 0x1A and 0x1C for Parallel Ports A and B, respec- PxACK tively. I and Q data output in AGC mode are output from the t AGC, not the individual channels. AGC A accepts data from PxREQ DPREQ Channel 0 to Channel 3, while AGC B accepts data from tDPP Channel 2 and Channel 3. Each pair of channels is required to Px[15:0] I[15:0] Q[15:0] be configured such that the generation of output samples from the channels is out of phase (by typically 180°). Each parallel tDPIQ port can provide data from either one or both AGCs. Bit 1 and PxIQ tDPCH Bit 2 of Register Addresses 0x1A (Port A) and 0x1C (Port B) control the inclusion of data from AGCs A and B, respectively. PxCH[1:0] PCxhCaHn[n1e:0l ]# = 03198-0-042 AGC mode provides only one I&Q format, which is similar to the 16-bit interleaved format of channel mode. When both REQ Figure 55. Channel Mode Interleaved Format and ACK are asserted, the next rising edge of PCLK triggers the The 8-bit concurrent format provides 8 bits of I data and 8 bits output of a 16-bit AGC I word for one PCLK cycle. The PAIQ of Q data simultaneously during one PCLK cycle, also triggered and PBIQ output indicator pins are high during this cycle, and on the rising edge of PCLK. The I byte occupies the most are low otherwise. A 16-bit AGC Q word is provided during the significant byte of the port, while the Q byte occupies the least subsequent PCLK cycle. If the AGC gain word has been updated significant byte. The PAIQ and PBIQ output indicator pins are since the last sample, a 12-bit RSSI word is provided during the set high during the PCLK cycle. Note that if data from multiple PCLK cycle following the Q word of 12 MSBs of the parallel channels is output consecutively, the PAIQ and PBIQ output port data pins. This RSSI word is the bit-inverse of the signal indicator pins remain high until data from all channels has been gain word used in the gain multiplier of the AGC. output. The data provided by the PACH[1:0] and PBCH[1:0] pins in PCLKn AGC mode is different than that provided in channel mode. In AGC mode, PACH[0] and PBCH[0] indicate the AGC source of the data currently being output (0 = AGC A, 1 = AGC B). PxACK tDPREQ PACH[1] and PBCH[1] indicate whether the current data is an I/Q word or an AGC RSSI word (0 = I/Q word, 1 = AGC RSSI PxREQ word). The two different AGC outputs are shown in Figure 57 tDPP and Figure 58. I[15:8] Px[15:0] Q[7:0] tDPIQ PCLKn PxIQ PxCH[1:0] tDPPCCxHhCaHn[n1:e0l ]# = 03198-0-043 PPxxRAECQK tDPREQ Figure 56. Channel Mode 8I/8Q Parallel Format tDPP The PACH[1:0] and PBCH[1:0] pins provide a 2-bit binary Px[15:0] I[15:0] Q[15:0] value indicating the source channel of the data currently being tDPIQ output. PxIQ tDPCH Care should be taken to read data from the port as soon as pnoewss idbaleta. Isfa nmopt,l eth aer rsiavmesp. lTe hwisil ol bcceu orvse ornw ari tpteern- cwhhaennn ethl eb anseisx;t PxCH[1:0] PxCPHx[C0H] =[1 A] =G C0 # 03198-0-044 that is, a Channel 0 sample is overwritten only by a new Figure 57. AGC with No RSSI Word Channel 0 sample, and so on. The order of data output is dependent on when data arrived at the port, which is a function of total decimation rate, start hold- off values, and so on. Priority order is, from highest to lowest, Channels 0, 1, 2, and 3. Rev. 0 | Page 51 of 76

AD6652 PCLKn PARALLEL PORT PIN FUNCTIONS PCLK Input/output. As an output (master mode), the maximum PxACK tDPREQ frequency is CLK/n, where CLK is the AD6652 clock and n is an integer divisor 1, 2, 4 or 8. As an input (slave mode), it might be PxREQ asynchronous relative to the AD6652 CLK. This pin powers up tDPP as an input to avoid possible contentions. Other port outputs Px[15:0] I[15:0] Q[15:0] RSSI[11:0] change on the rising edge of PCLK. tDPIQ REQ PxIQ tDPCH Active high output, synchronous to PCLK. A logic high on this pin indicates that data is available to be shifted out of the port. PxCH[1:0] PxPCxHC[H0][ 1=] A= G0C # PxCPHx[C0H] =[1 A] G= C1 # 03198-0-045 Ash ilfotgeidc ohuigt.h value remains high until all pending data has been Figure 58. AGC with RSSI Word PxACK MASTER/SLAVE PCLK MODES Active high asynchronous input. Applying a logic low on this The parallel ports operate in either master or slave mode. The pin inhibits parallel port data shifting. Applying a logic high to mode is set via the port clock control register (Address 0x1E). this pin when REQ is high causes the parallel port to shift out The parallel ports power up in slave mode to avoid possible data according to the programmed data mode. PxACK is contentions on the PCLK pin. sampled on the falling edge of PCLK. Data is shifted out on the next rising edge of PCLK after PxACK is sampled. PxACK can In master mode, PCLK is an output whose frequency is the be held high continuously. In this case, when data becomes AD6652 clock frequency divided by the PCLK divisor. Because available, shifting begins 1 PCLK cycle after the assertion of values for PCLK_divisor[2:1] can range from 0 to 3, integer REQ (see Figure 55 to Figure 58). divisors of 1, 2, 4,or 8, respectively, can be obtained. Because the maximum clock rate of the AD6652 is 65 MHz, the highest PAIQ, PBIQ PLCK rate in master mode is also 65 MHz. Master mode is High whenever I data is present on the port output, otherwise selected by setting Bit 0 of Address 0x1E. low. In slave mode, external circuitry provides the PCLK signal. PACH[1:0], PBCH[1:0] Slave-mode PCLK signals can be either synchronous or These pins serve to identify data in both data modes. In channel asynchronous. The maximum slave-mode PCLK frequency is mode, these pins form a 2-bit binary number identifying the 100 MHz. source channel of the current data word. In AGC mode, [0] indicates the AGC source (0 = AGC A, 1 = AGC B), and [1] indicates whether the current data word is I/Q data (0) or a gain word (1). PA[15:0], PB[15:0] Parallel output data ports. Contents and format are mode- dependent. Rev. 0 | Page 52 of 76

AD6652 LINK PORT The AD6652 has two configurable link ports that provide a Note that Bit 0 = 1, Bit 1 = 0, and Bit 2 = 1 is not a valid seamless data interface with the TigerSHARC TS-101 series configuration. Bit 2 must be set to 0, to output AGC A IQ and DSP. Each link port allows the AD6652 to write output data to RSSI words on Link Port A and AGC B IQ and RSSI words on the receive DMA channel in the TigerSHARC for transfer to Link Port B. memory. Because they operate independently of each other, each link port can be connected to a different TigerSHARC or LINK PORT AGC A I, Q AGC B I, Q AGC A I, Q AGC B I, Q A OR B (4 BYTES) (4 BYTES) (4 BYTES) (4 BYTES) different link ports on the same TigerSHARC. Figure 59 shows ADDR 0x1B OR 0x1D BIT 0 = 1, BIT 1 = 0, BIT 2 = 0 how to connect one of the two AD6652 link ports to one of the LINK PORT AGC A I, Q AGC A RSSI AGC B I, Q AGC B RSSI four TigerSHARC link ports. Link Port A is configured through A OR B (4 BYTES) (4 BYTES) (4 BYTES) (4 BYTES) ADDR 0x1B OR 0x1D BIT 0 = 1, BIT 1 = 0, BIT 2 = 1 Register 0x1B and Link Port B is configured through AGC A I, Q AGC A RSSI AGC A I, Q AGC A RSSI Register 0x1D. LINK PORT A (4 BYTES) (4 BYTES) (4 BYTES) (4 BYTES) AD6L6C5L2KIN LTCigLKeIrNSHARC LINK PORT B A(4G BCY BTA EI,DS Q)DR 0xA1(BG4 CAB NYBTD RE 0SSxS)1ID BITA( 04G =BC Y1 BT, B EI,SI TQ) 1 = 1A, (BG4I CTB Y2BT =RE 0SSS)I 03198-0-048 LCLKOUT LCLKOUT Figure 61. Link Port Data from AGC PLCDLAKT 8 LDPCALTK 03198-0-046 LINK PORT TIMING Both link ports run off of PCLK, which can be externally Figure 59. Link Port Connection between AD6652 and TigerSHARC provided to the chip (Address 0x1E Bit 0 = 0) or generated from the master clock of the AD6652 (Address 0x1E Bit 0 = 1). This LINK PORT DATA FORMAT register boots to 0 (slave mode) and allows the user to control the data rate coming from the AD6652. PCLK can be run as fast Each link port can output data to the TigerSHARC in five as 100 MHz in slave mode. different formats: 2-channel, 4-channel, dedicated AGC, redundant AGC with receive signal strength indicator (RSSI) The link port provides 1-byte data words (LA[7:0], LB[7:0] word, and redundant AGC without RSSI word. Each format pins) and output clocks (LACLKOUT, LBCLKOUT pins) in outputs two bytes of I data and two bytes of Q data to form a response to a ready signal (LACLKIN, LBCLKIN pins) from the 4-byte IQ pair. Because the TigerSHARC link port transfers data receiver. Each link port transmits 8 bits on each edge of in quad-word (16-byte) blocks, four IQ pairs can make up one LCLKOUT, requiring 8 LCLKOUT cycles to complete quad-word. If the channel data is selected (Bit 0 = 0 of 0x1B/ transmission of the full 16 bytes of a TigerSHARC quad-word. 0x1D), then 4-byte IQ words of the four channels can be output in succession, or alternating channel pair IQ words can be Due to the TigerSHARC link port protocol, the AD6652 must output. Figure 60 and Figure 61 show the quad-word trans- wait at least 6 PCLK cycles after the TigerSHARC is ready to mitted for each case with corresponding register values for receive data, as indicated by the TigerSHARC setting the configuring each link port. respective AD6652 LCLKIN pin high. Once the AD6652 link port has waited the appropriate number of PCLK cycles and has LINK PORT CH 0 I, Q CH 1 I, Q CH 2 I, Q CH 3 I, Q A OR B (4 BYTES) (4 BYTES) (4 BYTES) (4 BYTES) begun transmitting data, the TigerSHARC does a connectivity ADDR 0x1B OR 0x1D BIT 0 = 0, BIT 1 = 0 check by sending the AD6652 LCLKIN low and then high while LINK PORT A CH 0 I, Q CH 1 I, Q CH 0 I, Q CH 1 I, Q the data is being transmitted. This tells the AD6652 link port (4 BYTES) (4 BYTES) (4 BYTES) (4 BYTES) that the TigerSHARC’s DMA is ready to receive the next quad- LINK PORT B (4C HB Y2T IE, QS) ADDR(4C 0 HBx 1Y3BT I E,A QSN)D 0x1D(4C B HBIT Y2 T0 I E,= QS 0), BIT 1( =4C H1B Y3T IE, QS) 03198-0-047 wcoonrnde acfttievri tcyo cmhpeclekt iios nd oonf eth ien cpuarrraelnletl qtou atdh-ew doartda . tBraencsamusies stihoen , the AD6652 can stream uninterrupted data to the TigerSHARC. Figure 60. Link Port Data from RCF If AGC output is selected (Bit 0 = 1), then RSSI information can LCLKIN TigerSHARC READY TO TigerSHARC READY TO RECEIVE QUAD-WORD RECEIVE NEXT QUAD-WORD be sent with the IQ pair from each AGC. Each link port can be configured to output data from one AGC, or both link ports can LCLKOUT WAIT≥ 6 CYCLES output data from the same AGC. If both link ports are transmit- tIiQn gw tohred ssa (mBiet d2a =ta 0, )th. Neno tReS tShIa itn tfhoer macatutiaoln R mSSuIs tw boer dse ins to wnliyth the LDAT[7:0] D0 D1 D2 D3 D4 DN1E5XTD 0QUDA1D-DW2ORD03198-0-049 two bytes (12 bits appended with 4 0s), so the link port sends Figure 62. Link Port Data Transfer two bytes of 0s immediately after each RSSI word to make a full 16-byte quad-word. Rev. 0 | Page 53 of 76

AD6652 The length of the wait before data transmission is a 4-bit TIGERSHARC CONFIGURATION programmable value in the link port control registers (0x1B and Because the AD6652 is always the transmitter in this link and 0x1D Bits 6–3). This value allows the AD6652 PCLK and the the TigerSHARC is always the receiver, the following values can TigerSHARC PCLK to be run at different rates and out of be programmed into the LCTL register for the link port used to phase. receive AD6652 output data. ⎛ f ⎞ Table 21. TigerSHARC LCTLx Register Configuration WAIT≥ciel ⎜6 × LCLK_AD6652 ⎟ ⎜ f ⎟ Register Value ⎝ LCLK_TSHARC ⎠ VERE 0 WAIT ensures that the amount of time the AD6652 needs to SPD User1 wait to begin data transmission is at least equal to the minimum LTEN 0 amount of time the TigerSHARC is expecting it to wait. If the PSIZE 1 PCLK of the AD6652 is out of phase with the PCLK of the TTOE 0 TigerSHARC and the argument to the ceil() function is an CERE 0 integer, then WAIT must be strictly greater than the value given LREN 1 in the above formula. RTOE 1 If the LCLKs are in phase, then the maximum output data rate is 1 The term User means that the actual register value depends on the user’s 15 application. f ≤ × f LCLK_AD6652 LCLK_TSHARC 6 Otherwise, it is 14 f ≤ × f LCLK_AD6652 LCLK_TSHARC 6 Rev. 0 | Page 54 of 76

AD6652 EXTERNAL MEMORY MAP The use of each of these individual registers is described in The external memory map is the only way to gain access to the detail in the following sections. It should be noted that the serial four channel address register pages and the output port control control interface has the same memory map as the microport register page. This set of eight registers is shown in Table 22. interface and can carry out exactly the same functions, although These registers are collectively referred to as the external at a slower rate. memory map registers, because they control all accesses to the channel address space as well as output control registers. Table 22. External Memory Map Address Name Comment 7 Access Control Register (ACR) 7: Auto increment 6: Broadcast 5–2: Instruction[3:0] 1–0: A[9:8] 6 Channel Address Registers (CAR) 7–0: A[7:0] 5 SOFT_SYNC Control Register (Write Only) 7: PN_EN 6: Test_MUX_Select 5: Hop 4: Start 3: SYNC CH3 2: SYNC CH2 1: SYNC CH1 0: SYNC CH0 4 PIN_SYNC Control Register (Write Only) 7: Reserved write to logic low 6: First SYNC only 5: Hop_En 4: Start_En 3: PIN SYNC_EN D 2: PIN SYNC_EN C 1: PIN SYNC_EN B 0: PIN SYNC_EN A 3 SLEEP (Write Only) 7–6: Reserved write to logic low 5: Access output port control registers 4: Reserved low 3: SLEEP CH3 2: SLEEP CH2 1: SLEEP CH1 0: SLEEP CH 0 2 Data Register 2 (DR2) 7–4: Reserved 3–0: D[19:16] 1 Data Register 1 (DR1) 15–8: D[15:8] 0 Data Register 0 (DR0) 7–0: D[7:0] Rev. 0 | Page 55 of 76

AD6652 ACCESS CONTROL REGISTER (ACR) CHANNEL ADDRESS REGISTER (CAR) External Address 7 External Address 6 The ACR specifies certain programming characteristics such as The user writes the 8-bit internal address of a channel register autoincrement or broadcast, which are to be applied to the to be programmed in the CAR. If the autoincrement bit of the incoming instructions, and selects which channel(s) are to be ACR is 1, then this value is incremented after every access to the programmed by the microport or serial port. DR0 register, which in turn accesses the location pointed to by this address. The channel address register cannot be read back Bit 7 of this register is the autoincrement bit. If this bit is a 1, while the broadcast bit is set high. then the CAR register, described in the Channel Address SOFT_SYNC CONTROL REGISTER Register (CAR) section, increments its value after every access External Address 5 to the channel. This allows blocks of address space such as coefficient memory to be initialized more efficiently. The SOFT_SYNC control register is write only. The register name is somewhat deceiving in that this register also contains Bit 6 of the register is the broadcast bit, which determines how BIST (built-in self-test) commands that turn internal test Bits 5–2 are interpreted. If broadcast is 0 then Bits 5–2, which signals off or on, namely, pseudonoise and negative full-scale are referred to as instruction bits (Instruction[3:0]), are sine wave, at Bits 7 and 6, explained below. compared with the CHIP_ID[3:0] pins. The instruction that matches the CHIP_ID[3:0] pins determines the access. This Bits 0–3 of this register are the SOFT_SYNC channel enable bits allows up to 16 chips to be connected to the same port and for each of the four DDC channels. Writing a logic high to one memory mapped without external logic. This also allows the or all of these bits simply selects the indicated channel(s) to be same serial port of a host processor to configure up to 16 chips. recipients of a soft_sync synchronizing pulse—whenever such signal is generated by Bits 4 and 5 of this register as described If the broadcast bit is high, the Instruction[3:0] word allows below. A pin-sync signal can be used in addition to a soft-sync multiple AD6652 channels and/or chips to be configured signal, if desired. simultaneously independent of the CHIP_ID[3:0] pins. The 10 possible instructions are defined in Table 23. This is useful Bit 4 is the start software synchronizing pulse. Writing this bit to for smart antenna systems, where multiple channels listening to logic high initiates a one-shot-type pulse to trigger the start a single antenna or carrier can be configured simultaneously. hold-off counter of the selected DDC channels according to The x’s in the comment portion of the table represent “don’t Bits 3–0 above. See the Channel/Chip Synchronization section cares” in the digital decoding. When broadcast is enabled (Bit 6 for further information. Programming this bit also programs set high) readback is not valid because of the potential for Channel Address Register 0x82 of each channel. internal bus contention. Therefore, if readback is subsequently Bit 5 is the hop software synchronizing pulse. Writing this bit to desired, the broadcast bit should be set low. logic high initiates a one-shot-type pulse to trigger the hop Bits 1–0 of the ACR are address bits that decode which of the frequency hold-off counter of the selected DDC channels four channels are being accessed. If the instruction bits decode according to Bits 3–0 above. See the Channel/Chip an access to multiple channels, then these bits are ignored. If the Synchronization section. Programming this bit also programs instruction decodes an access to a subset of chips, then the the Channel Address Register 0x82 of each channel. A[9:8] bits otherwise determine the channel being accessed. Bit 6 configures how the internal input data bus is configured. If Table 23. Microport Instructions, 7:5–2 this bit is low, then the ADCs (analog–to-digital converters) are Instruction Comment connected to the DDC NCOs according to the user’s choice— 0000 All chips and all channels have access. this is normal operation. If this bit is logic high, then the 0001 Channels 0, 1, 2 of all chips have access. internal test signals are connected to all DDC NCOs for BIST 0010 Channels 1, 2, 3 of all chips have access. purposes and this overrides any NCO programmed input 0100 All chips get the access.1 choice. The internal test signals are configured in Bit 7 of this 1000 All chips with Chip_ID[3:0] = xxx0 have access.1 register. 1001 All chips with Chip_ID[3:0] = xxx1 have access.1 1100 All chips with Chip_ID[3:0] = xx00 have access.1 If Bit 7 is logic low, a negative full-scale signal is generated and 1101 All chips with Chip_ID[3:0] = xx01 have access.1 made available to the internal data bus. If this bit is high, then 1110 All chips with Chip_ID[3:0] = xx10 have access.1 the internal pseudorandom noise generator is enabled and this 1111 All chips with Chip_ID[3:0] = xx11 have access.1 data is available to the internal input data bus. The combined functions of Bits 6 and 7 facilitate BIST functions. Also, in conjunction with the MISR registers, this allows for detailed 1 A[9:8] bits control which channel is decoded for access. in-system chip testing. Rev. 0 | Page 56 of 76

AD6652 PIN_SYNC CONTROL REGISTER Bit 5 allows access to the output control port registers. When External Address 4 this bit is low, the channel address registers are accessed. However, when this bit is set high, it allows access to the output This is the write-only PIN_SYNC control register. port control registers. When this bit is set high, the value in Bits 3–0 of this register are the PIN SYNC_EN control bits. External Address 6 (CAR) points to the memory map for the These bits can be written to by the controller to select any or all output control port registers instead of the normal channel of the external pin sync inputs: A, B, C, and/or D. One pin can address register memory map. See Table 29 in the Output Port be assigned to all channels, one pin can be assigned to one Control Registers section. channel, or any combination in between. This register is fully Bit 6–7 are reserved and should be written low. configurable at the channel level (in the channel address register memory map, 0x88) as to which pin-sync signal is selected. A DATA ADDRESS REGISTERS pin-sync signal can be used in addition to a soft-sync signal, if External Address 2–0 desired. See Figure 53. These registers form the data registers DR2, DR1, and DR0, respectively. All internal data-words have widths that are equal Bit 4 is the start enable bit. Writing this bit to logic high enables to or less than 20 bits. When External Address 0 is written to, it or facilitates the routing of the external pin-sync signal to all the triggers an internal access to the AD6652 based on the address DDC channels. This bit enables any pin-sync signals that were indicated in the ACR and CAR. Thus, during writes to the selected by Bits 3–0 above, to be routed to a 4-to-1 multiplexer internal registers, External Address [0] DR0 must be written and ultimately chosen to be the channel’s pin-sync signal that last. At this point, data is transferred to the internal memory controls the start function. See Figure 53. Programming this bit indicated in A[9:0]. Reads are performed in the opposite also programs the Channel Address Register 0x82 of each direction. Once the address is set, External Address [0] DR0 channel. must be the first data register read to initiate an internal access. Bit 5 is the hop enable bit. Writing this bit to logic high enables DR2 is only 4 bits wide. Data written to the upper 4 bits of this or facilitates the routing of the external pin-sync signal to all the register are ignored. Likewise, reading from this register DDC channels. This bit enables any pin-sync signals that were produces only 4 LSBs. selected by Bits 3–0 above to be routed to a 4-to-1 multiplexer Figure 63 is a block diagram of the memory structure. and ultimately chosen to be the channel’s pin-sync signal that controls the Hop function. See Figure 53. Programming this bit CHANNEL ADDRESS REGISTERS (CAR) also programs the Channel Address Register 0x82 of each 0x00–0x7F: Coefficient Memory (CMEM) channel. This register is the coefficient memory (CMEM) used by the Bit 6 is used to ignore repetitive synchronization signals. If this RCF. It is memory mapped as 128 words by 20 bits. A second bit is clear, each PIN_SYNC restarts or frequency hops the 128 words of RAM can be accessed via this same location by channel. If this bit is set, then only the first occurrence causes writing Bit 8 of the RCF control register high at Channel the action to occur. Programming this bit also programs the Address 0xA4. The filter calculated always uses the same Channel Address Register 0x82 of each channel. coefficients for I and Q. By using memory from both of these 128 blocks, a filter of up to 160 taps can be calculated. Multiple Bit 7 is reserved; the bits should be written to Logic 0. filters can be loaded and selected with a single internal access to the coefficient offset register at Channel Address 0xA3. SLEEP CONTROL REGISTER External Address 3 0x80: Channel Sleep Register In addition to sleep mode control, this register also provides This register contains the sleep bit for the channel. It mimics the access to the output port control register’s memory map. programming of Bits 0–3 at External Address 3. External Address 3 provides simultaneous sleep mode control for all four Bits 3–0 control the sleep mode of the indicated channel. If the DDC channels. The user can overwrite the data in 0x80, if bit is low, the channel operates normally. If the bit is high, the desired. Sleep mode is selected when this bit is written logic indicated channel enters a low-power sleep mode. Program- high. ming this bit also programs the Channel Address Register 0x82 of each channel. Bit 4 is reserved and should be written to Logic 0. Rev. 0 | Page 57 of 76

AD6652 0x00 CAR, EXTERNAL CHANNEL 0 ADDRESS 6 INPUT PORT MEMORY MAP CONTROL REGISTERS A[9:8] FROM BITS [1:0] OF 8 ACR, EXTERNAL CHANNEL CHANNEL 1 DECODER* MEMORY MAP ADDRESS 7 S1 D1 ADDRESS BUS 0x08 TO 2 S2 D4 ENB CHANNEL 2 DATA BUS OUTPUT PORT MEMORY MAP CONTROL REGISTERS 20 CHANNEL 3 MEMORY MAP 0x1E DR2, DR1, DR0, EXTERNAL ENB ADDRESSES 2, 1, 0 * COHVAENRNREIDLD DEENC BOYD EBRR OCAADNC BAEST FEATURE. AREXCETGCEEISRSTNSEA RTLOS A, OBDUIDTTR P5E,U SSTSL C E3OEPN TRREOGLISTER, 03198-0-050 Figure 63. Block Diagram of the AD6652 Internal Memory Maps and Controls 0x81: Soft_SYNC Register be overwritten to change the programming of a particular channel. If this bit is clear, each PIN_SYNC restarts or rehops This register is used to initiate software-generated SYNC events the channel. If this bit is set, then only the first sync pulse causes through the microport. It mimics the programming of Bits 4 the action to occur. and 5 at External Address 5. If the hop bit is written high, then the hop hold-off counter at Address 0x84 is loaded and begins 0x83: Start Hold-Off Counter to count down. When the count reaches a value of 1, the The start hold-off counter is loaded with the 16-bit value channel’s NCO frequency accumulator is loaded with the data written to this address. When the Start function is triggered by from Channel Addresses 0x85 and 0x86. When the start bit is either a Soft_SYNC or Pin_SYNC, the hold-off counter begins written high, the start hold-off counter is loaded with the value decrementing. When the count reaches a value of one, the at Address 0x83 and begins to count down. When the count channel is brought out of sleep mode and begins processing reaches a value of 1, the sleep bit in Address 0x80 is written low data. If the channel is already running, the phase of the filter(s) is and the channel is started. adjusted such that multiple AD6652s can be synchronized. 0x82: Pin_SYNC Register A periodic pulse on the SYNC pin can be used in this way to This register mimics Bits 4, 5, and 6 of External Memory Map adjust the timing of the filters with the resolution of the ADC Address 4. Because the programming at External Memory sample clock. See the 0xA1 register description for further Address 4 applies to all four channels, the user can customize a information about filter phase adjustment. If this register is particular channel by overwriting the data in 0x82.If the initial written to Logic 1, then the start occurs immediately after the programming provided by External Address 4 is satisfactory, the SYNC pulse arrives. If it is written to Logic 0, then the counter user does not need to reprogram the elements of this register. does not respond to a SYNC pulse. Unlike the two bits in 0x81 above, setting the Hop_En or the 0x84: Hop or Frequency Hold-Off Counter Start_En (Bits 1 and 0) of this register does not trigger anything. The NCO frequency hold-off counter is loaded with the 16-bit These bits simply allow, or enable, an external synchronizing value written to this address upon receipt of either a Soft_SYNC signal to be routed to the channel’s start and/or hop multi- or Pin_SYNC. The counter begins counting, and when the plexers. Even though a signal has been enabled to reach the count reaches a value of 1, the 32-bit NCO frequency word is multiplexer, it still needs to be selected. This job is accomplished updated with the values at 0x85 and 0x86. This is known as a by Bits 8 and 7 of 0x88, as discussed below. The schematic hop or Hop_SYNC. Writing this register to a value of 1 causes diagram of Figure 53 is helpful in understanding the Pin_SYNC the NCO frequency to be updated immediately when the SYNC enabling and selection bits of the involved registers. comes into the channel. If it is written to a 0, then no Hop occurs. NCO hops can be either phase-continuous or non- Bit 2 of 0x82 engages the first sync only function for the phase-continuous, depending upon the state of Bit 3 of the channel. This bit is a copy of External Address 4, Bit 6, but can Rev. 0 | Page 58 of 76

AD6652 NCO control register at Channel Address 0x88. When this bit is hold-off counter count reaches a value of 1. If the frequency low, then the phase accumulator of the NCO is not cleared, but hold-off counter value is set to a value of 1, then the register is starts to add the new NCO frequency word to the accumulator updated as soon as the shadow is written. as soon as the SYNC occurs. If this bit is high, then the phase 0x86: NCO Frequency Register 1 accumulator of the NCO is cleared to 0, and the new word is This register represents the 16 MSBs of the NCO frequency then accumulated. word. These bits are shadowed and are not updated to the 0x85: NCO Frequency Register 0 working register until the channel is either brought out of sleep This register represents the 16 LSBs of the NCO frequency mode, or a Soft_SYNC or Pin_SYNC has been issued. In the word. These bits are shadowed and are not updated to the latter two cases, the register is updated only when the frequency working register until the channel is either brought out of sleep hold-off counter count reaches a value of 1. If the frequency mode, or a Soft_SYNC or Pin_SYNC has been issued. In the hold-off counter is set to a value of 1, then the register is latter two cases, the register is updated when the frequency updated as soon as the shadow is written. Table 24. Channel Address Memory Map Channel Address Register Bit Width Comments 00–7F Coefficient Memory (CMEM) 20 128 x 20-bit memory 80 CHANNEL SLEEP 1 0: Sleep bit from EXT_ADDRESS 3 81 Soft_Sync Control Register 2 1: Hop 0: Start 82 Pin_SYNC Control Register 3 2: First SYNC only 1: Hop_En 0: Start_En 83 Start Hold-Off Counter 16 Start hold-off value 84 NCO Frequency Hold-Off Counter 16 NCO_FREQ hold-off value 85 NCO Frequency Register 0 16 NCO_FREQ[15:0] 86 NCO Frequency Register 1 16 NCO_FREQ[31:16] 87 NCO Phase Offset Register 16 NCO_PHASE[15:0] 88 NCO Control Register 9 8-7: SYNC input select[1:0] 00 = A, 01 = B, 10 = C, 11 = D 6: Input port select B or A, 0 = A, 1 = B 5-4: Reserved, write both bits logic low 3: Clear phase accumulator on hop 2: Amplitude dither 1: Phase dither 0: Bypass (A-input -> I-path, B -> Q) 89–8F Unused 90 rCIC2 Decimation − 1 12 M − 1 rCIC2 91 rCIC2 Interpolation − 1 9 L − 1 rCIC2 92 rCIC2 Scale 12 11: Reserved, write to logic low 10: Reserved, write to logic low 9-5: rCIC2 _QUIET [4:0] 4-0: rCIC2_LOUD [4:0] 93 Reserved 8 Reserved (must be written low) 94 CIC5 Decimation − 1 8 M − 1 CIC5 95 CIC5 Scale 5 4-0: CIC5_SCALE[4:0] 96 Reserved 8 Reserved (must be written low) 97–9F Unused A0 RCF Decimation − 1 8 M − 1 RCF A1 RCF Decimation Phase 8 P RCF A2 RCF Number of Taps − 1 8 N − 1 Taps A3 RCF Coefficient Offset 8 CO RCF Rev. 0 | Page 59 of 76

AD6652 Channel Address Register Bit Width Comments A4 RCF Control Register 11 10: RCF bypass BIST 9: RCF input select (own 0, other 1) 8: Program RAM bank 1/0 7: Use common exponent 6: Force output scale 5-4: Output format 1x: Floating point 12 + 4 01: Floating point 8 + 4 00: Fixed point 3-0: Output scale A5 BIST Signature for I Path 16 BIST-I A6 BIST Signature for Q Path 16 BIST-Q A7 BIST Outputs to Accumulate 20 19-0: Number of outputs (counter value read) A8 RAM BIST Control Register 3 2: D-RAM fail/pass 1: C-RAM fail/pass 0: RAM BIST enable A9 Output Control Register 10 9: Map RCF data to BIST registers 5: Output format 1: 16-bit I and 16-bit Q 0: 12-bit I and 12-bit Q 4-0: Reserved, write to Logic 0 0x87: NCO Phase Offset Register Bit 3 determines whether or not the phase accumulator of the This register represents a 16-bit phase offset to the NCO. It can NCO is cleared when a hop occurs. The hop can originate from be interpreted as values ranging from 0 to just under 2π. The either Pin_SYNC or Soft_SYNC. When this bit is set to 0, the 16-bit phase offset is added to the 16 MSBs of the 32-bit NCO hop is phase-continuous and the accumulator is not cleared. phase accumulator to arrive at the final phase angle number When this bit is set to 1, the accumulator is cleared to 0 before it used to compute the amplitude value. begins accumulating the new frequency word. This is appropri- 0x88: NCO Control Register ate when multiple channels are hopping from different frequen- cies to a common frequency. This 9-bit register controls features of the NCO and the channel. The bits are defined in this section. For details, see the Bits 2–1 control whether or not the phase and amplitude dither Numerically Controlled Oscillator section. functions of the NCO are activated. The use of these features is determined by the system constraints. See the Numerically Bits 8–7 of this register choose which one of the four Controlled Oscillator section for more information on the use Pin_SYNC pins (A, B, C, or D) is used by the channel to initiate of dither. As usual, a logic high activates the function. channel start and frequency hop functions. These bits can also be used to make timing adjustments to a channel. Bit 0 of this register allows the NCO frequency translation stage to be bypassed. When this occurs, the data from Input Port A is Table 25 shows the bit logic state needed to select a particular passed down the I path of the channel and the data from Input Pin_Sync. Port B is passed down the Q path of the channel. This allows a Table 25. Bit Logic States for Sync Pins real filter to be performed on baseband I and Q data. 0x88:8 0x88:7 Sync Pin Selected Ox89–0x8F: Unused 0 0 A Unused. 0 1 B 1 0 C 0x90: rCIC2 Decimation − 1 (MrCIC2 − 1) 1 1 D This register sets the decimation in the rCIC2 filter. The value Bit 6 of this register defines which ADC channel, A or B, is used written to this register is the decimation minus one. The rCIC2 by the DDC channel being programmed. If this bit is low, then decimation can range from 1 to 4096, depending upon the Input Port A selected; if this bit is high, Input Port B is selected. interpolation of the channel. The decimation must always be greater than the interpolation. Bits 5–4 are reserved and must be written logic low. Rev. 0 | Page 60 of 76

AD6652 M must be chosen larger than L , and both must be it retains the phase setting chosen here. This can be used as part rCIC2 rCIC2 chosen such that a suitable rCIC2 scalar can be chosen. For of a timing recovery loop with an external processor or can details, see the Second-Order RCIC Filter section. allow multiple RCFs to work together while using a single RCF pair. For details, see the RAM Coefficient Filter section. 0x91: rCIC2 Interpolation − 1 (L − 1) rCIC2 0xA2: RCF Number of Tap – 1 (N − 1) This register is used to set the interpolation in the rCIC2 filter. RCF The value written to this register is the interpolation minus 1. The number of taps for the RCF filter minus 1 is written to this The rCIC2 interpolation can range from 1 to 512, depending register. upon the decimation of the rCIC2. There is no timing error 0xA3: RCF Coefficient Offset (CO ) RCF associated with this interpolation. For details, see the Second- This register is used to specify which section of the 256-word Order RCIC Filter section. coefficient memory is used for a filter. It can be used to select 0x92: rCIC2 Scale among multiple filters that are loaded into memory and The rCIC2 scale register is used to provide attenuation to referenced by this pointer. compensate for the gain of the rCIC2 and to adjust the lineari- This register is shadowed, and the filter pointer is updated zation of the data from the floating-point input. The use of this (from the shadow register) on every new filter output sample. scale register is influenced by the rCIC2 growth. For details, see This allows the coefficient offset to be written without the Second-Order RCIC Filter section. disturbing operation, even while a filter is being computed. The Bit 11 is reserved. Write all bits to Logic 0. next sample that comes out of the RCF is with the new filter. 0xA4: RCF Control Register Bit 10 is reserved. Write all bits to Logic 0. The RCF control register is an 11-bit register that controls the Bits 9–5 are the actual scale value used when the level indicator, general features of the RCF as well as output formatting. The LI pin associated with this channel, is active (Logic 1). bits of this register and their functions are described below. Bits 4–0 are the actual scale value used when the level indicator, Bit 10 bypasses the RCF filter and sends the CIC5 output data to LI pin associated with this channel, is inactive (Logic 0). the BIST-I and BIST-Q registers. The 16 MSBs of the CIC5 data 0x93: Reserved can be accessed from this register, if Bit 9 of the output control register at Channel Address 0xA9 is set. Eight bits, reserved (must be written low). 0x94: CIC5 Decimation – 1 (M − 1) Bit 9 of this register controls the source of the input data to the CIC5 RCF. If this bit is 0, then the RCF processes the output data of its This register is used to set the decimation in the CIC5 filter. The own channel. If this bit is 1, then it processes the data from the 8-bit value written to this register is the decimation minus 1. CIC5 of another channel. The CIC5 channels that the RCF can 0x95: CIC5 Scale be connected to when this bit is 1 are shown in the Table 26. The 5-bit CIC5 scale factor is used to compensate for the These can be used to allow multiple RCFs to be used together to growth of the CIC5 filter. For details, see the Fifth-Order CIC process wider bandwidth channels. Filter section. Table 26. RCF Input Configurations 0x96: Reserved Channel RCF Input Source when Bit 9 Is 1 Reserved (must be written low). 0 1 0x97–0x9F: Unused 1 0 2 1 Unused. 3 1 0xA0: RCF Decimation − 1 (M − 1) RCF Bit 8 is used as an extra address to allow a second block of This register is used to set the decimation of the RCF stage. The 128 words of CMEM to be addressed by the channel addresses value written to this register is the desired decimation minus at 0x00–0x7F. If this bit is 0, then the first 128 words are written; one. Although this is an 8-bit register that allows decimation up if this bit is 1, then the next 128 words are written. This bit is to 256, most filter designs should be limited to between 1 and used to program only the coefficient memory so that filters 32. Higher decimations are allowed, but the alias rejection of the longer than 128 taps can be realized. RCF might not be acceptable for some applications. Bit 7 is used to control the output formatting of the AD6652’s 0xA1: RCF Decimation Phase (P ) RCF RCF data. This bit is used only when the 8 + 4 or 12 + 4 This register allows any one of the M phases of the filter to be RCF floating-point modes are chosen. These modes are enabled by used and can be adjusted dynamically. Each time a filter is Bits 5 and 4 of this register. When this bit is 0, then the I and Q started, this phase is updated. When a channel is synchronized, output exponents are determined separately based on their Rev. 0 | Page 61 of 76

AD6652 individual magnitudes. When this bit is 1, then the I and Q data 0xA6: BIST Register for Q is a complex floating-point number, where I and Q use a single This register serves two purposes. The first is to allow the exponent that is determined based on the maximum magnitude complete functionality of the Q data path in the channel to be of I or Q. tested in the system. See the User-Configurable Built-In Self- Test (BIST) section for further details. The second function is to Bit 6 is used to force the output scale factor in Bits 3–0 of this provide access to the Q output data through the microport. To register to be used to scale the data even when one of the accomplish this, the Map RCF Data to BIST bit in the RCF floating-point output modes is used. If the number is too large Control Register 2, 0xA9, should be set high. Then 16 bits of Q to represent with the output scale chosen, then the mantissas of data can be read through the microport in either the 8 + 4, the I and Q data clip do not overflow. 12 + 4, 12-bit linear, or 16-bit linear output modes. This data Normally, the AD6652 determines the exponent value that can come from either the formatted RCF output or the optimizes numerical accuracy. However, if Bit 6 is set, the value CIC5 output. stored in Bits 3–0 is used to scale the output. This ensures 0xA7: BIST Outputs to Accumulate consistent scaling and accuracy during conditions that warrant This 20-bit register controls the number of outputs of the RCF predictable output ranges. or CIC filter that are observed when a BIST test is performed. Bits 5 and 4 choose the output formatting option used by the The BIST signature registers at Addresses 0xA5 and 0xA6 RCF data. The options are defined in the Table 27 and are observe this number of outputs and then terminate. The loading discussed further in the Output Port Control Registers section. of this register also starts the BIST engine running. For details on utilizing the BIST circuitry, see the User-Configurable Built- Table 27. Output Formats In Self-Test (BIST) section. Bit Value Output Formatting Option 0xA8: RAM BIST Control Register 1x 12-bit mantissa and 4-bit exponent (12 + 4) 01 8-bit mantissa and 4-bit exponent (8 + 4) This 3-bit register is used to test the memories of the AD6652, if 00 Fixed point mode a failure is suspected. Bit 0 of this register is written with a 1 when the channel is in sleep mode. The user waits for Bits 3–0 of this register represent the output scale factor of the 1600 CLKs, and then polls the bits. If Bit 1 is high, then the RCF. The scale factor is used to scale the data when the output CMEM failed the test; if Bit 2 is high, then the data memory format is in fixed-point mode or when the force exponent bit is used by the RCF failed the test. high. If Bits 3–0 are represented by RCF scale, the scaling factor in dB is given by 0xA9: Output Control Register Bit 9 of this register allows the RCF or CIC5 data to be mapped Scaling Factor=(RCFScale − 3)× 20log (2)dB 10 to the BIST registers at Addresses 0xA5 and 0xA6. When this bit is 0, then the BIST register is in signature mode and ready for a For an RCF scale of 0, the scaling factor is equal to −18.06 dB; self-test to be run. When this bit is 1, then the output data from for a maximum RCF scale of 15, the scaling factor is equal to the RCF (after formatting) or from CIC5 data is mapped to +72.25 dB. these registers and can be read through the microport. 0xA5: BIST Register for I Bit 5 determines the word length used by the parallel port. If This register serves two purposes. The first is to allow the this bit is 0, then the parallel port uses 12-bit words for I and Q. complete functionality of the I datapath in the channel to be If this bit is 1, then the parallel port uses 16-bit words for I and tested in the system. See the User-Configurable Built-In Self- Q. When the fixed-point output option is chosen from the RCF Test (BIST) section for details. The second function is to control register, then these bits also set the rounding correctly in provide access to the I output data through the microport. To the output formatter of the RCF. accomplish this, the Map RCF Data to BIST bit in the RCF Control Register 2, 0xA9, should be set high. Then 16 bits of I Bits 4–0 are reserved and should be written low when data can be read through the microport in either the 8 + 4, programming. 12 + 4, 12-bit linear, or 16-bit linear output modes. This data can come from either the formatted RCF output or the CIC5 output. Rev. 0 | Page 62 of 76

AD6652 INPUT PORT CONTROL REGISTERS Bit 2–0 determines the internal latency of the gain detect The input port control registers enable various input-related function. When the LIA, LIA pins are made active, they are features used primarily for level control. Depending on the typically used to change an attenuator or gain stage. Because mode of operation, up to four different signal paths can be this is prior to the ADC, there is a latency associated with the monitored with these registers. These features are accessed by ADC and with the settling of the gain change. This register setting Bit 5 of External Address 3 (sleep register) and then allows the internal delay of the LIA, LIA signal to be using the CAR (External Address 6) to address the eight programmed. locations available. Response to these settings is directed to the 0x04: Lower Threshold B LIA, LIA, LIB, and LIB pins. This word is 10 bits wide and maps to the 10 MSB of the mantissa. If the upper 10 bits of Input Port B are less than or To access the input port registers, the program gain control bit equal to this value, then the lower threshold has been met. In should be written high. The CAR is then written with the normal chip operation, this starts the dwell time counter. If the address to the correct input port register. input signal increases above this value, then the counter is 0x00: Lower Threshold A reloaded and awaits the input to drop back to this level. This word is 10 bits wide and maps to the 10 MSB of the 0x05: Upper Threshold B mantissa. If the upper 10 bits of Input Port A are less than or This word is 10 bits wide and maps to the 10 MSB of the equal to this value, then the lower threshold has been met. In mantissa. If the upper 10 bits of Input Port B are greater than or normal chip operation, this starts the dwell time counter. If the equal to this value, then the upper threshold has been met. In input signal increases above this value, then the counter is normal chip operation, this causes the appropriate LI pin (LIB reloaded and awaits the input to drop back to this level. or LIB) to become active 0x01: Upper Threshold A 0x06: Dwell Time B This word is 10 bits wide and maps to the 10 MSB of the mantissa. If the upper 10 bits of Input Port A are greater than or This word sets the time that the input signal must be at or below equal to this value, then the upper threshold has been met. In the lower threshold before the LI pin is deactivated. For the normal chip operation, this causes the appropriate LI pin (LIA input level detector to work, the dwell time must be set to at or LIA) to become active. least 1. If set to 0, the LI functions are disabled. This is a 20-bit register. When the lower threshold is met following an 0x02: Dwell Time A excursion into the upper threshold, the dwell time counter is This word sets the time that the input signal must be at or below loaded and begins to count high speed clock cycles as long as the lower threshold before the LI pin is deactivated. For the the input is at or below the lower threshold. If the signal input level detector to work, the dwell time must be set to at increases above the lower threshold, the counter is reloaded and least 1. If set to 0, the LI functions are disabled. This is a 20-bit waits for the signal to fall below the lower threshold again. register. When the lower threshold is met following an 0x0: Gain Range B Control Register excursion into the upper threshold, the dwell time counter is loaded and begins to count high speed clock cycles as long as Bit 4 determines the polarity of LIB and LIB. If this bit is the input is at or below the lower threshold. If the signal clear, then the LI signal is high when the upper threshold has increases above the lower threshold, the counter is reloaded and been exceeded. However, if this bit is set, the LI pin is low waits for the signal to fall below the lower threshold again. when active. This allows maximum flexibility when using this function. 0x03: Gain Range A Control Register Bit 4 determines the polarity of LIA and LIA. If this bit is Bit 3 = 0 (Reserved. clear, then the LI signal is high when the upper threshold has Bit 2–0 determines the internal latency of the gain detect been exceeded. However, if this bit is set, the LI pin is low function. When the LIB, LIB pins are made active, they are when active. This allows maximum flexibility when using typically used to change an attenuator or gain stage. Because this function. this is prior to the ADC, there is a latency associated with Bit 3 = 0 (Reserved). the ADC and with the settling of the gain change. This register allows the internal delay of the LIB, LIB signal to be programmed. Rev. 0 | Page 63 of 76

AD6652 Table 28. Memory Map for Input Port Control Registers Channel Address Register Bit Width Comments 00 Lower Threshold A 10 9–0: Lower threshold for Input A 01 Upper Threshold A 10 9–0: Upper threshold for Input A 02 Dwell Time A 20 19–0: Minimum time below Lower Threshold A 03 Gain Range A Control Register 5 4: Output polarity LIA and LIA 3: (0) Reserved 2–0: Linearization hold-off register 04 Lower Threshold B 10 9–0: Lower threshold for Input B 05 Upper Threshold B 10 9–0: Upper threshold for Input B 06 Dwell Time B 20 19–0: Minimum time below Lower Threshold B 07 Gain Range B Control Register 5 4: Output polarity LIB and LIB 3: (0) Reserved 2–0: Linearization hold-off register OUTPUT PORT CONTROL REGISTERS Bits 2 and 1 choose which channels are interleaved. The truth table for these bits is shown in Table 29. This group of registers is dedicated to data management after individual channels have processed the incoming data. They Bit 0, the bypass bit, when high, directs data from the interleave manage data interleaving, 2× interpolation, AGC functions, stage to bypass the half-band filter stage and proceed directly to output port assignment, and output port setup. Because there the AGC stage without interpolation. The channel data streams are two output ports, A and B, the data must be funneled from are still interleaved, but they are not filtered or interpolated. The four channels down to two. These registers are responsible for maximum data rate from this configuration is two times the guiding the data directly to the proper output port(s) or chip rate. detouring the data through other post-filtering stages (AGC, and so on) before the output port is selected. When Bit 0 is low, data from the interleave stage is passed through the half-band filter and undergoes a 2× interpolation To access the output port registers for Output Ports A and B, Bit rate. The maximum output data rate of the half-band is four 5 of External Address 3 (the sleep register) must be written logic times the chip rate. high. The channel address register (CAR) is then written with 0x09: LHB B Control Register the address to the correct output port register. See Table 29 for a complete listing and brief description of all registers. Same as LHB A, except that only two channels can be inter- leaved. Channels are selected using only Bit 1; Bit 2 is the LHB B 0x00–0x07: Reserved enable bit. Reserved. All bits should be written logic low. 0x0A: AGC A Control Register 0x08: LHB A Control Register Bits 7–5 define the output word length of the AGC. The output LHB is the acronym for interpolating half-band, with L being a word can be 4 to 8, 10, 12, or 16 bits wide. The truth table to widely accepted symbol for interpolation. This register includes obtain different output word lengths is given in the Table 29 the interleaving stage as well as the half-band filter stage, as memory map, 0x0A. shown in Figure 64. These two stages are controlled separately from the final AGC stage, so that they do not get lost among the Bit 4 of this register sets the mode of operation for the AGC. numerous AGC control elements. When this bit is 0, the AGC tracks to maintain the output signal level; when this bit is 1, the AGC tracks to maintain a constant Bit 3, the LHB A enable bit, acts as an on/off switch for the clipping error. See the Automatic Gain Control section for interleave stage, half-band filter, and the AGC stage. See details about these two modes. Figure 64. If Bit 3 is low, the interleave stage is shut down and prevents any further propagation of data to the remaining Bits 3–1 are used to configure the synchronization of the AGC. stages. This condition is desirable when the three stages are not The CIC decimator filter in the AGC can be directly synchro- needed and power conservation is desired. When Bit 3 is high, nized to an externally generated signal. When synchronized, the the interleave stage is active and works to interleave the data of AGC outputs an update sample for the AGC error calculation up to four DDC channels according to the truth table of Bit 2 and filtering. This way, the AGC gain changes can be synchro- and Bit 1. The data is then propagated to the LHB and AGC nized to a Rake receiver. stages with bypass opportunities included. Rev. 0 | Page 64 of 76

AD6652 BYPASS BYPASS (0x08:0, 0x09:0) (0x0A:0, 0x12:0) LHB CHANNEL HALF-BAND INTERLEAVE FILTER AND AGC PROCESSED DATA 2× INTERPOLATION TO OUTPUT PORTS FROM RCFS A AND B E(0NxA08B:L3E, 0/DxI0S9A:2B)LE 03198-0-051 Figure 64. Block Diagram of an AGC Stage Showing the Components and Signal Routing Options control register. A truncation at the output of the AGC Note: The hold-off counter of AGC A shares the PIN SYNC accomplishes this task. assigned to DDC processing Channel 0. Therefore, if the user intends to use the AGC A’s hold-off counter, the user must 0x0B: AGC A Hold-Off Counter attach the external sync signal to the pin sync that is assigned to The AGC A hold-off counter is loaded with the 16-bit value DDC Channel 0. The hold-off counter register at Address 0x0B written to this address when Sync Now is written high or a for AGC A must be programmed with a 16-bit number that Pin_Sync is received. If this register is written to a 0, the AGC corresponds to the desired delay before a new CIC decimated cannot be synchronized. value is updated. Writing a logic high to the proper pin sync pin triggers the AGC hold-off counter with a retriggerable one-shot Note: The hold-off counter of AGC A shares the pin sync pulse every time the pin is written high. assigned to DDC processing Channel 0. Therefore, if the user intends to use AGC A’s hold-off counter, the user must either Bit 3 is the sync now bit. If the user chooses not to use pin sync attach the external sync signal to the pin sync that is assigned to signals, the user can use the Sync Now command by program- DDC Channel 0 or use the software-controlled Sync Now ming this bit high. This performs an immediate start of function of Bit 3 at 0x0A. decimation for a new update sample and initializes the AGC, if Bit 2 is set. This bit has a one-shot characteristic and does not The hold-off counter must be programmed with a 16-bit need to be reset in order to respond to a new logic high being number that corresponds to the desired delay before a new CIC written to it. Use of the sync now bit bypasses the AGC hold-off decimated value is updated. Writing a logic high to the proper counters; therefore, the name Sync Now. pin sync pin triggers the AGC hold-off counter with a retriggerable one-shot pulse every time the pin is written high. Bit 2 is used to determine whether the AGC should initialize on 0x0C: AGC A Desired Level a Sync Now or not. When this bit is set, the CIC filter is cleared and new values for CIC decimation, number of averaging This 8-bit register contains the desired output power level or samples, CIC scale, signal gain Gs, gain K, and pole parameter P desired clipping level, depending on the mode of operation. are loaded. When Bit 2 = 0, the above-mentioned parameters are This desired request R level can be set in dB from 0 to not updated and the CIC filter is not cleared. In both cases, an −23.99 dB, in steps of 0.094 dB. An 8-bit binary floating-point AGC update sample is output from the CIC filter and the representation is used with a 2-bit exponent followed by the decimator starts operating towards the next output sample 6-bit mantissa. The mantissa is in steps of 0.094 dB and the whenever a Sync Now occurs. exponent is in 6.02 dB steps. For example: 10’100101 represents 2 × 6.02 + 37 × 0.094 = 15.518 dB. Bit 1 is used to ignore repetitive Pin_Sync signals. In some 0x0D: AGC A Signal Gain applications, the synchronization signal might occur periodi- cally. If this bit is clear, each Pin_Sync resynchronizes the AGC. This register is used to set the initial value for a signal gain used If this bit is set, only the first sync high is recognized and in the gain multiplier. This 12-bit value sets the initial signal succeeding sync events are ignored until Bit 1 is reset. gain between 0 and 96.296 dB in steps of 0.024 dB. A 12-bit binary floating-point representation is used with a 4-bit Bit 0 is used to bypass the AGC section, when it is set. The data exponent followed by the 8-bit mantissa. For example: from the interpolating half-band filters is still reduced to a 0111’10001001 represents 7 × 6.02 + 137 × 0.024 = 45.428 dB. lower bit width representation as set by Bits 7–5 of the AGC A Rev. 0 | Page 65 of 76

AD6652 Table 29. Memory Map for Output Port Control Registers Address Register Bit Width Comments 08 LHB A Control Register 4 3: LHB A enable1 2–1: LHB A signal interleaving 11 All 4 channels 10 Channels 0, 1, 2 01 Channels 0, 1 00 Channel 0 0: Bypass LHB A1 09 LHB B Control Register 3 2: LHB B enable1 1: LHB B signal interleaving 1: Channels 2, 3 0: Channel 2 0: Bypass LHB B1 0A AGC A Control Register 8 7–5: Output word length 111 4 bits 110 5 bits 101 6 bits 100 7 bits 011 8 bits 010 10 bits 001 12 bits 000 16 bits 4: Clipping error 1: Maintain level of clipping error 0: Maintain output signal level 3: Sync now 2: Init on sync 1: First sync only 0: Bypass 0B AGC A Hold-Off Counter 16 15–0: Hold-off value 0C AGC A Desired Level 8 7–0: Desired output power level or clipping energy (R parameter) 0D AGC A Signal Gain 12 11–0: Gs parameter 0E AGC A Loop Gain 8 7–0: K parameter 0F AGC A Pole Location 8 7–-0: P parameter 10 AGC A Average Samples 6 5–2: Scale for CIC decimator 1–0: Number of averaging samples 11 AGC A Update Decimation 12 11–0: CIC decimation ratio 12 AGC B Control Register 8 7–5: Output word length 111 4 bits 110 5 bits 101 6 bits 100 7 bits 011 8 bits 010 10 bits 001 12 bits 000 16 bits 4: Clipping error 1: Maintain level of clipping error 0: Maintain output signal level Rev. 0 | Page 66 of 76

AD6652 Address Register Bit Width Comments 3: Sync now 2: Init on Sync 1: First sync only 0: Bypass 13 AGC B Hold-Off Counter 16 15–0: Hold-off value 14 AGC B Desired Level 8 7–0: Desired output power level or clipping energy (R parameter) 15 AGC B Signal Gain 12 11–0: Gs parameter 16 AGC B Loop Gain 8 7–0: K parameter 17 AGC B Pole Location 8 7–0: P parameter 18 AGC B Average Samples 6 5–2: Scale for CIC decimator 1–0: Number of averaging samples 19 AGC B Update Decimation 12 11–0: CIC decimation 1A Parallel A Control 8 7–6: Reserved 5: Parallel port data format 1: 8-bit parallel I, Q 0: 16-bit interleaved I, Q 4: Channel 3 3: Channel 2 2: Channel 1/AGC B enable 1: Channel 0/AGC A enable 0: AGC_CH select 1: Data comes from AGCs 0: Data comes from channels 1B Link A Control 8 7: Link Port A enable 6–3: Wait 2: No RSSI word 1: Don’t output RSSI word 0: Output RSSI word 1: Channel data interleaved 1: 2-channel mode/separate AB 0: 4-channel mode/AB same port 0: AGC_CH select 1: Data comes from AGCs 0: Data comes from channels 1C Parallel B Control 8 7–6: Reserved 5: Parallel port data format 1: 8-bit parallel I, Q 0: 16-bit interleaved I, Q 4: Channel 3 3: Channel 2 2: Channel 1/AGC B enable 1: Channel 0/AGC A enable 0: AGC_CH select 1: Data comes from AGCs 0: Data comes from channels 1D Link B Control 8 7: Link Port B enable 6–3: Wait 2: No RSSI word 1: Do not output RSSI word 0: Output RSSI word Rev. 0 | Page 67 of 76

AD6652 Address Register Bit Width Comments 1: Channel data interleaved 1: 2-channel mode/separate AB 0: 4-channel mode/AB same port 0: AGC_CH select 1: Data comes from AGCs 0: Data comes from channels 1E Port Clock Control 3 2–1: PCLK divisor 0: PCLK master/slave2 0: Slave 1: Master 1 Set the LHB A and/or LHB B enable bits to logic low only when the entire block functions (LHB signal interleaving, LHB filtering, and AGC functions) are to be shut down. 2 PCLK boots as a slave. 0x0E: AGC A Loop Gain The CIC decimator filter in the AGC can be indirectly synchronized to an externally generated signal. When synchro- This 8-bit register defines the open loop gain K. Its value can be nized, the AGC outputs an update sample for the AGC error set from 0 to 0.996 in steps of 0.0039. This value of K is updated calculation and filtering. This way, the AGC gain changes can be in the AGC loop each time the AGC is initialized. synchronized to a Rake receiver or other external block. 0x0F: AGC A Pole Location This 8-bit register defines the open loop filter pole location P. Its Note: The hold-off counter of AGC B shares the pin sync value can be set from 0 to 0.996 in steps of 0.0039. This value of assigned to DDC processing Channel 2. Therefore, if the user P is updated in the AGC loop each time the AGC is initialized. intends to use the AGC B’s hold-off counter, the user must This open loop pole location directly impacts the closed loop attach the external sync signal to the pin sync that will be pole locations. See the Automatic Gain Control section. assigned to DDC Channel 2. The hold-off counter must be programmed with a 16-bit number that corresponds to the 0x10: AGC A Average Samples desired delay before a new CIC decimated value is updated. This 6-bit register contains the scale used for the CIC filter and Writing a logic high to the proper pin sync pin triggers the AGC the number of power samples to be averaged before being fed to hold-off counter with a retriggerable one-shot pulse every time the CIC filter. the pin is written high. Bits 5–2 define the scale used for the CIC filter. Bit 3 is the sync now bit. If the user chooses not to use pin sync signals, the user can use the Sync Now command by program- Bits 1–0 define the number of samples to be averaged before ming this bit high. This performs an immediate start of they are sent to the CIC decimating filter. This number can be decimation for a new update sample and initializes the AGC, if set between 1 and 4 with 00 meaning one sample and 11 mean- Bit 2 is set. This bit has a one-shot characteristic and does not ing four samples. need to be reset in order to respond to a new logic high being 0x11: AGC A Update Decimation written to it. Use of the sync now bit bypasses the AGC hold-off This 12-bit register sets the AGC decimation ratio from 1 to counters; therefore, the name Sync Now. 4096. Set an appropriate scaling factor to avoid loss of bits. Bit 2 is used to determine whether the AGC should initialize on 0x12: AGC B Control Register a Sync Now or not. When this bit is set, the CIC filter is cleared Bits 7–5 define the output word length of the AGC. The output and new values for CIC decimation, number of averaging word can be 4 to 8, 10, 12, or 16 bits wide. The control register samples, CIC scale, signal gain Gs, gain K, and pole parameter P bit representation to obtain different output word lengths is are loaded. When Bit 2 = 0, the above-mentioned parameters are given in Table 29. not updated and the CIC filter is not cleared. In both cases, an AGC update sample is output from the CIC filter and the Bit 4 of this register sets the mode of operation for the AGC. decimator starts operating towards the next output sample When this bit is 0, the AGC tracks to maintain the output signal whenever a Sync Now occurs. level; when this bit is 1, the AGC tracks to maintain a constant clipping error. See the Automatic Gain Control section for Bit 1 is used to ignore repetitive Pin_Sync signals. In some details about these two modes. applications, the synchronization signal might occur periodi- cally. If this bit is clear, each Pin_Sync resynchronizes the AGC. Bits 3–1 are used to configure the synchronization of the AGC. Rev. 0 | Page 68 of 76

AD6652 If this bit is set, only the first sync high is recognized and 0x18: AGC B Average Samples succeeding sync events are ignored until Bit 1 is reset. This 6-bit register contains the scale used for the CIC filter and the number of power samples to be averaged before being fed to Bit 0 is used to bypass the AGC section, when it is set. When the the CIC filter. AGC is bypassed, the output data is the 16 MSBs of the 24-bit input data from the half-band filter. Bits 5–2 define the scale used for the CIC filter. 0x13: AGC B Hold-Off Counter Bits 1–0 define the number of samples to be averaged before The AGC B hold-off counter is loaded with the 16-bit value they are sent to the CIC decimating filter. This number can be written to this address when Sync Now is written high or a set between 1 and 4 with bit representation 00 meaning one Pin_Sync signal is received. If this register is written to 0, the sample and bit representation 11 meaning four samples. AGC cannot be synchronized. 0x19: AGC B Update Decimation Note: The hold-off counter of AGC B shares the pin sync This 12-bit register sets the AGC decimation ratio from 1 to assigned to DDC processing Channel 2. Therefore, if the user 4096. Set an appropriate scaling factor to avoid loss of bits. intends to use AGC A’s hold-off counter, the user must either 0x1A: Parallel Port Control A attach the external sync signal to the pin sync that is assigned to DDC Channel 2, or use the software-controlled sync now Data is output through either a parallel port interface or a link function of Bit 3 at 0x12. port interface. When 0x1B, Bit 7 = 0, the use of Link Port A is disabled and the use of Parallel Port A is enabled. The parallel The hold-off counter must be programmed with a 16-bit port provides different data modes for interfacing with DSPs or number that corresponds to the desired delay before a new CIC FPGAs. decimated value is updated. Writing a logic high to the proper pin sync pin triggers the AGC hold-off counter with a retrigger- Bit 0 selects which data is output on Parallel Port A. When able one-shot pulse every time the pin is written high. Bit 0 = 0, Parallel Port A outputs data from the RCF according to the format specified by Bits 1–4. When Bit 0 = 1, Parallel 0x14: AGC B Desired Level Port A outputs the data from the AGCs according to the format This 8-bit register contains the desired output power level or specified by Bits 1 and 2. desired clipping level, depending on the mode of operation. This desired request R level can be set from 0 dB to −23.99 dB In AGC mode, Bit 0 = 1 and Bit 1 determines if Parallel Port A in steps of 0.094 dB. An 8-bit binary floating-point representa- can output data from AGC A. Bit 2 determines if Parallel Port A tion is used with a 2-bit exponent followed by the 6-bit man- can output data from AGC B. The order of output depends on tissa. The mantissa is in steps of 0.094 dB and the exponent is in the rate of triggers from each AGC, which in turn is determined 6.02 dB steps. For example: 10’100101 represents 2 × 6.02 + 37 × by the decimation rate of the channels feeding it. In channel 0.094 = 15.518 dB. mode, Bit 0 = 0 and Bits 1–4 determine which combination of the four processing channels is output. The output order 0x15: AGC B Signal Gain depends on the rate of triggers received from each channel, This register is used to set the initial value for a signal gain used which is determined by the decimation rate of each channel. in the gain multiplier. This 12-bit value sets the initial signal The channel output indicator pins can be used to determine gain between 0 dB and 96.296 dB in steps of 0.024 dB. A 12-bit which data came from which channel. binary floating-point representation is used with a 4-bit expo- nent followed by the 8-bit mantissa. For example: Bit 5 determines the format of the output data words. When 0111’10001001 represents 7 × 6.02 + 137 × 0.024 = 45.428 dB. Bit 5 = 0, Parallel Port A outputs 16-bit words on its 16-bit bus. This means that I and Q data are interleaved, and the IQ 0x16: AGC B Loop Gain indicator pin determines whether data on the port is I data or This 8-bit register is used to define the open loop gain K. Its Q data. When Bit 5 = 1, Parallel Port A is outputting an 8-bit value can be set from 0 to 0.996 in steps of 0.0039. This value of I word and an 8-bit Q word at the same time, and the IQ K is updated in the AGC loop each time the AGC is initialized. indicator pins are high. 0x17: AGC B Pole Location 0x1B: Link Port Control A This 8-bit register is used to define the open loop filter pole Data is output through either a parallel port interface or a link location P. Its value can be set from 0 to 0.996 in steps of 0.0039. port interface. The link port provides an efficient data link This value of P is updated in the AGC loop each time the AGC between the AD6652 and a TigerSHARC DSP and can be is initialized. This open loop pole location directly impacts the enabled by setting 0x1D, Bit 7 = 1. closed loop pole locations as explained in the Automatic Gain Control section. Rev. 0 | Page 69 of 76

AD6652 combination of the four processing channels is output. The Bit 0 selects which data is output on Link Port A. When output order depends on the rate of triggers received from each Bit 0 = 0, Link Port A outputs data from the RCF according to channel, which is determined by the decimation rate of each the format specified by Bit 1. When Bit 0 = 1, Link Port A channel. The channel output indicator pins can be used to outputs the data from the AGCs according to the format determine which data came from which channel. specified by Bits 1 and 2. Bit 5 determines the format of the output data words. When Bit 1 has two different meanings, depending on whether data is Bit 5 = 0, Parallel Port B outputs 16-bit words on its 16-bit bus. coming from the AGCs or from the RCFs. When data is coming This means that I and Q data are interleaved and the IQ indica- from the RCFs (Bit 0 = 0), Bit 1 selects between two and four tor pin determines whether data on the port is I data or Q data. channel data mode. Bit 1 = 1 indicates that Link Port A When Bit 5 = 1, Parallel Port B is outputting an 8-bit I word and transmits RCF IQ words alternately from Channels 0 and 1. an 8-bit Q word at the same time, and the IQ indicator pins are When Bit 1 = 1, Link Port A outputs RCF IQ words from each high. of the four channels in succession: 0, 1, 2, 3. However, when AGC data is selected (Bit 0 = 1), Bit 1 selects the AGC data 0x1D: Link Port Control B output mode. In this mode, when Bit 1 = 1, Link Port A outputs Data is output through either a parallel port interface or a link AGC A IQ and gain words. With this mode, gain words must be port interface. The link port provides an efficient data link included by setting Bit 2 = 0. However, if Bit 0 = Bit 1 = 0, then between the AD6652 and a TigerSHARC DSP and can be AGC A and AGC B are alternately output on Link Port A and enabled by setting 0x1D, Bit 7 = 1. the inclusion or exclusion of the gain words is determined by Bit 2. Bit 0 selects which data is output on Link Port B. When Bit 0 = 0, Link Port B outputs data from the RCF according to Bit 2 determines if RSSI words are included or not in the data the format specified by Bit 1. When Bit 0 = 1, Link Port B output. If Bit 1 = 1, Bit 2 = 0. Because the RSSI words are only outputs the data from the AGCs according to the format two bytes long and the IQ words are four bytes long, the RSSI specified by Bits 1 and 2. words are padded with zeros to give a full 16-byte TigerSHARC quad-word. If AGC output is not selected (Bit 0 = 0), then this Bit 1 has two different meanings that depend on whether data is bit can be any value. coming from the AGCs or from the RCFs. When data is coming from the RCFs (Bit 0 = 0), Bit 1 selects between two and four Bits 6–3 specify the programmable delay value for Link Port A channel data mode. Bit 1 = 1 indicates that Link Port A between the time the link port receives a data ready from the transmits RCF IQ words alternately from Channels 0 and 1. receiver and the time it transmits the first data-word. The link When Bit 1 = 1, Link Port B outputs RCF IQ words from each port must wait at least 6 cycles of the receiver’s clock, so this of the four channels in succession: 0, 1, 2, 3. However, when value allows the user to use clocks of differing frequency and AGC data is selected (Bit 0 = 1), Bit 1 selects the AGC data phase for the AD6652 link port and the TigerSHARC link port. output mode. In this mode, when Bit 1 = 1, Link Port B outputs For details on the limitations and relationship of these clocks, AGC B IQ and gain words. With this mode, gain words must be see the Link Port section. included by setting Bit 2 = 0. However, if Bit 0 = Bit 1 = 0, then 0x1C: Parallel Port Control B AGC A and B are alternately output on Link Port B and the inclusion or exclusion of the gain words is determined by Bit 2. Data is output through either a parallel port interface or a link port interface. When 0x1D, Bit 7 = 0, the use of Link Port B is Bit 2 determines whether gain words are included in the data disabled and the use of Parallel Port B is enabled. The parallel output. If Bit 1 = 1, Bit 2 = 0. Because the gain words are only port provides different data modes for interfacing with DSPs or two bytes long and the IQ words are four bytes long, the gain FPGAs. words are padded with zeros to give a full 16-byte TigerSHARC quad-word. If AGC output is not selected (Bit 0 = 0), then this Bit 0 selects which data is output on Parallel Port B. When bit can be any value. Bit 0 = 0, Parallel Port B outputs data from the RCF according to the format specified by Bits 1–4. When Bit 0 = 1, Parallel Bits 6–3 specify the programmable delay value for Link Port B Port B outputs the data from the AGCs according to the format between the time the link port receives a data ready from the specified by Bits 1 and 2. receiver and the time it transmits the first data-word. The link port must wait at least six cycles of the receiver’s clock, so this In AGC mode, Bit 0 = 1 and Bit 1 determines if Parallel Port B is value allows the user to use clocks of differing frequency and able to output data from AGC A. Bit 2 determines if Parallel phase for the AD6652 link port and the TigerSHARC link port. Port B is able to output data from AGC B. The order of output For details on the limitations and relationship of these clocks, depends on the rate of triggers from each AGC, which in turn is see the Link Port section. determined by the decimation rate of the channels feeding it. In channel mode, Bit 0 = 0 and Bits 1–4 determine which Rev. 0 | Page 70 of 76

AD6652 0x1E: Port Clock Control Read/Write Chaining Bit 0 determines whether PCLK is supplied externally by the The microport of the AD6652 allows for multiple accesses while user or derived internally in the AD6652. If PCLK is derived CS is held low. (CS can be tied permanently low, if the micro- internally from CLK (Bit 0 = 1), it is output through the PCLK port is not shared with additional devices.) The user can access pin as a master clock. For most applications, PCLK is provided multiple locations by pulsing the WR or RD line and changing by the user as an input to the AD6652 via the PCLK pin. the contents of the external 3-bit address bus. External access to the external registers of Table 22 is accomplished in one of two Bits 2 and 1 allow the user to divide CLK by an integer value to modes using the CS, RD, WR, and MODE inputs. The access generate PCLK (00 = 1, 01 = 2, 10 = 4, 11 = 8). modes are Intel nonmultiplexed mode and Motorola nonmulti- MICROPORT CONTROL plexed mode. These modes are controlled by the MODE input (MODE = 0 for INM, MODE = 1 for MNM). CS, RD, and WR The AD6652 has an 8-bit microprocessor port or microport. The control the access type for each mode. microport interface is a multimode interface that is designed to give flexibility when dealing with the host processor. There are Intel Nonmultiplexed Mode (INM) two modes of bus operation: Intel nonmultiplexed mode (INM), MODE must be tied low to operate the AD6652 microprocessor and Motorola nonmultiplexed mode (MNM). The mode is in INM mode. The access type is controlled by the user with the selected based on the host processor and which mode is best CS, RD (DS), and WR (R/W) inputs. The RDY (DTACK) signal suited to that processor. The microport has an 8-bit data bus is produced by the microport to communicate to the user that (D[7:0]), 3-bit address bus (A[2:0]), 3 control pin lines (CS, DS, an access has been completed. RDY (DTACK) goes low at the or RD, R/W or WR), and one status pin (DTACK or RDY). The start of the access and is released when the internal cycle is functionality of the control signals and status line changes complete. See the timing diagrams for both the read and write slightly depending upon the mode that is chosen. modes in the DDC Timing Diagrams section. Write Sequencing Motorola Nonmultiplexed Mode (MNM) Writing to an internal location is achieved by first writing the MODE must be tied high to operate the AD6652 microproces- upper two bits of the address to Bits 1–0 of the ACR (Access sor in MNM mode. The access type is controlled by the user Control Register, External Address 7). Bits 7:2 can be set to with the CS, DS (RD), and R/W (WR) inputs. The DTACK select the channel, as indicated above. The CAR is then written (RDY) signal is produced by the microport to communicate to with the lower eight bits of the internal address (the CAR can be the user that an access has been completed. DTACK (RDY) goes written before the ACR, as long as both are written before the low when an internal access is complete and then returns high internal access). Data Register 2 (DR2) and Data Register 1 after DS (RD) is deasserted. See the timing diagrams for both (DR1) must be written first, because the write to Data Register the read and write modes in the DDC Timing Diagrams DR0 triggers the internal access. Data Register DR0 must always section. be the last register written to initiate the internal write. Microport Programming Overview Read Sequencing The AD6652 uses an indirect addressing scheme. The external Reading from the microport is accomplished in the same memory map (or external registers) is used to access the manner. The internal address is set up the same way as the internal memory maps that are made up of a channel memory write. A read from Data Register DR0 activates the internal map and an output port memory map. The 4-channel memory read; thus, Register DR0 must always be read first to initiate an pages are decoded using A[9:8] given in the External Memory internal read followed by DR1and DR2. This provides the Register 7 of the access control register (ACR). The output port 8 LSBs of the internal read through the microport (D[7:0]). register memory map is selected using Bit 5 of External Additional data registers can be read to read the balance of the Address 3 (sleep register). When this bit is written with a 0, the internal memory. channel memory map is selected; when this bit is 1, the output port memory map is selected. Rev. 0 | Page 71 of 76

AD6652 Internal Write Access Internal Read Access Up to 20 bits of data (as needed) can be written by the following A read is performed by first writing the channel address register process. Any high order bytes that are needed are written to the (CAR) and ACR as with a write. The data registers (DR2–DR0) corresponding data registers defined in the external memory are then read in the reverse order that they were written. First, map 3-bit address space. The least significant byte is then the least significant byte of the data (D[7:0]) is read from DR0. written to DR0 at Address (000). When a write to DR0 is On this transaction, the high bytes of the data are moved from detected, the internal microprocessor port state machine then the internal address pointed to by the CAR and ACR into the moves the data in DR2–DR0 to the internal address pointed to remaining data registers (DR2–DR1). This data can then be by the address in the channel address register (CAR) and access read from the data registers using the appropriate 3-bit control register (ACR). addresses. The number of data registers used depends solely on Write Pseudocode the amount of data to be read or written. Any unused bit in a void write_micro(ext_address, int data); data register should be masked out for a read. main(); Read Pseudocode { int read_micro(ext_address); /* This code shows the programming of the NCO phase offset register using the write_micro main(); function as defined above. The variable address is { the External Address A[2:0] and data is the value /* This code shows the reading of the first RCF to be placed in the external interface register. coefficient using the read_micro function as Internal Address = 0x087 defined above. The variable address is the */ External Address A[2..0]. // holding registers for NCO phase byte wide Internal Address = 0x000 access data */ int d1, d0; // holding registers for the coefficient // NCO frequency word (16 bits wide) int d2, d1, d0; NCO_PHASE = 0xCBEF; // coefficient (20-bits wide) // write ACR long coefficient; write_micro(7, 0x03 ); // write ACR // write CAR write_micro(7, 0x00 ); write_micro(6, 0x87); // write CAR // write DR1 with D[15:8] write_micro(6, 0x00); d1 = (NCO_PHASE & 0xFF00) >> 8; /* read D[7:0] from DR0, All data is moved from write_micro(1, d1); the internal registers to the interface registers // write DR0 with D[7:0] on this access */ // On this write all data is transferred to the d0 = read_micro(0) & 0xFF; internal address // read D[15:8] from DR1 d0 = NCO_FREQ & 0xFF; d1 = read_micro(1) & 0xFF; write_micro(0, d0); // read D[23:16] from DR2 } // end of main d2 = read_micro(2) & 0x0F; coefficient = d0 + (d1 << 8) + (d2 << 16); } // end of main Rev. 0 | Page 72 of 76

AD6652 APPLICATIONS AD6652 RECEIVER APPLICATIONS DESIGN GUIDELINES One CDMA2000 IF Carrier with No External Analog When designing the AD6652 into a system, it is recommended Filtering that, before starting design and layout, the designer become Code Division Multiple Access depends upon a unique code familiar with these guidelines, which discuss the special circuit sequence that modulates the IF carrier along with the payload connections and layout requirements required for certain pins. data. This permits multiple signals to be transmitted on the same carrier frequency and successfully separated at the 1. The following power-up sequence is recommended for the receiver. This technique spreads the spectrum of the initial AD6652. First, ensure that RESET is held logic low. Apply digital bit stream over a much wider bandwidth. The wideband AVDD (3.0 V) and VDD (2.5 V), allowing them both to nature and stringent adjacent channel-filtering requirements of settle to nominal values before applying VDDIO (3.3 V). CDMA2000 allow the AD6652 to process only one CDMA2000 Once VDDIO (3.3 V) has settled to nominal value, bring channel. To do this requires the processing power of all four RESET logic high. Last, apply a logic low RESET pulse for channels operating at maximum speed. 30 ns to reset the AD6652 into a known state ready for programming. Two CDMA2000 IF Carriers with External Analog Saw Filtering 2. RESET pin: The RESET pin must be held logic low during If two CDMA2000 carriers are to be processed by the AD6652, power-up sequencing to ensure that the internal logic starts prefiltering of the analog signal(s) going to the AD6652 is in a known state. Certain registers, noted in the datasheet, required. Surface acoustic wave (SAW) filters are commonly are cleared after hardware reset. Failure to ensure hardware used to reduce the digital signal processing required of the reset during power-up might result in invalid output until a AD6652 filters. This combination permits adequate reduction valid reset is applied. of the adjacent channel interference as specified for that medium and permits two CDMA2000 carriers to be processed 3. The number format used in this part is twos complement. using only two DDC channels per carrier. All input ports and output ports use twos complement data format. The formats for individual internal registers are Two UMTS or WCDMA IF Carriers with No External given in the memory map description of these registers. Analog Saw Filtering Due to less stringent filter requirements of wideband CDMA 4. To enhance microport programming, the DTACK (RDY) and UMTS, the AD6652 can receive two WCDMA carriers pin should be pulled high (to VDDIO) externally using a using the processing power of two channels for each carrier pull-up resister. The recommended value for the pull-up without the use of external analog filters. resistor is between 1 kΩ and 5 kΩ. Baseband I and Q Processor 5. CS pin is used as chip select for programming with the This application calls for baseband I and Q analog signals to be microport. It is recommended that the designer not tie this routed individually to the two AD6652 ADC inputs. The 12-bit pin low at all times. This pin should ideally be pulled high ADCs digitize the signals and send the data to all four receive using a pull-up resistor, and the user can pull it low processing channels for decimation and filtering. Therefore, whenever microport control is required. each channel is processing the same 12 bits of I data and 12 bits of Q data simultaneously. The user can shut down unused 6. The output parallel port has one clock cycle overhead for channels as desired. every output sample. So, if data from two AGCs with the same data rate are output on one output port in 16-bit Processing baseband I and Q data requires that each active interleaved I/Q mode along with the AGC word, then four channel’s NCO and quadrature mixer be bypassed by program- clock cycles are required for one sample from each ming of the NCO control registers. channel/AGC: one blank clock cycle, and one clock cycle each for I data, Q data, and gain data. Rev. 0 | Page 73 of 76

AD6652 9. To optimize ADC performance, decouple any system- 7. Serial port control and serial data output are not available induced noise from the sensitive ADC reference nodes. on this part. Place the 0.010 µF, 0.1 µF, and 10 µF external decoupling 8. Broadcast and programming multiple AD6652 parts using capacitors as close as possible to the AD6652 device’s VREF, the same microport control/data signals does not work for REFTA/REFBA, and REFTB/REFBB pins. See the ADC input/output port control registers (Addresses 0x00 to Voltage Reference section of the data sheet and the 0x1E). If two AD6652 parts have different values for evaluation board schematics, which are available on the input/output control registers, they cannot share the AD6652 product page at www.analog.com. HTU UTH microport bus (see the Microport Control section). Rev. 0 | Page 74 of 76

AD6652 AD6652 EVALUATION BOARD AND SOFTWARE The AD6652 evaluation board kit contains a fully populated Users can preview the evaluation board schematic, the software, AD6652 PCB, schematic diagrams, operating software, and the instruction manual on the product Web page of the comprehensive instruction manual, and digital filter design Analog Devices website. A block diagram of the basic software. components is shown in Figure 65. XTAL U201 OSCILLATOR J205 J206 J201 EXTERNAL CLK INPUT J101 6V POWER SUPPLY CONNECTOR J202 T201 INPUT A CLK CLK CLK 32kFIFO ANALOG AD6652 MICROPORT FPGA U501 INPUT CONTROL LINES U401 J203 U301 INPUT B U601 BUFFER T202 03 2 U PROM PC PARALLEL PRINTER PORT CONNECTOR (J601) J602 16-BIT PARALLEL OUTPUT PORT A J603 16-BIT PARALLEL OUTPUT PORT B J605P 8O-RBTIT B LINK J604P 8O-RBTIT A LINK 03198-0-056 Figure 65. Simplified Block Diagram of AD6652 PCB Rev. 0 | Page 75 of 76

AD6652 OUTLINE DIMENSIONS A1 CORNER 17.00 INDEX AREA BSC SQ 16 14 12 10 8 6 4 2 15 13 11 9 7 5 3 1 A BALL A1 B INDICATOR DC 15.00 BSC E F SQ G H 1.00 J BSC K L M N P R T TOP VIEW BOTTOM VIEW 1.31* DETAIL A 1.21 1.85* 1.10 1.71 1.40 0.50 0.30 0.70 0.20 MAX SEATING 0.60 COPLANARIT PLANE 0.50 BALL DIAMETER DETAIL A COMPLIANT TO JEDEC STANDARDS MO-192-AAF-1 EXCEPT FOR (*)DIMENSIONS Figure 66. 256-Lead Chip Scale Ball Grid Array [CSPBGA] (BC-256-2) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD6652BBC −40°C to +85°C 256-Lead CSPBGA (Chip Scale Ball Grid Array) BC-256-2 AD6652BC/PCB Evaluation Board with AD6652 and Software © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03198–0–7/04(0) Rev. 0 | Page 76 of 76

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