74LVC38A Quad 2-input NAND gate; open-drain Rev. 4 — 4 November 2011 Product data sheet 1. General description The 74LVC38A provides four 2-input NAND functions. The outputs are open-drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications. 2. Features and benefits  5 V tolerant inputs for interfacing with 5 V logic  Wide supply voltage range from 1.2V to5.5V  CMOS low power consumption  Direct interface with TTL levels  Open-drain outputs  Complies with JEDEC standard: JESD8-7A (1.65Vto1.95V JESD8-5A (2.3Vto2.7V JESD8-C/JESD36 (2.7Vto3.6V  ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115B exceeds 200V CDM JESD22-C101E exceeds 1000V  Specified from 40Cto+85Cand40Cto+125C 3. Ordering information Table 1. Ordering info rmation Type number Package Temperature range Name Description Version 74LVC38AD 40Cto+125C SO14 plastic small outline package; 14 leads; SOT108-1 bodywidth3.9mm 74LVC38ADB 40Cto+125C SSOP14 plastic shrink small outline package; 14 leads; SOT337-1 bodywidth 5.3mm 74LVC38APW 40Cto+125C TSSOP14 plastic thin shrink small outline package; 14 leads; SOT402-1 body width 4.4 mm 74LVC38ABQ 40Cto+125C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat package; no leads; 14 terminals; body2.5  3  0.85 mm

74LVC38A NXP Semiconductors Quad 2-input NAND gate; open-drain 4. Functional diagram 1 & 3 2 1 1A 1Y 3 4 2 1B & 6 5 4 2A 2Y 6 5 2B 9 9 3A & 8 3Y 8 10 10 3B 12 4A 12 4Y 11 & 11 13 4B 13 mna697 mna698 Fig 1. Logic symbol Fig 2. IEC logic symbol Y A B GND mna699 Fig 3. Logic diagram for one gate 5. Pinning information 5.1 Pinning 74LVC38A 74LVC38A terminal 1 A CC 1A 1 14 VCC index area 1 V 1B 2 13 4B 1B 2 1 14 13 4B 1Y 3 12 4A 1Y 3 12 4A 2A 4 11 4Y 2A 4 11 4Y 2B 5 GND(1) 10 3B 2B 5 10 3B 2Y 6 9 3A 2Y 6 9 3A 7 8 D Y GND 7 8 3Y N 3 001aad039 G 001aad038 Transparent top view (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 4. Pin configuration for SO14 and (T)SSOP14 Fig 5. Pin configuration for DHVQFN14 74LVC38A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 4 November 2011 2 of 15

74LVC38A NXP Semiconductors Quad 2-input NAND gate; open-drain 5.2 Pin description Table 2. Pin descripti on Symbol Pin Description 1A, 2A, 3A, 4A 1, 4, 9, 12 data input 1B, 2B, 3B, 4B 2, 5, 10, 13 data input 1Y, 2Y, 3Y, 4Y 3, 6, 8, 11 data output GND 7 ground (0V) V 14 supply voltage CC 6. Functional description Table 3. Function sel ection[1] Input Output nA nB nY L L Z L H Z H L Z H H L [1] H=HIGH voltage level; L=LOW voltage level; Z= high-impedance OFF-state 7. Limiting values Table 4. Limiting valu es In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V supply voltage 0.5 +6.5 V CC I input clamping current V < 0 50 - mA IK I V input voltage [1] 0.5 +6.5 V I I output clamping current V < 0 50 - mA OK O V output voltage active mode [2] 0.5 +6.5 V O high-impedance mode [2] 0.5 +6.5 V I output current V = 0 V to V - 50 mA O O CC I supply current - 100 mA CC I ground current 100 - mA GND T storage temperature 65 +150 C stg P total power dissipation T = 40 C to +125 C [3] - 500 mW tot amb [1] The minimum input voltage ratings may be exceeded if the input current ratings are observed. [2] The output voltage ratings may be exceeded if the output current ratings are observed. [3] For SO14 packages: above 70C the value of Ptotderates linearly with 8mW/K. For (T)SSOP14 packages: above 60C the value of Ptotderates linearly with 5.5mW/K. For DHVQFN14 packages: above 60C the value of Ptotderates linearly with 4.5mW/K. 74LVC38A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 4 November 2011 3 of 15

74LVC38A NXP Semiconductors Quad 2-input NAND gate; open-drain 8. Recommended operating conditions Table 5. Recommend ed operating conditions Symbol Parameter Conditions Min Typ Max Unit V supply voltage 1.65 - 5.5 V CC functional 1.2 - - V V input voltage 0 - 5.5 V I V output voltage active mode 0 - V V O CC high-impedance mode 0 - 5.5 V T ambient temperature in free air 40 - +125 C amb t/V input transition rise and fall V = 1.65 V to 2.7 V 0 - 20 ns/V CC rate V = 2.7 V to 3.6 V 0 - 10 ns/V CC 9. Static characteristics Table 6. Static charac teristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ[1] Max Min Max V HIGH-level V = 1.2 V 1.08 - - 1.08 - V IH CC input voltage V = 1.65 V to 1.95 V 0.65  V - - 0.65  V - V CC CC CC V = 2.3 V to 2.7 V 1.7 - - 1.7 - V CC V = 2.7 V to 3.6 V 2.0 - - 2.0 - V CC V = 4.5 V to 5.5 V 0.7  V - - 0.7  V - V CC CC CC V LOW-level input V = 1.2 V - - 0.12 - 0.12 V IL CC voltage V = 1.65 V to 1.95 V - - 0.35  V - 0.35  V V CC CC CC V = 2.3 V to 2.7 V - - 0.7 - 0.7 V CC V = 2.7 V to 3.6 V - - 0.8 - 0.8 V CC V = 4.5 V to 5.5 V - - 0.30  V - 0.30  V V CC CC CC V LOW-level V =V orV OL I IH IL output voltage I =100A; - - 0.20 - 0.3 V O V =1.65Vto5.5 V CC I =4mA; V = 1.65 V - - 0.45 - 0.65 V O CC I =8mA; V = 2.3V - - 0.6 - 0.8 V O CC I =12mA; V = 2.7 V - - 0.4 - 0.6 V O CC I =24mA; V = 3.0 V - - 0.55 - 0.8 V O CC I =32mA; V = 4.5 V - - 0.55 - 0.8 V O CC I input leakage V =5.5VorGND; - 0.1 5 - 20 A I I current V =1.65 Vto5.5 V CC I OFF-state V =V ; V = 5.5V or GND; - 0.1 5 - 20 A OZ I IH O output current V =1.65V to 5.5 V CC I power-off V orV =5.5V; V =0V - 0.1 10 - 20 A OFF I O CC leakage current 74LVC38A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 4 November 2011 4 of 15

74LVC38A NXP Semiconductors Quad 2-input NAND gate; open-drain Table 6. Static characteristics …continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ[1] Max Min Max I supply current V =V orGND; I =0A; - 0.1 10 - 40 A CC I CC O V = 5.5 V CC I additional per input pin; - 5 500 - 5000 A CC supply current V =V 0.6V; I =0A; I CC O V =2.7Vto5.5 V CC C input V =0 V to 5.5V; - 4.0 - - - pF I CC capacitance V =GNDtoV I CC [1] All typical values are measured at VCC=3.3V (unless stated otherwise) and Tamb=25C. 10. Dynamic characteristics Table 7. Dynamic cha racteristics Voltages are referenced to GND (ground=0V). For test circuit see Figure7. Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ[1] Max Min Max t OFF-state to LOW nA, nB to nY; see Figure6 PZL propagation delay V = 1.2 V - 5.7 - - - ns CC V = 1.65 V to 1.95 V 1.0 2.6 6.0 1.0 6.9 ns CC V = 2.3 V to 2.7 V 0.5 1.8 3.3 0.5 3.8 ns CC V = 2.7 V 0.5 1.7 2.9 0.5 4.0 ns CC V = 3.0 V to 3.6 V 0.5 1.8 3.0 0.5 4.0 ns CC t LOW to OFF-state nA, nB to nY; see Figure6 PLZ propagation delay V = 1.2 V - 5.7 - - - ns CC V = 1.65 V to 1.95 V 1.0 2.7 6.0 1.0 6.9 ns CC V = 2.3 V to 2.7 V 0.5 1.5 3.3 0.5 3.8 ns CC V = 2.7 V 1.0 2.6 3.8 1.0 5.0 ns CC V = 3.0 V to 3.6 V 1.0 2.3 3.6 1.0 4.5 ns CC t output skew time [2] - - 1.0 - 1.5 ns sk(o) 74LVC38A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 4 November 2011 5 of 15

74LVC38A NXP Semiconductors Quad 2-input NAND gate; open-drain Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground=0V). For test circuit see Figure7. Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ[1] Max Min Max C power dissipation per gate; V =GNDtoV [3] PD I CC capacitance V = 1.65 V to 1.95 V - 6.2 - - - pF CC V = 2.3 V to 2.7 V - 9.7 - - - pF CC V = 3.0 V to 3.6 V - 12.9 - - - pF CC [1] Typical values are measured at Tamb=25C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively. [2] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. [3] CPDis used to determine the dynamic power dissipation (PDinW). PD=CPDVCC2fiN+(CLVCC2fo)where: f = input frequency in MHz; f =output frequency in MHz i o C =output load capacitance inpF L V =supply voltage in Volts CC N= number of inputs switching (CLVCC2fo)=sum of the outputs 11. AC waveforms VI nA, nB input VM GND tPLZ tPZL VCC nY output VM VOL VX mna700 Measurement points are given in Table8 V is a typical output voltage level that occurs with the output load. OL Fig 6. The input nA, nB to output nY propagation delays Table 8. Measuremen t points Supply voltage Input Output V V V CC M X <2.7 V 0.5  V V + 0.15 V CC OL 2.7 V to 3.6 V 1.5 V V + 0.3 V OL 74LVC38A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 4 November 2011 6 of 15

74LVC38A NXP Semiconductors Quad 2-input NAND gate; open-drain tW VI 90 % negative pulse VM VM 10 % 0 V tf tr tr tf VI 90 % positive pulse VM VM 10 % 0 V tW VEXT VCC RL VI VO G DUT RT CL RL 001aae331 Test data is given in Table9. Definitions for test circuit: RL = Load resistance. C = Load capacitance including jig and probe capacitance. L RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 7. Test circuit for measuring switching times Table 9. Test data Supply voltage Input Load V EXT V t, t C R t , t t , t I r f L L PLH PHL PLZ PZL 1.2V V  2 ns 30pF 1 k open 2  V CC CC 1.65Vto1.95V V  2 ns 30pF 1 k open 2  V CC CC 2.3Vto2.7V V  2 ns 30pF 500 open 2  V CC CC 2.7V 2.7V  2.5ns 50pF 500 open 2  V CC 3.0Vto3.6V 2.7V  2.5ns 50pF 500 open 2  V CC 74LVC38A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 4 November 2011 7 of 15

74LVC38A NXP Semiconductors Quad 2-input NAND gate; open-drain 12. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 14 8 Q A2 A1 (A 3 ) A pin 1 index θ Lp 1 7 L e w M detail X bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mAax. A1 A2 A3 bp c D(1) E(1) e HE L Lp Q v w y Z(1) θ 0.25 1.45 0.49 0.25 8.75 4.0 6.2 1.0 0.7 0.7 mm 1.75 0.25 1.27 1.05 0.25 0.25 0.1 0.10 1.25 0.36 0.19 8.55 3.8 5.8 0.4 0.6 0.3 8o 0.010 0.057 0.019 0.0100 0.35 0.16 0.244 0.039 0.028 0.028 0o inches 0.069 0.01 0.05 0.041 0.01 0.01 0.004 0.004 0.049 0.014 0.0075 0.34 0.15 0.228 0.016 0.024 0.012 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT108-1 076E06 MS-012 03-02-19 Fig 8. Package outline SOT108-1 (SO14) 74LVC38A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 4 November 2011 8 of 15

74LVC38A NXP Semiconductors Quad 2-input NAND gate; open-drain SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 D E A X c y HE v M A Z 14 8 Q A2 A1 (A 3 ) A pin 1 index θ Lp L 1 7 detail X w M e bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mAax. A1 A2 A3 bp c D(1) E(1) e HE L Lp Q v w y Z(1) θ mm 2 00..2015 11..8605 0.25 00..3285 00..2009 66..40 55..42 0.65 77..96 1.25 10..0633 00..97 0.2 0.13 0.1 10..49 80oo Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT337-1 MO-150 03-02-19 Fig 9. Package outline SOT337-1 (SSOP14) 74LVC38A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 4 November 2011 9 of 15

74LVC38A NXP Semiconductors Quad 2-input NAND gate; open-drain TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 D E A X c y HE v M A Z 14 8 Q A2 (A 3 ) A pin 1 index A1 θ Lp L 1 7 detail X w M e bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mAax. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ mm 1.1 00..1055 00..9850 0.25 00..3109 00..21 54..19 44..53 0.65 66..62 1 00..7550 00..43 0.2 0.13 0.1 00..7328 80oo Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT402-1 MO-153 03-02-18 Fig 10. Package outline SOT402-1 (TSSOP14) 74LVC38A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 4 November 2011 10 of 15

74LVC38A NXP Semiconductors Quad 2-input NAND gate; open-drain DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm SOT762-1 D B A A A1 E c terminal 1 detail X index area terminal 1 e1 C index area e b v M C A B y1 C y w M C 2 6 L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) A(1) UNIT max. A1 b c D(1) Dh E(1) Eh e e1 L v w y y1 0.05 0.30 3.1 1.65 2.6 1.15 0.5 mm 1 0.2 0.5 2 0.1 0.05 0.05 0.1 0.00 0.18 2.9 1.35 2.4 0.85 0.3 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 02-10-17 SOT762-1 - - - MO-241 - - - 03-01-27 Fig 11. Package outline SOT762-1 (DHVQFN14) 74LVC38A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 4 November 2011 11 of 15

74LVC38A NXP Semiconductors Quad 2-input NAND gate; open-drain 13. Abbreviations Table 10. Abbreviation s Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history T able 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC38A v.4 20111104 Product data sheet - 74LVC38A v.3 Modifications: • The format of this document has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Table4, Table5, Table6, Table7 and Table8: values added for lower voltage ranges. 74LVC38A v.3 20040322 Product specification - 74LVC38A v.2 74LVC38A v.2 20040310 Product specification - 74LVC38A v.1 74LVC38A v.1 20020408 - - - 74LVC38A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 4 November 2011 12 of 15

74LVC38A NXP Semiconductors Quad 2-input NAND gate; open-drain 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. 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This document supersedes and replaces all information supplied prior conveyance or implication of any license under any copyrights, patents or to the publication hereof. other industrial or intellectual property rights. Suitability for use — NXP Semiconductors products are not designed, Export control — This document as well as the item(s) described herein authorized or warranted to be suitable for use in life support, life-critical or may be subject to export control regulations. Export might require a prior safety-critical systems or equipment, nor in applications where failure or authorization from competent authorities. 74LVC38A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 4 November 2011 13 of 15

74LVC38A NXP Semiconductors Quad 2-input NAND gate; open-drain Non-automotive qualified products — Unless this data sheet expressly NXP Semiconductors’ specifications such use shall be solely at customer’s states that this specific NXP Semiconductors product is automotive qualified, own risk, and (c) customer fully indemnifies NXP Semiconductors for any the product is not suitable for automotive use. It is neither qualified nor tested liability, damages or failed product claims resulting from customer design and in accordance with automotive testing or application requirements. NXP use of the product for automotive applications beyond NXP Semiconductors’ Semiconductors accepts no liability for inclusion and/or use of standard warranty and NXP Semiconductors’ product specifications. non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in 15.4 Trademarks automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the Notice: All referenced brands, product names, service names and trademarks product for such automotive applications, use and specifications, and (b) are the property of their respective owners. whenever customer uses the product for automotive applications beyond 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74LVC38A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 4 November 2011 14 of 15

74LVC38A NXP Semiconductors Quad 2-input NAND gate; open-drain 17. Contents 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 3 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 Recommended operating conditions. . . . . . . . 4 9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 10 Dynamic characteristics. . . . . . . . . . . . . . . . . . 5 11 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 6 12 Package outline. . . . . . . . . . . . . . . . . . . . . . . . . 8 13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 12 14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13 15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13 15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 13 15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14 16 Contact information. . . . . . . . . . . . . . . . . . . . . 14 17 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 4 November 2011 Document identifier: 74LVC38A