74LCX74 LOW VOLTAGE CMOS DUAL D-TYPE FLIP FLOP WITH 5V TOLERANT INPUTS n 5V TOLERANT INPUTS n HIGH SPEED : f = 150 MHz (MAX.) at V = 3V MAX CC n POWER DOWN PROTECTION ON INPUTS AND OUTPUTS n SYMMETRICAL OUTPUT IMPEDANCE: |I | = I = 24mA (MIN) at V = 3V SOP TSSOP OH OL CC n PCI BUS LEVELS GUARANTEED AT 24 mA n BALANCED PROPAGATION DELAYS: t @ t ORDER CODES PLH PHL n OPERATING VOLTAGE RANGE: PACKAGE TUBE T & R V (OPR) = 2.0V to 3.6V (1.5V Data CC SOP 74LCX74M 74LCX74MTR Retention) TSSOP 74LCX74TTR n PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 74 n LATCH-UP PERFORMANCE EXCEEDS A signal on the D INPUT is transferred to the Q 500mA (JESD 17) OUTPUT during the positive going transition of the n ESD PERFORMANCE: clock pulse. HBM > 2000V (MIL STD 883 method 3015); CLR and PR are independent of the clock and MM > 200V accomplished by a low setting on the appropriate input. DESCRIPTION It has same speed performance at 3.3V than 5V The 74LCX74 is a low voltage CMOS DUAL AC/ACT family, combined with a lower power D-TYPE FLIP FLOP WITH PRESET AND CLEAR consumption. NON INVERTING fabricated with sub-micron All inputs and outputs are equipped with silicon gate and double-layer metal wiring C2MOS protection circuits against static discharge, giving technology. It is ideal for low power and high them 2KV ESD immunity and transient excess speed 3.3V applications; it can be interfaced to 5V voltage. signal environment for inputs. PIN CONNECTION AND IEC LOGIC SYMBOLS September 2001 1/11

74LCX74 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 1, 13 1CLR, 2CLR Asynchronous Reset - Direct Input 2, 12 1D, 2D Data Inputs 3, 11 1CK, 2CK Clock Input (LOW to HIGH, Edge Triggered) 4, 10 1PR, 2PR Asynchronous Set - Direct Input 5, 9 1Q, 2Q True Flip-Flop Outputs 6, 8 1Q, 2Q Complement Flip-Flop Outputs 7 GND Ground (0V) 14 VCC Positive Supply Voltage TRUTH TABLE INPUTS OUTPUTS FUNCTION CLR PR D CK Q Q L H X X L H CLEAR H L X X H L PRESET L L X X H H H H L L H H H H H L H H X Qn Qn NO CHANGE X : Don’t Care 2/11

74LCX74 LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VCC Supply Voltage -0.5 to +7.0 V VI DC Input Voltage -0.5 to +7.0 V VO DC Output Voltage (VCC = 0V) -0.5 to +7.0 V VO DC Output Voltage (High or Low State) (note 1) -0.5 to VCC + 0.5 V IIK DC Input Diode Current - 50 mA IOK DC Output Diode Current (note 2) - 50 mA IO DC Output Current – 50 mA ICC DC Supply Current per Supply Pin – 100 mA IGND DC Ground Current per Supply Pin – 100 mA Tstg Storage Temperature -65 to +150 °C TL Lead Temperature (10 sec) 300 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied 1) I absolute maximum rating must be observed O 2) V < GND O RECOMMENDED OPERATING CONDITIONS Symbol Parameter Value Unit VCC Supply Voltage (note 1) 2.0 to 3.6 V VI Input Voltage 0 to 5.5 V VO Output Voltage (VCC = 0V) 0 to 5.5 V VO Output Voltage (High or Low State) 0 to VCC V IOH, IOL High or Low Level Output Current (VCC = 3.0 to 3.6V) – 24 mA IOH, IOL High or Low Level Output Current (VCC = 2.7V) – 12 mA Top Operating Temperature -55 to 125 °C dt/dv Input Rise and Fall Time (note 2) 0 to 10 ns/V 1) Truth Table guaranteed: 1.5V to 3.6V 2) V from 0.8V to 2V at V = 3.0V IN CC 3/11

74LCX74 DC SPECIFICATIONS Test Condition Value Symbol Parameter -40 to 85 °C -55 to 125 °C Unit V CC (V) Min. Max. Min. Max. V High Level Input IH 2.0 2.0 V Voltage 2.7 to 3.6 V Low Level Input IL 0.8 0.8 V Voltage VOH High Level Output 2.7 to 3.6 IO=-100 m A VCC-0.2 VCC-0.2 Voltage 2.7 IO=-12 mA 2.2 2.2 V IO=-18 mA 2.4 2.4 3.0 IO=-24 mA 2.2 2.2 VOL Low Level Output 2.7 to 3.6 IO=100 m A 0.2 0.2 Voltage 2.7 IO=12 mA 0.4 0.4 V IO=16 mA 0.4 0.4 3.0 IO=24 mA 0.55 0.55 I Input Leakage I Current 2.7 to 3.6 VI = 0 to 5.5V – 5 – 5 m A I Power Off Leakage off Current 0 VI or VO = 5.5V 10 10 m A ICC QCuurieresnctent Supply 2.7 to 3.6 VI = VCC or GND 10 10 m A VI or VO= 3.6 to 5.5V – 10 – 10 D ICC ICC incr. per Input 2.7 to 3.6 VIH = VCC - 0.6V 500 500 m A DYNAMIC SWITCHING CHARACTERISTICS Test Condition Value Symbol Parameter V TA = 25 °C Unit CC (V) Min. Typ. Max. VVOOLLPV DOyuntpaumt i(cn Lootew 1 L)evel Quiet 3.3 VIL =C 0LV =, V5I0Hp =F 3.3V -00..88 V 1) Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is measured in the LOW state. 4/11

74LCX74 AC ELECTRICAL CHARACTERISTICS Test Condition Value Symbol Parameter -40 to 85 °C -55 to 125 °C Unit V C R t = t CC L L s r (V) (pF) (W ) (ns) Min. Max. Min. Max. t t Propagation Delay 2.7 1.5 8.0 1.5 9.2 PLH PHL 50 500 2.5 ns Time (CK to Q or Q) 3.0 to 3.6 1.5 7.0 1.5 8.0 t t Propagation Delay 2.7 1.5 8.0 1.5 9.2 PLH PHL Time (PR or CLR to 50 500 2.5 ns 3.0 to 3.6 1.5 7.0 1.5 8.0 Q or Q) t Setup Time, HIGH or 2.7 2.5 3.5 S 50 500 2.5 ns LOW level D to CK 3.0 to 3.6 2.5 3.5 t Hold Time, HIGH or 2.7 1.5 1.5 h 50 500 2.5 ns LOW level D to CK 3.0 to 3.6 1.5 1.5 t CK Pulse Width, 2.7 3.0 4.0 W HIGH or LOW 50 500 2.5 ns PR or CLR Pulse 3.0 to 3.6 3.0 4.0 Width, LOW t Recovery Time PR 2.7 0 0 rec 50 500 2.5 ns or CLR to CK 3.0 to 3.6 0 0 f Clock Pulse MAX 2.7 50 500 2.5 150 150 MHz Frequency t Output To Output 3.0 to 3.6 50 500 2.5 1.0 1.0 ns OSLH t Skew Time (note1, OSHL 2) 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch- ing in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|) 2) Parameter guaranteed by design CAPACITIVE CHARACTERISTICS Test Condition Value Symbol Parameter V TA = 25 °C Unit CC (V) Min. Typ. Max. CIN Input Capacitance 3.3 VIN = 0 to VCC 6 pF C Power Dissipation Capacitance 3.3 f = 10MHz 40 PD IN pF (note 1) V = 0 or V IN CC 1) C is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without PD load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I = C x V x f + I /2 (per CC(opr) PD CC IN CC Flip-Flop) 5/11

74LCX74 TEST CIRCUIT C = 50 pF or equivalent (includes jig and probe capacitance) RL = 500W or equivalent RL = Z of pulse generator (typically 50W ) T OUT WAVEFORM 1 : PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) 6/11

74LCX74 WAVEFORM 2 : PROPAGATION DELAYS (f=1MHz; 50% duty cycle) 7/11

74LCX74 WAVEFORM 3 : RECOVERY TIMES (f=1MHz; 50% duty cycle) WAVEFORM 4 : PULSE WIDTH (f=1MHz; 50% duty cycle) 8/11

74LCX74 SO-14 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. MIN. TYP. MAX. A 1.75 0.068 a1 0.1 0.2 0.003 0.007 a2 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45° (typ.) D 8.55 8.75 0.336 0.344 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 7.62 0.300 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M 0.68 0.026 S 8° (max.) PO13G 9/11

74LCX74 TSSOP14 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. MIN. TYP. MAX. A 1.2 0.047 A1 0.05 0.15 0.002 0.004 0.006 A2 0.8 1 1.05 0.031 0.039 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 D 4.9 5 5.1 0.193 0.197 0.201 E 6.2 6.4 6.6 0.244 0.252 0.260 E1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 BSC 0.0256 BSC K 0° 8° 0° 8° L 0.45 0.60 0.75 0.018 0.024 0.030 A A2 K L A1 b e c E D E1 PIN 1 IDENTIFICATION 1 0080337D 10/11

74LCX74 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2000 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom © http://www.st.com 11/11