Is Now Part of To learn more about ON Semiconductor, please visit our website at www.onsemi.com Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor product management systems do not have the ability to manage part nomenclature that utilizes an underscore (_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated device numbers. The most current and up-to-date ordering information can be found at www.onsemi.com. Please email any questions regarding the system integration to Fairchild_questions@onsemi.com. ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

7 4 L C X December 2013 5 7 3 — 74LCX573 L o Low Voltage Octal Latch with 5V Tolerant w V o Inputs and Outputs l t a g e Features General Description O c ■ 5V tolerant inputs and outputs The LCX573 is a high-speed octal latch with buffered t a ■ 2.3V–3.6V VCC specifications provided common Latch Enable (LE) and buffered common Out- l L ■ 7.0 ns t max. (V = 3.3V), 10µA I max. put Enable (OE) input. a PD CC CC t ■ Power down high impedance inputs and outputs The LCX573 is functionally identical to the LCX373 but ch ■ Supports live insertion/withdrawal(1) has inputs and outputs on opposite sides. w ■ ±24mA output drive (V = 3.0V) The LCX573 is designed for low voltage applications it CC h ■ Implements proprietary noise/EMI reduction circuitry with capability of interfacing to a 5V signal environment. 5 The LCX573 is fabricated with an advanced CMOS V ■ Latch-up performance exceeds JEDEC 78 conditions tech- nology to achieve high speed operation while T ■ ESD performance o maintaining CMOS low power dissipation. l – Human body model > 2000V e r a – Machine model > 200V n t ■ Leadless DQFN package I n p Note: u t s 1. To ensure the high impedance state during power up a or down, OE should be tied to VCC through a pull-up n resistor: the minimum value of the resistor is d determined by the current-sourcing capability of the O u driver. t p u t s Ordering Information Order Package Number Number Package Description 74LCX573WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LCX573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LCX573BQX(2) MLP20B 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm 74LCX573MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 74LCX573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Note: 2. DQFN package available in Tape and Reel only. Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX573 Rev. 1.6.1

7 4 Connection Diagrams Logic Symbol L C X Pin Assignments for 5 SOIC, SOP, SSOP, TSSOP 7 D0D1D2D3D4D5D6D7 3 LE — ODDE10 123 211098 VOOC10C OEO0O1O2O3O4O5O6O7 Low D2 4 17 O2 V D3 5 16 O3 o D4 6 15 O4 Truth Table lta D5 7 14 O5 g D6 8 13 O6 Inputs Outputs e O D7 9 12 O7 OE LE D O n c GND 10 11 LE t L H H H a l Pad Assignments for DQFN L L H L L a OE VCC L L X O tc 1 20 0 h D0 2 19 O0 H X X Z w i D1 3 18 O1 H = HIGH Voltage th D2 4 17 O2 L = LOW Voltage 5V D3 5 16 O3 Z = High Impedance T o D4 6 15 O4 X = Immaterial le r D5 7 14 O5 O0 = Previous O0 before HIGH-to-LOW transition of a n Latch Enable D6 8 13 O6 t I n D7 9 12 O7 p Functional Description u 10 11 t GND LE The LCX573 contains eight D-type latches with 3-STATE s (Top View) (Bottom View) output buffers. When the Latch Enable (LE) input is an HIGH, data on the D inputs enters the latches. In this d Pin Descriptions n condition the latches are transparent, i.e., a latch output O u Pin Names Description will change state each time its D input changes. When t LE is LOW the latches store the information that was p D –D Data Inputs u 0 7 present on the D inputs a setup time preceding the t s LE Latch Enable Input HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is OE 3-STATE Output Enable Input LOW, the buffers are enabled. When OE is HIGH the O0–O7 3-STATE Latch Outputs buffers are in the high impedance mode but this does not DAP No Connect interfere with entering new data into the latches. Note: DAP (Die Attach Pad) Logic Diagram D0 D1 D2 D3 D4 D5 D6 D7 D D D D D D D D Q Q Q Q Q Q Q Q LE LE LE LE LE LE LE LE LE OE O0 O1 O2 O3 O4 O5 O6 O7 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX573 Rev. 1.6.1 2

7 4 Absolute Maximum Ratings L C Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be X 5 operable above the recommended operating conditions and stressing the parts to these levels is not recommended. 7 In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. 3 The absolute maximum ratings are stress ratings only. — L Symbol Parameter Conditions Value Units o w VCC Supply Voltage –0.5 to +7.0 V V V DC Input Voltage –0.5 to +7.0 V o I l t a V DC Output Voltage Output in 3-STATE –0.5 to +7.0 V O g Output in HIGH or LOW State(3) –0.5 to VCC + 0.5 e O I DC Input Diode Current V < GND –50 mA c IK I t IOK DC Output Diode Current VO < GND –50 mA al L VO > VCC +50 a t I DC Output Source/Sink Current ±50 mA c O h I DC Supply Current per Supply Pin ±100 mA w CC i IGND DC Ground Current per Ground Pin ±100 mA th 5 T Storage Temperature –65 to +150 °C STG V T o l Recommended Operating Conditions(4) er a The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended n t operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not I n recommend exceeding them or designing to absolute maximum ratings. p u Symbol Parameter Conditions Min. Max. Units ts a V Supply Voltage Operating 2.0 3.6 V CC n d Data Retention 1.5 3.6 O VI Input Voltage 0 5.5 V u t V Output Voltage HIGH or LOW State 0 V V p O CC u t 3-STATE 0 5.5 s I /I Output Current V = 3.0V–3.6V ±24 mA OH OL CC V = 2.7V–3.0V ±12 CC V = 2.3V–2.7V ±8 CC T Free-Air Operating Temperature –40 85 °C A ∆t/∆V Input Edge Rate V = 0.8V–2.0V, V = 3.0V 0 10 ns/V IN CC Notes: 3. I Absolute Maximum Rating must be observed. O 4. Unused inputs must be held HIGH or LOW. They may not float. ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX573 Rev. 1.6.1 3

7 4 DC Electrical Characteristics L C X TA = –40°C to +85°C 5 7 Symbol Parameter V (V) Conditions Min. Max. Units 3 CC — V HIGH Level Input Voltage 2.3–2.7 1.7 V IH L 2.7–3.6 2.0 o w VIL LOW Level Input Voltage 2.3–2.7 0.7 V V o 2.7–3.6 0.8 l t a VOH HIGH Level Output 2.3–3.6 IOH = –100µA VCC – 0.2 V g Voltage e 2.3 IOH = –8mA 1.8 O 2.7 I = –12mA 2.2 c OH t a 3.0 IOH = –18mA 2.4 l L I = –24mA 2.2 a OH t c VOL LOW Level Output 2.3–3.6 IOL = 100µA 0.2 V h Voltage 2.3 I = 8mA 0.6 w OL i t 2.7 I = 12mA 0.4 h OL 5 3.0 IOL = 16mA 0.4 V I = 24mA 0.55 T OL o I Input Leakage Current 2.3–3.6 0 ≤ V ≤ 5.5V ±5.0 µA le I I r IOZ 3-STATE Output Leakage 2.3–3.6 0 ≤ VO ≤ 5.5V, VI = VIH or VIL ±5.0 µA an t IOFF Power-Off Leakage Current 0 VI or VO = 5.5V 10 µA In I Quiescent Supply Current 2.3–3.6 V = V or GND 10 µA p CC I CC u 3.6V ≤ VI, VO ≤ 5.5V(5) ±10 ts ∆I Increase in I per Input 2.3–3.6 V = V –0.6V 500 µA a CC CC IH CC n d O u AC Electrical Characteristics t p u TA = –40°C to +85°C, RL = 500Ω ts V = 3.3V ± 0.3V, V = 2.7V, V = 2.5 ± 0.2V, CC CC CC C = 50pF C = 50pF C = 30pF L L L Symbol Parameter Min. Max. Min. Max. Min. Max. Units t , t Propagation Delay, D to O 1.5 8.0 1.5 9.0 1.5 9.6 ns PHL PLH n n t , t Propagation Delay, LE to O 1.5 8.5 1.5 9.5 1.5 10.5 ns PHL PLH n t , t Output Enable Time 1.5 8.5 1.5 9.5 1.5 10.5 ns PZL PZH t , t Output Disable Time 1.5 6.5 1.5 7.0 1.5 7.8 ns PLZ PHZ t Setup Time, D to LE 2.5 2.5 4.0 ns S n t Hold Time, D to LE 1.5 1.5 2.0 ns H n t LE Pulse Width 3.3 3.3 4.0 ns W t , t Output to Output Skew(6) 1.0 ns OSHL OSLH Notes: 5. Outputs disabled or 3-STATE only. 6. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t ) or LOW-to-HIGH (t ). OSHL OSLH ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX573 Rev. 1.6.1 4

7 4 Dynamic Switching Characteristics L C X T = 25°C 5 A 7 3 Symbol Parameter V (V) Conditions Typical Units CC — VOLP Quiet Output Dynamic Peak VOL 3.3 CL = 50pF, VIH = 3.3V, VIL = 0V 0.8 V L 2.5 C = 30pF, V = 2.5V, V = 0V 0.6 o L IH IL w VOLV Quiet Output Dynamic Valley VOL 3.3 CL = 50pF, VIH = 3.3V, VIL = 0V –0.8 V V o 2.5 CL = 30pF, VIH = 2.5V, VIL = 0V –0.6 lt a g e Capacitance O c t a Symbol Parameter Conditions Typical Units l L C Input Capacitance V = Open, V = 0V or V 7 pF a IN CC I CC t c COUT Output Capacitance VCC = 3.3V, VI = 0V or VCC 8 pF h C Power Dissipation Capacitance V = 3.3V, V = 0V or V , f = 10 MHz 25 pF w PD CC I CC i t h 5 V T o l e r a n t I n p u t s a n d O u t p u t s ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX573 Rev. 1.6.1 5

7 4 AC Loading and Waveforms (Generic for LCX Family) LC X VCC 5 500Ω OPEN tPLH, tPHL 7 SIGTENSATL DUT GND tPZH, tPHZ 3 — VI tPZL, tPLZ L CL 500Ω o w V o l Figure 1. AC Test Circuit (C includes probe and jig capacitance) t L a g e Test Switch O c tPLH, tPHL Open t a tPZL, tPLZ 6V at VCC = 3.3 ± 0.3V l L VCC x 2 at VCC = 2.5 ± 0.2V a t t , t GND c PZH PHZ h w i DATINA Vmi VGCNCD COONUTTRPOUTL Vmi VGCNCD th 5 tpxx tpxx tPZH tPHZ V DOAUTAT Vmo DOAUTAT Vmo VVOYH To l e r Waveform for Inverting and 3-STATE Output High Enable and a n Non-Inverting Functions Disable Times for Logic t I n COCNLTORCOINKL tW treVcmiVmi VGCNCD CONINTDRPAOUTITLNA tS VtHmi Vmi VGVGCCNNCCDD puts and tPHL tPLH MR tS trec Ou OUTPUT Vmo Vmo CLEOARR Vmi tp u t Propagation Delay, Pulse Width and Setup Time, Hold Time and s t Waveforms Recovery Time for Logic rec OUTPUT VCC tr tf CONTROL Vmi GND tPZL tPLZ VOH ANY 90% 90% DOAUTAT Vmo VX OUTPUT 10% 10% VOL VOL 3-STATE Output Low Enable and t and t rise fall Disable Times for Logic Figure 2. Waveforms (Input Characteristics; f = 1MHz, t = t = 3ns) r f V CC Symbol 3.3V ± 0.3V 2.7V 2.5V ± 0.2V V 1.5V 1.5V V / 2 mi CC V 1.5V 1.5V V / 2 mo CC V V + 0.3V V + 0.3V V + 0.15V x OL OL OL V V – 0.3V V – 0.3V V – 0.15V y OH OH OH ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX573 Rev. 1.6.1 6

7 4 Schematic Diagram (Generic for LCX Family) LC X Input Stage 5 7 3 — L o P2 w V P1 o l VCC ta g e O Data c t ESD a P5 X1 l D2 N+/P– L VDD a N1 N2 t c h w GTO™ Output i Input Stage th P4 D6 5 V N+/P– T o l e r a n P3 t I n N5 p u t s Enable N4 a n ESD d D4 N+/P– O N3 u t p u t s ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX573 Rev. 1.6.1 7

7 4 Tape and Reel Specification L C X Tape Format for DQFN 5 7 Package Tape Number Cavity Cover Tape 3 — Designator Section Cavities Status Status L BQX Leader (Start End) 125 (typ) Empty Sealed o w Carrier 3000 Filled Sealed V Trailer (Hub End) 75 (typ) Empty Sealed o l t a Tape Dimensions inches (millimeters) g e O c t a l L a t c h w i t h 5 V T o l e r a n t I n p u t s a n d O u t p u t s Reel Dimensions inches (millimeters) Tape Size A B C D N W1 W2 12mm 13.0 (330.0) 0.059 (1.50) 0.512 (13.00) 0.795 (20.20) 2.165 (55.00) 0.488 (12.4) 0.724 (18.4) ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX573 Rev. 1.6.1 8

7 4 Physical Dimensions L C X 5 13.00 7 12.60 3 A — 11.43 L 20 11 o B w V o l t a 9.50 g e 10.65 7.60 10.00 7.40 O c t 2.25 a l L a t c h 1 10 0.65 PINONE 0.51 1.27 1.27 w INDICATOR 0.35 it h 0.25 M C B A 5 LANDPATTERNRECOMMENDATION V T o 2.65MAX SEEDETAILA le r a n 0.33 t C 0.20 In p 0.30 0.10 C u 0.75 0.10 SEATINGPLANE ts 0.25X45° a NOTES:UNLESSOTHERWISESPECIFIED n d (R0.10) A) THISPACKAGECONFORMSTOJEDEC O (R0.10) GAGEPLANE MS-013,VARIATIONAC,ISSUEE u t B) ALLDIMENSIONSAREINMILLIMETERS. p 8° 0.25 u 0° C) DIMENSIONSDONOTINCLUDEMOLD t s FLASHORBURRS. 1.27 D) CONFORMSTOASMEY14.5M-1994 0.40 SEATINGPLANE E) LANDPATTERNSTANDARD:SOIC127P1030X265-20L (1.40) DETAILA F) DRAWINGFILENAME:MKT-M20BREV3 SCALE:2:1 Figure 3. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX573 Rev. 1.6.1 9

7 4 Physical Dimensions (Continued) LC X 5 7 3 — L o w V o l t a g e O c t a l L a t c h w i t h 5 V T o l e r a n t I n p u t s a n d O u t p u t s Figure 4. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX573 Rev. 1.6.1 10

7 4 Physical Dimensions (Continued) LC X 5 7 3 — L o w V o l t a g e O c t a l L a t c h w i t h 5 V T o l e r a n t I n p u t s a n d O u t p u t s Figure 5. 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX573 Rev. 1.6.1 11

7 4 Physical Dimensions (Continued) LC X 5 7 3 — L o w V o l t a g e O c t a l L a t c h w i t h 5 V T o l e r a n t I n p u t s a n d O u t p u t s Figure 6. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX573 Rev. 1.6.1 12

7 4 Physical Dimensions (Continued) LC X 5 7 3 — L o w V o l t a g e O c t a l L a t c h w i t h 5 V T o l e r a n t I n p u t s a n d O u t p u t s Figure 7. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX573 Rev. 1.6.1 13

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