INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: •The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications •The IC06 74HC/HCT/HCU/HCMOS Logic Package Information •The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT139 Dual 2-to-4 line decoder/demultiplexer Product specification September 1993 File under Integrated Circuits, IC06

Philips Semiconductors Product specification Dual 2-to-4 line decoder/demultiplexer 74HC/HCT139 FEATURES GENERAL DESCRIPTION • Demultiplexing capability The 74HC/HCT139 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL • Two independent 2-to-4 decoders (LSTTL). It is specified in compliance with JEDEC • Multifunction capability standard no. 7A. • Active LOW mutually exclusive outputs The 74HC/HCT139 are high-speed, dual 2-to-4 line decoder/multiplexers. This device has two independent • Output capability: standard decoders, each accepting two binary weighted inputs • I category: MSI (nA and nA ) and providing four mutually exclusive active CC 0 1 LOW outputs (nY to nY3). Each decoder has an active 0 LOW enable input (nE). When nEis HIGH, every output is forced HIGH. The enable can be used as the data input for a 1-to-4 demultiplexer application. The “139” is identical to the HEF4556 of the HE4000B family. QUICK REFERENCE DATA GND = 0 V; T = 25(cid:176) C; t = t = 6 ns amb r f TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC HCT t / t propagation delay C = 15 pF; V = 5 V PHL PLH L CC nA to nY 11 13 ns n n nE to nY 10 13 ns 3 n C input capacitance 3.5 3.5 pF I C power dissipation capacitance per multiplexer notes 1 and 2 42 44 pF PD Notes 1. C is used to determine the dynamic power dissipation (P inm W): PD D P = C · V 2· f +(cid:229) (C · V 2· f )where: D PD CC i L CC o f = input frequency in MHz i f = output frequency in MHz o (cid:229) (C · V 2· f )= sum of outputs L CC o C =output load capacitance in pF L V =supply voltage in V CC 2. For HC the condition is V =GND to V I CC For HCT the condition is V =GND to V - 1.5 V I CC APPLICATIONS • Memory decoding or data-routing • Code conversion ORDERING INFORMATION See“74HC/HCT/HCU/HCMOS Logic Package Information”. September1993 2

Philips Semiconductors Product specification Dual 2-to-4 line decoder/demultiplexer 74HC/HCT139 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1, 15 1E, 2E enable inputs (active LOW) 2, 3 1A , 1A address inputs 0 1 4, 5, 6, 7 1Y to 1Y outputs (active LOW) 0 3 8 GND ground (0 V) 12, 11, 10, 9 2Y to 2Y outputs (active LOW) 0 3 14, 13 2A , 2A address inputs 0 1 16 V positive supply voltage CC Fig.1 Pin configuration. Fig.2 Logic symbol. (a) (b) Fig.3 IEC logic symbol. September1993 3

Philips Semiconductors Product specification Dual 2-to-4 line decoder/demultiplexer 74HC/HCT139 Fig.4 Functional diagram. FUNCTION TABLE INPUTS OUTPUTS nE nA nA nY nY nY nY 0 1 0 1 2 3 H X X H H H H L L L L H H H L H L H L H H L L H H H L H L H H H H H L Notes 1. H = HIGH voltage level L = LOW voltage level X = don’t care Fig.5 Logic diagram (one decoder/demultiplexer). September1993 4

Philips Semiconductors Product specification Dual 2-to-4 line decoder/demultiplexer 74HC/HCT139 DC CHARACTERISTICS FOR 74HC For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard I category: MSI CC AC CHARACTERISTICS FOR 74HC GND = 0 V; t = t = 6 ns; C = 50 pF r f L T ((cid:176) C) TEST CONDITIONS amb 74HC SYMBOL PARAMETER UNIT WAVEFORMS V +25 - 40to+85 - 40to+125 CC (V) min. typ. max. min. max. min. max. 39 145 180 220 2.0 propagation delay t / t 14 29 36 44 ns 4.5 Fig.6 PHL PLH nA toY n n 11 25 31 38 6.0 33 135 170 205 2.0 propagation delay t / t 12 27 34 41 ns 4.5 Fig.7 PHL PLH nEto nY n 10 23 29 35 6.0 19 75 95 110 2.0 output transition t / t 7 15 19 22 ns 4.5 Figs 6 and 7 THL TLH time 6 13 16 19 6.0 September1993 5

Philips Semiconductors Product specification Dual 2-to-4 line decoder/demultiplexer 74HC/HCT139 DC CHARACTERISTICS FOR HCT For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard I category: MSI CC Note to HCT types The value of additional quiescent supply current (D I ) for a unit load of 1 is given in the family specifications. CC To determineD I per input, multiply this value by the unit load coefficient shown in the table below. CC INPUT UNIT LOAD COEFFICIENT 1A 0.70 n 2A 0.70 n nE 1.35 AC CHARACTERISTICS FOR 74HCT GND = 0 V; t = t = 6 ns; C = 50 pF f f L T ((cid:176) C) TEST CONDITIONS amb 74HCT SYMBOL PARAMETER UNIT WAVEFORMS V +25 - 40to+85 - 40to+125 CC (V) min. typ. max. min. max. min. max. propagation delay t / t 16 34 43 51 ns 4.5 Fig.6 PHL PLH nA toY n n propagation delay t / t 16 34 43 51 ns 4.5 Fig.7 PHL PLH nEto nY n output transition t / t 7 15 19 22 ns 4.5 Figs 6 and 7 THL TLH time September1993 6

Philips Semiconductors Product specification Dual 2-to-4 line decoder/demultiplexer 74HC/HCT139 AC WAVEFORMS (1) HC : VM= 50%; VI= GND to VCC. HCT:VM= 1.3 V; VI=GND to 3 V. Fig.6 Waveforms showing the address input (nA )to output (nY ) propagation delays and the output transition n n times. (1) HC : VM= 50%; VI= GND to VCC. HCT:VM= 1.3 V; VI=GND to 3 V. Fig.7 Waveforms showing the enable input (nE) to output (nY )propagation delays and the output transition n times. PACKAGE OUTLINES See“74HC/HCT/HCU/HCMOS Logic Package Outlines”. September1993 7