74ACT11074 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCAS498A – DECEMBER 1986 – REVISED APRIL 1996 (cid:1) Inputs Are TTL-Voltage Compatible D, DB, OR N PACKAGE (cid:1) Center-Pin V and GND Configurations to (TOP VIEW) CC Minimize High-Speed Switching Noise (cid:1) EPIC(cid:2) (Enhanced-Performance Implanted 1PRE 1 14 1CLK 1Q 2 13 1D CMOS) 1-(cid:1)m Process 1Q 3 12 1CLR (cid:1) 500-mA Typical Latch-Up Immunity GND 4 11 V at125°C CC 2Q 5 10 2CLR (cid:1) Package Options Include Plastic 2Q 6 9 2D Small-Outline (D) and Shrink Small-Outline 2PRE 7 8 2CLK (DB) Packages, and Standard Plastic 300-mil DIPs (N) description This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs on the low-to-high transition of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the D input may be changed without affecting the levels at the outputs. The 74ACT11074 is characterized for operation from –40°C to 85°C. FUNCTION TABLE INPUTS OUTPUTS PRE CLR CLK D Q Q L H X X H L H L X X L H L L X X H(cid:3) H(cid:3) H H ↑ H H L H H ↑ L L H H H L X Q0 Q0 †This configuration is unstable; that is, it does not persist when either PRE or CLR returns to its inactive (high) level. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Copyright  1996, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

74ACT11074 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCAS498A – DECEMBER 1986 – REVISED APRIL 1996 logic symbol† 1 1PRE S 2 1Q 14 1CLK C1 13 1D 1D 3 1Q 12 1CLR R 7 2PRE 6 2Q 8 2CLK 9 2D 5 2Q 10 2CLR †This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V CC Input voltage range, VI (see Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA CC Maximum power dissipation at T = 55°C (in still air) (see Note 2):D package . . . . . . . . . . . . . . . . . . . 1.25 W A DB package . . . . . . . . . . . . . . . . . . . 0.5 W N package . . . . . . . . . . . . . . . . . . . . 1.1 W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. (cid:1) 2. The maximum package power dissipation is calculated using a junction temperature of 150 C and a board trace length of 750 mils, except for the N package, which has a trace length of zero. recommended operating conditions MIN MAX UNIT VCC Supply voltage 4.5 5.5 V VIH High-level input voltage 2 V VIL Low-level input voltage 0.8 V VI Input voltage 0 VCC V VO Output voltage 0 VCC V IOH High-level output current –24 mA IOL Low-level output current 24 mA (cid:1)t/(cid:1)v Input transition rise or fall rate 0 10 ns/V TA Operating free-air temperature –40 85 °C 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

74ACT11074 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCAS498A – DECEMBER 1986 – REVISED APRIL 1996 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS VVCCCC MMIINN MMAAXX UUNNIITT MIN TYP MAX 4.5 V 4.4 4.4 IIOOHH == –5500 (cid:1)(cid:1)AA 5.5 V 5.4 5.4 VOH 4.5 V 3.94 3.8 V IIOOHH == –2244 mmAA 5.5 V 4.94 4.8 IOH = –75 mA† 5.5 V 3.85 4.5 V 0.1 0.1 IIOOLL == 5500 (cid:1)(cid:1)AA 5.5 V 0.1 0.1 VOL 4.5 V 0.36 0.44 V IIOOLL == 2244 mmAA 5.5 V 0.36 0.44 IOL = 75 mA† 5.5 V 1.65 II VI = VCC or GND 5.5 V ±0.1 ±1 (cid:1)A ICC VI = VCC or GND, IO = 0 5.5 V 4 40 (cid:1)A (cid:1)ICC‡ One input at 3.4 V, Other inputs at GND or VCC 5.5 V 0.9 1 mA Ci VI = VCC or GND 5 V 3.5 pF †Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. ‡This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC. timing requirements over recommended ranges of supply voltage and free-air temperature (unless otherwise noted) (see Figure 1) TA = 25°C MMIINN MMAAXX UUNNIITT MIN MAX fclock Clock frequency 0 100 0 100 MHz PRE or CLR low 5 5 ttw PPuullssee dduurraattiioonn nnss CLK low or high 5 5 Data high or low 4.5 4.5 ttsu SSeettupp ttiimmee bbeeffoorree CCLLKK↑↑ nnss PRE or CLR inactive 2 2 th Hold time after CLK↑ 0 0 ns switching characteristics over recommended ranges of supply voltage and free-air temperature (unless otherwise noted) (see Figure 1) FROM TO TA = 25°C PPAARRAAMMEETTEERR MMIINN MMAAXX UUNNIITT (INPUT) (OUTPUT) MIN TYP MAX fmax 100 125 100 MHz tPLH 1.5 5.7 8.9 1.5 9.6 PPRREE oorr CCLLRR QQ oorr QQ nnss tPHL 1.5 6.6 11.3 1.5 12.5 tPLH 1.5 6 8.5 1.5 9.4 CCLLKK QQ oorr QQ nnss tPHL 1.5 5.7 8 1.5 8.8 operating characteristics, VCC = 5 V, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance per flip-flop CL = 50 pF, f = 1 MHz 30 pF POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

74ACT11074 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCAS498A – DECEMBER 1986 – REVISED APRIL 1996 PARAMETER MEASUREMENT INFORMATION From Output Under Test tw CL = 50 pF 3 V (see Note A) 500 W Input 1.5 V 1.5 V 0 V LOAD CIRCUIT VOLTAGE WAVEFORMS 3 V Input 1.5 V 1.5 V (see Note B) 0 V tPLH tPHL VOH T(simeein Ngo Itnep But) 1.5 V 3 V InO-Puhtapsuet 50% VCC 50% VCVCOL 0 V th tPHL tPLH tsu 3 V VOH Out-of-Phase Data Input 1.5 V 1.5 V 50% VCC 50% VCC Output 0 V VOL VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 W , tr =3 ns, tf = 3 ns. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 74ACT11074D ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ACT11074 & no Sb/Br) 74ACT11074DBR ACTIVE SSOP DB 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AT074 & no Sb/Br) 74ACT11074DG4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ACT11074 & no Sb/Br) 74ACT11074N ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 74ACT11074N & no Sb/Br) 74ACT11074NSR ACTIVE SO NS 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ACT11074 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) 74ACT11074NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) 74ACT11074NSR SO NS 14 2000 367.0 367.0 38.0 PackMaterials-Page2

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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,65 0,15 M 0,22 28 15 0,25 0,09 5,60 8,20 5,00 7,40 Gage Plane 1 14 0,25 A 0°–(cid:1)8° 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** 14 16 20 24 28 30 38 DIM A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065/E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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